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On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection
- Source :
- 3DIC
- Publication Year :
- 2019
- Publisher :
- IEEE, 2019.
-
Abstract
- For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for- Testability) method for TSVs using a modified boundary scan circuit with embedded Time-to-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a delay line. In this paper, for improving delay resolution, delay gates that have small propagation delay time are investigated and implemented as a delay line. In order to prevent pulse shrinking of transition signal through a delay line, the proposed cell is designed to reduce the difference in transition delay between the delay for rising transition and for falling transition. The measurement results for an experimental chip show the effectiveness of our new design.
- Subjects :
- Interconnection
Boundary scan
Pulse (signal processing)
Computer science
Design for testing
Three-dimensional integrated circuit
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
Propagation delay
Chip
020202 computer hardware & architecture
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
020201 artificial intelligence & image processing
Testability
Hardware_LOGICDESIGN
Subjects
Details
- Database :
- OpenAIRE
- Journal :
- 2019 International 3D Systems Integration Conference (3DIC)
- Accession number :
- edsair.doi...........ddf991588c2ccf5748aa6301659244d7