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Plasma position and shape parameters are essential for equilibrium control and physics analysis in a tokamak. Such information is often obtained via optical boundary analysis. In this study, a new analysis of the visible image histogram of a high-speed high-resolution camera is presented which can effectively distinguish between the foreground information (showing the plasma of interest) and the background information (showing the inside views of the vacuum vessel wall and flanges, and so on). Using this method, we can obtain a reasonable approximation to the plasma boundary close to the last closed flux surface (LCFS) where plasma brightness contrast is greatest. The reliability and accuracy of this method are checked by comparing it favorably with other algorithms for different plasma shapes. The method is successfully tested also when the outboard plasma boundary oscillates in time with a magnitude of 10%. [ABSTRACT FROM AUTHOR]

To improve the electrical performance of thin-film transistors with an atomic-layer-deposited Al2O3 dielectric/InOx channel, O2 plasma surface treatments of the InOx back channel are explored in comparison with thermal annealing. It is demonstrated that the O2 plasma treatment can enhance the device performance much more efficiently than thermal annealing, exhibiting an extremely low-thermal budget. Furthermore, it is revealed that the plasma treatment at a higher temperature can improve the device performance much faster than that at a lower temperature. For a 4 min O2plasma treatment at 200 °C, superior electrical characteristics are achieved, such as a field-effect mobility of 11 cm2V−1s−1, a threshold voltage of 0.9 V, a subthreshold swing of 0.38 V/dec, and good gate bias stress stabilities. This is ascribed to faster passivation of oxygen vacancies, removal of more C residues, and weaker surface damage and smaller surface roughness of the InOx back channel in comparison with long plasma treatments at lower temperatures. [ABSTRACT FROM AUTHOR]

In this paper, we study the effect of highly doped n^+/p^+ Si as the bottom electrode on unipolar RRAM with Ni-electrode/\HfOx structure. With heavily doped p^+-Si as the bottom electrode, RRAM devices illustrate the coexistence of the bipolar and the unipolar resistive switching. Meanwhile, by substituting heavily doped n^+-Si, the switching behavior changes to that of the self-rectifying unipolar device. The asymmetry and rectifying reproducible behavior in a n^+-\Si/HfOx/\Ni device resulted from the Schottky barrier of defect states in the \SiOx/\HfOx junction and n^+ Si substrate, but this behavior is not seen for the p^+-Si bottom electrode case. With rectifying characteristics and high forward current density observed in the \Ni/HfOx/\n^{+}\Si device, the sneak current path in the conventional crossbar architecture was significantly suppressed. We believe that the proposed structure is a promising candidate for future crossbar-type RRAM applications. [ABSTRACT FROM AUTHOR]

Raman measurement is carried out to understand Vth shift in single-layer graphene field-effect transistors (GFETs). The G (2D) peak shift in Raman spectra is correlated to the corresponding \Delta Vth during stress and recovery phases. A blue (red) shift of G and 2D peaks is seen during stress (recovery) phase, indicating the corresponding trapping (detrapping) effects in the graphene device. It is interesting to note that, after forming gas annealing (\H2/\Ar), the defects can be generated in graphene (evidenced by D peak of Raman spectra), leading to the increased \Delta Vth for both negative bias temperature instability and positive bias temperature instability in single-layer GFETs. [ABSTRACT FROM PUBLISHER]

Atomic layer deposited (ALD) \HfO2 resistive-switching random access memory devices with high uniformity, self-compliance, and forming-free behavior are demonstrated. Through comparative experiments, we find that appropriate deposition techniques and annealing conditions lead to self-compliance. The forming-free behavior originates from the oxygen deficiency due to the metal doping layer. High uniformity, by first-principle calculation, is caused by Ge doping in the \HfO2, which lowers the oxygen-vacancy formation energy. [ABSTRACT FROM AUTHOR]

In this brief, high-\kappa HfZrO (via atomic layer deposition) fabricated by a novel multideposition multiroom-temperature annealing (MDMA) technique in ultraviolet-ozone (UVO) ambient is systematically investigated by both electrical and physical characterization and is integrated with a TiN metal gate in a gate-last process. Compared with the conventional rapid-thermal-annealed sample, it is found that the device annealed via MDMA in UVO demonstrates the following: 1) more than one order of leakage current reduction at 25 ^\circ\C and 125 ^\circ\C without an equivalent oxide thickness penalty; 2) less susceptibility to stress-induced degradation; and 3) improved time-dependent dielectric-breakdown lifetime. Grain boundary suppression and healing of oxygen vacancies are believed to be responsible for the improvement, as evidenced by scanning tunneling microscopy and X-ray photoelectron spectroscopy analysis. [ABSTRACT FROM AUTHOR]

A new method is proposed to distinguish the contributions of the low-frequency noise (LFN) from the channel and the source/drain Schottky contacts in MOS devices. The method is applied to back-gated nMOSFETs with MoS2 channel and Al2O3 gate dielectric. To avoid a possible noise signal contamination from the top MoS2 surface by oxygen or water molecules absorption, the nMOSFETs with multilayer MoS2 are fabricated, and the measurements are carried out in the vacuum. The trap density Not at the MoS2/Al2O3 interface is derived for the first time using the proposed method. It is found that the Not responsible to LFN depends strongly on the surface potential, ranging from 4\times 10^10 cm ^\mathrm -2 in the weak over-drive region to 5\times 10^11 cm ^\mathrm -2 in the strong over-drive region. [ABSTRACT FROM AUTHOR]

A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence (∼tn) of interface-trap generation is observed. The index n is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics. [ABSTRACT FROM AUTHOR]

The magnet design, fabrication, and measurement of HIRFL-CSR (Heavy Ion Research Facility in Lanzhou Cooling Storage Ring) are presented. All magnets will be laminated and welded with an armor-coated surface between two big endplates made of sticking glue 0.5 mm-thick sheets. The dipole of CSRm was chosen an H type with an air circle on the pole to improve the field uniformity. The dipole of CSRe was chosen the C type with an air circle and two air slots on the pole to improve the field homogeneity. Its reproducibility of magnet to magnet was adjusted with inserting small laminating pieces before demountable pole ends to reach less than ±2 × 10-4 at optimized field level. CSRm quadrupoles diameter is 170 mm and has two different lengths, and its endplates were made with punching pieces after coating with epoxy glue, there is chamfered directly on the pole ends to reduce 12th-order contribution of field and without the demountable pole ends. CSRe main quadrupoles diameter is 240 mm and has two different lengths, and its endplates were also made with punching pieces coated with epoxy glue, there is also chamfered directly on the pole ends to reduce 12th-order contribution of field like CSRm. [ABSTRACT FROM AUTHOR]

Cooler Storage Ring (CSR) of Heavy Ion Research Facility in Lanzhou (HIRFL) consists of a main ring (CSRm) and an experimental ring (CSRe). Two particular C-type dipoles with embedded windings are used in the injection beam line of CSRm. They also act as the prototype dipoles of CSRe. The windings are designed to improve the field quality by their trimming current. The current impacts on field homogeneity and multipole components arc investigated by a hall sensor and a long coil, respectively. The experiment shows that a field homogeneity of ±1.0 × 10-3 can be reached by adjusting the trimming currents, though the multipole components change correspondingly. In our case, the quadrupole component is decreased to a low level with the octupole, decapole and 12-pole ones increased slightly when the trimming current is optimized. [ABSTRACT FROM AUTHOR]

In this letter, a bipolar resistive switching RAM based on \Ni/AlOy/\n^{+}\-\Si which exhibits high potential to realize transistor-free operation for cross-bar array is successfully demonstrated. The proposed device shows well-behaved bipolar memory performance with self-rectifying behavior in low-resistance state (> 700 at 0.2 V), a high on/off resistance ratio (> \10^3), a good retention characteristic (> \10^4\ \s at 100 ^\circ\C ), and a wide readout margin for cross-bar architecture (number of word line N > \2^5 for worst case condition). [ABSTRACT FROM AUTHOR]

In this letter, a unipolar resistive switching random access memory (RAM) based on \NiSi/HfOx/\TiN structure is demonstrated, which is compatible with NiSi S/D in advance CMOS technology process. Highlights of the demonstrated resistive RAM include the following: 1) CMOS-technology-friendly materials and process; 2) excellent self-rectifying behavior in low-resistance state (>\10^3 at 1 V); 3) well-behaved memory performance, such as high on/off resistance ratio (> \10^2) and good retention characteristics (> \10^5 \ \s at 125 ^\circ\C); and 4) wide readout margin for high-density cross-point memory devices (number of word lines >\10^6 for the worst case condition). [ABSTRACT FROM AUTHOR]

In this letter, we report positive bias-induced Vth instability in single- and multilayer graphene field effect transistors (GFETs) with back-gate \SiO2 dielectric. The \Delta Vth of GFETs increases as stressing time and voltage increases, and tends to saturate after long stressing time. In the meanwhile, it does not show much dependence on gate length, width, and the number of graphene layers. The \1/f noise measurement indicates no newly generated traps in \SiO2/\graphene interface caused by positive bias stressing. Mobility is seen to degrade with temperature increasing. The degradation is believed to be caused by the trapped electrons in bulk \SiO2 or \SiO2/graphene interface and trap generation in bulk \SiO2. [ABSTRACT FROM AUTHOR]

In this letter, a resistive random access memory based on Ni electrode/ \HfOx dielectric/\n^+ Si substrate structure is demonstrated, which can be integrated with Si diode as selector for application in crossbar architecture. The unipolar device shows well-behaved memory performance, such as high on/off resistance ratio ( > \10^3), good retention characteristics ( > \10^5\ \s at \150\ ^\circ\C), satisfactory pulse switching endurance ( > \10^5\ \cycles), and a fast programming speed of about 50 ns. More importantly, it also exhibits almost 100% device yield on a 6-in wafer. [ABSTRACT FROM PUBLISHER]

Scanning Kelvin probe microscopy (SKPM) is applied to experimentally understand the asymmetric behaviors in hole and electron transportation regions in graphene field-effect transistors (FETs). With gate modulation, the transition from p-p-p to p-n-p (for a Ag or Pd source/drain junction with graphene) or from n-p-n to n-n-n (for an Al source/drain junction with graphene) is verified by SKPM, which is believed to be responsible for the asymmetric transport. The odd resistance (Rodd) is positive for Ag (or Pd)/single-layer-graphene (SLG) FETs with \DeltaWFintrinsic > 0, while Rodd is negative for Al/SLG devices with \DeltaWFintrinsic < 0, where \DeltaWFintrinsic is defined as the work function difference between metal and intrinsic graphene. [ABSTRACT FROM AUTHOR]

In this letter, the temperature instability of HfOx-based resistive switching memory is investigated. It is observed that with the increase of high temperature (up to 100 °C in this work), the leakage current of high-resistance state would increase, and the set/reset voltages would decrease. In addition, multibit switching exhibited at room temperature might not be retained with the increase of temperature. All these phenomena can be correlated with oxygen-vacancy-related trap formation and annihilation. [ABSTRACT FROM AUTHOR]