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A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application. [ABSTRACT FROM AUTHOR]

The leakage current degradation, single-event burnout (SEB), and single-event gate rupture (SEGR) behaviors induced by the heavy-ion irradiation in p-Channel and n-Channel power U-shaped metal–oxide–semiconductor field-effect transistors (UMOSFETs) are comparatively investigated in this article via experiments and simulations. The SEB and SEGR performances of a commercially available −100-V-rated p-Channel UMOSFET are tested under heavy-ion irradiation. The experimental results show that the sample devices can be prevented from the drain leakage current or gate leakage current degradation under the bias conditions of $V_{\mathrm {GS}} = -100$ V and $V_{\mathrm {GS}} = 0$. However, a severe gate leakage current degradation can occur at $V_{\mathrm {DS}} = -100$ V when $V_{\mathrm {GS}} \ge 5$ V. In addition, the SEB and SEGR characteristics of a 100-V-rated n-Channel UMOSFET are obtained by simulations. The simulation results indicate that a p-Channel UMOSFET can achieve much better robustness against heavy ions compared with an n-Channel UMOSFET. Further, the leakage current degradation and failure mechanisms induced by heavy-ion irradiation are investigated via simulations. Finally, an effective method, which enlarges the width and depth of the source contact trench, is introduced to enhance the SEB tolerance of an n-Channel UMOSFET. The simulation result shows that the SEB threshold voltage can represent an increase of 23.1% with the hardening method. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance (${R}_{\text {on, sp}}$) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/ $\mu \text{m}$. However, the maximum temperature of the improved VDMOSFET is 2150 K when ${V}_{\mathrm {DS}}$ = 950 V. [ABSTRACT FROM AUTHOR]

In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations. [ABSTRACT FROM AUTHOR]

This article proposes an RC-IGBT structure with N-Si/n-Ge heterojunction (NNH-IGBT) to suppress snapback effect. Because the proposed N-Si/n-Ge heterojunction acts as a gradually reverse bias diode to suppress the electron flow into the N-short region, so the snapback effect can be suppressed. For the same ${\mathrm{\scriptstyle {ON}}}$ -state voltage drop (${V}_{\text {CE}}$), the turn-off loss (${E}_{\mathrm{\scriptstyle {OFF}}}$) of the NNH-IGBT is lower than the conventional RC-IGBT (Con-RC-IGBT). In addition, the reverse recovery speed of NNH-IGBT is nearly identical to the Con-RC-IGBT. Because of the use of heterojunction, the NNH-IGBT is suitable for operate to suppress the snapback effect, especially at low temperatures. [ABSTRACT FROM AUTHOR]

This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction (SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS (C-VDMOS), which indicated a severe degeneration threshold of 500 V. The SiC common SJ VDMOS (C-SJ VDMOS) was proven to be sensitive to high-energy heavy-ion and represents comparative SEB performance compared with the SiC C-VDMOS. The robustness of the SiC SJ VDMOS with different single buffer layer (SBL) designs against a heavy-ion was simulated. It is found that the maximum temperature in the source metal/SiC interface and bottom of the structure could be compromised by the thickness of the buffer layer. As a result, the SiC SJ VDMOS with an optimal SBL exhibited a severe degeneration threshold of 800 V, which was a 60% increase compared to the SiC C-SJ VDMOS. [ABSTRACT FROM AUTHOR]

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ($R_{ {on,sp}}$) of the SOI BP-LDMOS is 9.5 $\text{m}\Omega \cdot {\mathrm{ cm}}^{{2}}$ with a breakdown voltage (BV) of 229 V, which corresponds to a figure of merit (FOM) of 5.52 MW/cm2. The analysis of structural parameter optimization of the SOI BP-LDMOS under different doping concentrations in the drift region and P-pillar layer is conducted via numerical simulation. The results show that the tested sample can achieve about 80% of the maximal FOM. Finally, the experimental and numerical investigation of the total ionizing dose (TID) radiation effect on the BV shift is performed. The TID tolerance of the measured SOI BP-LDMOS can reach 300 krad(Si) to support a voltage of 200 V. Due to the electric field modulation hardening design, compared with the conventional hardened SOI LDMOS, the studied hardened BP-LDMOS can achieve a significant improvement in the TID tolerance from 225 krad(Si) to 525 krad(Si). [ABSTRACT FROM AUTHOR]

This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power metal–oxide–semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion’s strike position to SEB is proved to be the edge of the P+/P− JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure’s 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one. [ABSTRACT FROM AUTHOR]

In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/μm and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters. [ABSTRACT FROM AUTHOR]

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure. [ABSTRACT FROM AUTHOR]

This brief first time presents single-event burnout (SEB) simulation results for conventional AlGaN/ GaN gate field plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the first time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high field region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/ $\mu \text{m}$ striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ($\tau $) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected. [ABSTRACT FROM AUTHOR]