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This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller–Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases and calculating optimal weights, the SPD exhibits optimized phase-locking characteristic that maximizes the PAM-4 vertical eye opening (VEO) compared with the conventional logical approaches. In addition, unlike SS-MMPD, which may suffer from a severe multiple-locking problem, the SPD tracks a unique and optimal sampling phase even with an adaptive decision-feedback equalizer (DFE). For verification, a prototype PAM-4 receiver is fabricated in 40-nm CMOS technology and occupies 0.24 mm2. Tested with PRBS-7 patterns, it achieves a bit error rate (BER) of less than $10^{-11}$ and energy efficiency of 2.4 pJ/b at 48 Gb/s. [ABSTRACT FROM AUTHOR]

This brief presents a programmable phase detector (PD) for the Baud-rate clock and data recovery (CDR) in four-level pulse amplitude modulation (PAM-4) quarter-rate receiver, using a transition weighted gain (TWG) technique. By assigning a different gain to the phase detection for each data-level transition, the TWG-based CDR (TWG-CDR) achieves stable operation of the CDR and jitter tracking. An optimal phase detection transfer characteristic is obtained by assigning the highest weight on the 1-level data transition and the lowest on the 3-level transition. The proposed CDR fabricated in 40 nm CMOS technology performs at 64-Gb/s in PAM-4. The measured jitter tolerance (JTOL) shows that the TWG-CDR improves the horizontal eye opening margin compared to the sign-sign Mueller-Müller CDR. The TWG-CDR tested around a 6dB loss channel achieves a BER less than 10−11 and energy efficiency of 2.37 pJ/b. [ABSTRACT FROM AUTHOR]

This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the PCIe requires wide-range operation and compensation for high insertion loss. The proposed multi-rate CDR engine enables the receiver to operate with multi-rate clocking schemes according to the data rates, which does not need any additional high-speed analog circuits normally used for wide-range operation. In addition, the hybrid DFE architecture not only meets the DFE feedback timing constraint and but also reduces the equalization power. By using clock gating, the receiver can save power when operating at lower generations such as Gen 1, 2, 3, and 4. The prototype chip is fabricated in a 40-nm CMOS technology and occupies an active area of 0.14 mm2. The receiver achieves BER less than 10−12 with various PCIe channels, satisfying PCIe jitter tolerance masks. It consumes 62.7 mW at 32 Gb/s, compensating for 27.5-dB inserting loss, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.07 pJ/b/dB is achieved. [ABSTRACT FROM AUTHOR]

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initial clock frequency. The effect of the quadrature error is analyzed and verified by simulation. In addition, a frequency lock detector is implemented to control the loop gain for fast frequency acquisition. The prototype CDR circuit was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.045 mm2. The CDR circuit achieves a capture range from 4 Gb/s to 20 Gb/s, which is limited only by the oscillator operating range. The worst case acquisition time is 25 μs with a PRBS31 pattern. The CDR circuit achieves a BER less than 10−12 and an energy efficiency of 1.87 pJ/b. [ABSTRACT FROM AUTHOR]

This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than $10^{-12}$ in a wide range of data rates: 1.62–10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB. [ABSTRACT FROM AUTHOR]

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved. [ABSTRACT FROM AUTHOR]

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate all-digital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing is not perfectly aligned with the phase of the oscillator, the timing margin of the data sampler is reduced, resulting in the degradation of jitter tolerance (JTOL) performance. The proposed ILCDR achieves robust injection behavior over path mismatch variations by correlating the error information from the phase detector (PD) in the conventional phase-locked loop (PLL)-based CDR with the polarity of the data transition, thereby adapting the path delay of the injection pulse and placing it at the optimum timing. Fabricated in 28-nm CMOS technology, the proposed ILCDR occupies 0.03 mm2 and consumes 12.8 mW at 10 Gb/s with a 0.9-V supply voltage. The measured JTOL is 1 UIpp at 31 MHz with the target bit error rate (BER) of $10^{-12}$ in the presence of the initial path delay mismatch. [ABSTRACT FROM AUTHOR]

An injection-locked phase-locked loop (ILPLL) which continuously tracks the injection timing to achieve improved jitter performance is presented. When the injection timing is not precisely matched with the edges of the oscillator clock, the performance of ILPLL such as jitter and reference spur degrades significantly. To find an optimum injection timing, a calibration technique is proposed that continuously monitors the error information from the bang-bang phase and frequency detector when the injection of the reference clock is intentionally omitted every other cycle. The timing calibrator enables a robust ILPLL operation over the process, voltage, and temperature variations. The proposed ILPLL fabricated in 28-nm CMOS technology occupies 0.03 mm2and consumes 5.65 mW at 5 GHz with 0.9-V supply voltage. The measured jitter integrated from 1 kHz to 40 MHz is 152 fs, and the spur levels at the reference and 2nd subharmonic are −62 dBc and −53 dBc, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be −7.5 dBm at 21.2 Gb/s with an optical excitation, and $120~{\mu }\text{A}_{\text{pp}}$ at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b. [ABSTRACT FROM AUTHOR]

This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE). The adaptive DFE facilitates the best bit error rate (BER) performance for various losses of video cables. A differential-pair stage is added to the DFE for extending an effective DFE range, presetting a minimum data level, and calibrating a mismatch offset. Circuit techniques are proposed to relax timing constraints for the direct-feedback DFE architecture. A referenceless frequency acquisition is performed during a dedicated clock recovery phase. The measured BER at 10 Gb/s is lower than 10−12 with a 23-dB loss cable. The RMS jitter and the peak-to-peak jitter of a recovered clock are measured as 2.38 ps and 17.5 ps, respectively. The prototype chip is implemented in 65-nm CMOS technology and occupies an active area of 0.254 mm2. This receiver consumes 24.4 mW at 10 Gb/s, corresponding to the energy efficiency of 2.44 pJ/b, which is the lowest compared to other recently published video interface receivers. [ABSTRACT FROM AUTHOR]

A 1.62-to-8.1 Gb/s video interface receiver with an adaptive equalizer and a stream clock generator (SCG) is proposed. The adaptation logic is achieved by an edge-based adaptation and it controls the continuous-time linear equalizer ac boost. Using the adaptation logic, the minimum BER point is selected for several cables. The SCG consists of a phase-switching fractional divider and a delta–sigma modulator. The dividing factor is determined by the display resolution and the SCG operates up to 680 MHz which is the 4K UHD pixel frequency. The proposed receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.282 mm2. The measured BER is less than 10^-12 with a 20-ft-long video cable, whose insertion loss at 4.05 GHz is 20 dB. The receiver consumes 55.1 mW at the data rate of 8.1 Gb/s. [ABSTRACT FROM AUTHOR]