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We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged by fluorescence microscopy. Our method offers a manufacturable wafer-scale approach for CMOS-compatible bio-chip platform.

In this work we present a potential solution for forming ultra-shallow junctions with extremely low contact resistivities in which dopants are implanted into silicides and diffused to the semiconductor interface using low temperature anneals. Conventional silicide process requires a fine tuning of silicide thickness and deep source/drain doping profile to achieve low contact resistance and low source/drain diffusion sheet resistance. With the silicide implantation approach, we show that they can be engineered independently, providing a larger design space for the reduction of total external resistance. We demonstrate that contact resistance for NiPt silicide can be significantly reduced down to 7×10−9 Ω-cm2 for p+ Si and 6×10−9 Ω-cm2 for n+ Si by using Schottky Barrier Height (SBH) tuning through the implantation of B/As into pre-formed NiPtSi followed by low-temperature drive-in annealing (see Fig. 1 for the process flow). Moreover, we find that the same low contact resistance can be achieved for both heavily and moderately doped junctions, which grants an additional degree of freedom in junction design to reduce series resistance. With this technology, the ultra-shallow junction process can be simplified to the formation of ultra-thin silicide followed by shallow implantation and low temperature RTA (

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

In conclusion, we have demonstrated long and short-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation. Devices with alpha-Si show much higher transonductance and effective peak mobility of 3810 cm2/Vs. These results indicates that the alpha-Si layer has successfully passivated the III-V surface. Short-channel MOSFETs with gate length of 160 nm display record current of 825 mA/mm and peak transconductance of 683 mS/mm. These results are promising for realizing InGaAs-channel MOSFETs suitable for VLSI applications.

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10-8 Omega-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V/sub T/) and cell beta ratio (/spl beta/) are optimized for cell stability at these aggressive ground rules. The 0.143 /spl mu/m/sup 2/ 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V/sup DD/=1.0 V.

In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. >

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET. >

Ultra-low power operation of 0.1 /spl mu/m CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are carried out in a power supply-threshold voltage design space. Experimental results show a ring oscillator delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor=0.01) at 0.4 V. A 20X reduction in power/circuit is achieved at the same performance level as 0.25 /spl mu/m CMOS. >

We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.