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In this work, vertical NiO/Ga2O3 heterojunction diodes (HJDs) integrated with SiNx/Al2O3 double-layered insulating field plate (FP) structures have been demonstrated. With the additional post-annealing, the resultant diode exhibits a decreased differential specific on-resistance ( $\text{R}_{\mathrm{ on,sp}}$ ) of 5.4 $\text{m}\boldsymbol{\Omega } \cdot $ cm2 and an enhanced breakdown voltage (BV) of 1036 V. The improved performance is attributed by the combination of the FP-suppressed crowding electric field at the device edge and the reduced trap density at the NiO/Ga2O3 interface. In particular, the near-unity ideality factor has been achieved for this p-n HJD at an elevated temperature of 275 °C, indicating that the diffusion current is dominated. The high-temperature operation capability is owing to the quality improvement of NiO/Ga2O3 interface, where the Shockley-Read-Hall (SRH) recombination mediated by deep-level defects within the depletion region is thus suppressed.

This article analyzes the performance of pinned photodiode (PPD) for Time-of-Flight(ToF) applications on high resistivity epitaxial wafers. Due to its wide depletion region, high epitaxial resistivity PPDs feature some key advantages in collecting photogenerated charges. This article compares the demodulation contrast of the same pixel design on epitaxial wafers with different resistivity at near-infrared wavelength to analyze their performance. By comparing the simulated profile of pixels with different epitaxial resistivity, the characteristics of the PPD pixel on high resistivity epitaxial wafer when collecting photogenerated charges are concluded. This article also discusses the effects of using high resistivity epitaxial wafer with various design parameters. It is found that the use of high resistivity epitaxial wafer can greatly improve crosstalk performance, allow pixels to work at higher modulation frequencies, and enable large-sized pixels to have good demodulation capabilities.

With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (Nd) and substrate doping concentration (Psub) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (Vd), the turn-off nonbreakdown time (Tnonbv) of the device with higher Psub decreases faster. However, the Tnonbv with higher Psub is higher at low Vd. Therefore, the maximum Tnonbv can be obtained by optimizing Nd and Psub under a given Vd. In addition, Tnonbv is greatly reduced with increasing temperature.

High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV2/Ron,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the Ron,sp is reduced, yielding a significantly improved BV2/Ron,sp, together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, CGD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller VDS, which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.

The breakdown voltage model of Si-substrated AlGaN/GaN HEMTs with gate and drain field plates is proposed in this work. The silicon substrate and GaN buffer are considered as the depletion region in the modeling process. The analytical model shows great simplicity and veracity. It gives physical insights into the breakdown characteristics of the AlGaN/GaN HEMTs. The avalanche breakdown occurs at the field plate’s edge in lateral structure or at the interface in vertical structure. According to the analytical model, the relationship between the lateral breakdown and the vertical breakdown is demonstrated in this work. The breakdown location is affected by the variation of the structure parameters, including gate-to-drain distance, buffer thickness and field plates’ lengths. With the aid of the analytical model, effective guidance for device optimization to achieve high performance can be obtained.

This study presents a 2-D analytical model for the double gate tunnel FET (DG-TFET). The model considers the gate-on-source overlap that may occur intentionally or unintentionally due to fabrication tolerances. The 2-D Poisson's equation is solved in the main four regions of the structure, namely, the source, channel, drain, and the overlapped region inside the source. The mobile charge inside the channel is taken into consideration. In addition, the source and the drain depletion region lengths are precisely calculated by an iterative technique. Such crucial assumptions and calculations result in accurate expectations of the electrostatic potential. The energy band diagram could be extracted according to the obtained electrostatic potential, and, subsequently, the minimum tunneling width is computed. The impact of channel length and the overlap distance is thoroughly investigated. The results of the proposed model and Silvaco TCAD simulations are compared. The comparison satisfies a good agreement that verifies the validity of the presented model.

There is always a great demand for TFET analytical models to understand its underlined physics. One of the most widely known and citable models is the pseudo model as it gives satisfying results compared to TCAD simulations. However, the calculation of the depletion regions lengths is erroneous when using fully analytical solutions. The base on which the depletion regions is calculated should be revised to accurately model the electrostatic potential. In this work, we review the expressions that are based on pn junction assumption regarding the depletion regions lengths. A discussion is provided to prove the inability of the used equation to correctly predict the depletion lengths inside the source and the drain.

we propose electrically reconfigurable metamaterials (MTMs) at terahertz (THz) frequencies using InGaZnO (IGZO) Schottky barrier diodes, achieving a continuous amplitude modulation of 13%. The IGZO film was deposited at the capacitive gap of electric-field-coupled inductor-capacitor (ELC) MTMs. By sweeping the depletion region with DC bias, the averaged conductivity of IGZO film is changed, and thus the reconfiguration is accomplished. Upon varying the film conductivity, the simulated transmission can be modulated from 14.5 to -9.9 dB at 0.39 THz, corresponding to a modulation depth of 13%. Such active metamaterials address many attractive advantages, including not only low cost and simple fabrication process but also reasonable modulation depth and large area for several inch-scale.

A CMOS detector with the core transistors biased using negative body voltages is proposed to improve the quality of the sub-terahertz imaging system. The negative body voltage decreases the subthreshold slope by increasing the depletion layer, which can improve the voltage responsivity of the detector. The proposed detector consists of an integrated differential antenna, three parallel differential core transistors biased with differential body voltages, a preamplifier to combine the DC outputs as the current, and the main amplifier with a high voltage gain. The proposed detector fabricated on with TSMC 0.25 $\mu m$ mixed-signal CMOS process shows 2.6 times higher voltage responsivity and 2.9 times higher sensitivity than the detector biased with zero body voltages at the 200 GHz signal. The measurement results show the voltage responsivity of 5.7 MV/W and noise equivalent power of 62.4 p$\mathbf{W} / \sqrt{\mathbf{H} z}$ at the gate bias of 0.15 V and the body bias set (0, –0.2, and –0.4 V). The raster-scanned images using 200 GHz signals generated from the gyrotron achieve a signal-to-noise ratio (SNR) of 30.6 dB obtained from the proposed detector, compared with an SNR of 25.5 dB obtained from the zero-biased detector.

This work presents a study of the capacitance of asymmetric self-cascode silicon-on-insulator (ASC SOI) MOSFETs with similar gate areas and different gate lengths. Experimental results of total gate capacitance of different ASC are presented and complemented with the results of two-dimensional simulations. The transcapacitances are explored through two-dimensional simulations. Results show that different channel lengths of the composite transistors have more influence in the depletion region of the capacitance curves for low VDS. The gate-source and gate-drain capacitances show opposite trends with the change in the lengths of source and drain transistors, despite of the VDS applied.

The resistance degradation of sputtered doped lead zirconate titanate thin film resulting from the lowering of the Schottky barrier height was identified by current-voltage characterization over degradation. In addition to migration of oxygen vacancies, potential hole trapping of lead vacancies was observed by Thermally Stimulated Depolarization Current measurements. Both defects were proposed to increase the effective positive space charge density near the interface depletion region along degradation and be responsible for the resulting resistance degradation. This manifestation of defects in the resistance degradation was found to be separated in degradation time and dependent on the wafer position.

In high power Light-Emitting Diode (LED) illumination, the alternating current input and LED-compatible monolithic integration of the current regulator driver are demanded. In this work, we firstly report a novel GaN bidirectional current regulator by implementing the self-quantum channel modulation. This modulation is realized by the dynamic expanded space charge region in the p-type GaN layer, which squeezes the current channel, resulting in a stable current. The proposed regulator shows a prospective future in high-power LED illumination applications.

Semiconducting nanowires (NWs) are studied in field-emission (FE) for expanding electron gun performances and functionality in terms of stability, brightness and pulsed emission. Here we report on a pronounced double negative differential resistance (NDR) in the FE IV characteristics measured during photo-assisted field emission experiments on highly crystalline ptype silicon nanowires (NWs). The main feature is a double NDR in the current saturation regime, which can be modulated by both temperature and light intensity. These results contrast with previous FE studies in which only barely discernable single NDR was reported. Several mechanisms for the physical explanation of the NDR are currently under consideration : photo-generated carrier instabilities in the depletion region, which give raise to a pulsed space-charge current build-ups in the nanowire or the presence of a double quantum well formed by confinement near the Si nanowire apex. Because NDRs are signatures of pulsed currents, these results suggest new functionalities for which pulsed electron sources can potentially be achieved at high repetition rates.

A split-gate SiC trench MOSFET with a hetero-junction diode (HJD) is proposed and numerically analyzed in this paper. The proposed structure features the HJD to effectively suppress the turn-on of the parasitic body diode and reduce the depletion region in the JFET area. A P+ shielding layer surrounding the HJD and the gate oxide layer is used to alleviate the concentration of the electric field under the gate trench and improve the switching performance. As a result, not only the breakdown voltage is increased by 20.8% at the same level of the on-state resistance but also the miller charge and the switching loss of the proposed structure are reduced by 52% and 39.1%, respectively when compared with those of the conventional SiC trench MOSFET.

Four-terminal poly-Si thin-film transistors (TFTs), with a counter-doped body terminal connected to the floating channel, can suppress both dc and dynamic hot-carrier (HC) degradation of TFTs. With 3-D TCAD simulation, we clarify the underlying mechanisms of the suppression effect and analyze its dependence on the position and width of the body terminal. Under dc HC condition, a wider body terminal or that closer to the drain collects more holes generated from impact ionization in the drain depletion region and suppresses the parasitic bipolar junction transistor effect, subsequently reduces the kink current more effectively. Under dynamic HC condition, the body terminal injects holes at the end of the falling time of the gate pulse, partially removes the non-equilibrium state, significantly relieves the transient maximum electric field in the drain depletion region, thus suppresses the dynamic HC degradation. A wider body terminal can inject more holes and the holes injected by that closer to the drain diffuse to drain depletion region first, thus suppress the dynamic HC degradation better.

A Si photodetector with 2D grating structure is geometrically optimized to improve the absorption of light at near-infrared (NIR) wavelength range. The cell's width is 600 nm, with pillar and substrate thickness of 500 nm each. The periodic characteristic of light absorption allows the altering of the device's absorption spectrum by pillar width variation. The depletion region area is configured to allow optimum photogenerated current. Absorption peak of 0.17 is obtained at 370 nm pillar width, a ~146% improvement from the bulk absorption at 0.069, with cell responsivity reaching 17.7 nA/µm/W.

The performance of high-efficiency textured silicon solar cells is modelled within the thin-base approximation. In addition to the standard recombination mechanisms (Shockley-Read-Hall, radiative, and Auger), our approach includes the trap-assisted exciton Auger recombination and the space charge region recombination. A simple phenomenological expression is used for the photocurrent external quantum efficiency in the long-wavelength part of the absorption spectrum. The key parameters of textured silicon solar cells, such as short-circuit current, open-circuit voltage and photoconversion efficiency, are determined theoretically. They are in good agreement with the experimental results obtained for the heterojunction solar cells with the record efficiency of 26.6% produced by Yoshikawa et al. (2017). The theoretical optimal doping level and base thickness of these solar cells are found to be quite close to the experimental ones.

Various techniques may be employed for the excitation and control of micromechanical systems such as electrostatic or thermal transduction. However, most of these techniques require a dedicated driver circuit to provide the voltage or current levels needed for these actuators. On the other hand, the inefficiency of these techniques often necessitates the need for a local energy source. As such, options for remote operation of microactuators remain limited. Herein, we report on the first demonstration of direct optomechanical excitation of microstructures utilizing depletion region actuators. We demonstrate the possibility of using light to modulate the space charge density, and hence, the internal strain across the depletion region of regular p-n junctions. The modulation of strain across the junction can be effectively transformed into mechanical displacements. We show that the amount of force induced in the junction and the mechanical displacements can be controlled by varying the intensity of illumination. The produced strain does not scale when the device dimensions are reduced, making it a suitable actuation technique at nano-scales.

The reduction of the non-radiative recombination rate by modifying the solar cell structure without improving the material quality is discussed. Our calculations show that adopting a heterojunction design instead of a homojunction design can lead to a reduction of the non-radiative recombination rate in the depletion region due to formation of a depletion region in the wide–gap emitter material, which has a lower intrinsic carrier density. We experimentally confirm the relation between the non-radiative recombination rate in the depletion region and the carrier concentration in the wide-gap emitter layer.

We studied an advanced drift layer design which has an intermediate layer in mesa region for two-step-oxide field-plate MOSFET. The intermediate layer is formed by a high energy ion-implantation via source contact window. By TCAD simulation, it was confirmed the intermediate layer can decrease depletion layer capacitance in lower drain voltage. There was no change of breakdown voltage, and on-resistance (R ON A) increased slightly with increasing the implantation energy. An attractive effectiveness was obtained as gate-drain charge (Q GD ) decrease, and output charge and reverse recovery charge were slightly decreased. Evaluated performances showed that the Q GD and R ON Q GD were reduced by 14.1% and 10%, respectively. In power loss estimation of an assumed circuit, it was observed the newly designed FP-MOSFET can improve total power loss, especially in high-speed switching.

Electrochemical Nanoimprint Lithography (ECNL) works directly on semiconductor wafer, free of thermoplastic and photocuring resists, and without any auxiliary process. The principle of ECNL is the spatially confined electrochemical corrosion caused by the contact potential across the metal/semiconductor phase boundaries exposed to electrolyte solution. ECNL has been proved successful in fabricating various functional micro/nano-structures directly on gallium arsenide and silicon wafer. By virtue of photoelectric effect of semiconductors, the corrosion process can be well accelerated, and the ECNL efficiency is improved. The machining accuracy is determined by the diffusion coefficient of the holes and the corrosion rate of the semiconductor $(\mu=(\mathrm{D}_{\text{hole}}/\mathrm{k}_{\text{corr}})^{1/2})$ , which is usually smaller than the Debye length of the space charge layer at the metal/semiconductor phase boundary. Here we would like to report our recent progresses in ECNL.

3D integration (3DI) with bumpless Wafer-on-Wafer (WOW) technology is expected to be one of the most promising methods for improving device performance. One of the key points of this technology is how to reduce the Si as thin as possible without degrading the device characteristics. In this work, ultra-thin DRAMs with 5 µm- and 3 µm-thick Si wafers have been developed for WOW applications. The influences of Cu contamination and backside defects on device reliability were evaluated using 3 µm-thiek Si wafer for the first time. The backside defects were compared with thinning methods using grinding and chemical mechanical polishing (CMP), respectively. It was found that the refresh time according to the normalized failure rate below 10 -6 was shortened due to Cu contamination after CMP process. The refresh time was improved by increasing the thickness of the backside defects layer using grinding. However, these defects may cause degradation of the standby currents when the Si thickness closes to depletion region at 3 µm in thickness. Thus, it is important how to design the diffusion length of defects carefully to prevent incoming defects to depletion layer, taking the standby currents and the retention characteristics into account.

Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to digital circuits. We present here a novel reliability-aware compact modeling method that can accurately capture the full post-stress I-V characteristics of the MOSFET, taking into account the impact of drain depletion region on induced defects.

This paper conducts analysis to examine how pinned photodiode (PPD) performance improves on high resistivity epitaxial wafers for the Time-of-Flight (ToF) applications. High epitaxial resistivity PPDs feature crucial advantages in the collection of photogenerated charges because of its wide depletion region. The comparison is made in this paper for performance analyses at a near-infrared wavelength among the pixels of identical design on epitaxial wafers under different resistivities and demodulation contrast is used as performance metrics. The effects of high resistivity epitaxial wafer with various design parameters are also discussed in the paper, and the result shows that high resistivity epitaxial wafer significantly enhances crosstalk performance, allows pixels to work at higher modulation frequencies, and equips large-size pixels with well-performed demodulation capabilities.

THz and sub-THz radiation is useful in the radio astronomy field, medical visualization, surveillance etc. A novel two-terminal device is offered. It represents a diode containing active lateral border. The operation principle of the diode is usage of intervalley electron transfer and electron tunneling in tunnel junction of lateral border. The electronic processes that occur in diodes are considered. The one of a possible numerical model for analyze of electronic processes in the diodes has been proposed. It is based on applying the Ensemble Monte Carlo technique and generation of charge carrier rate due to tunneling effects. Some results are obtained via using the model for GaAs-based planar diode structure is represented.

Via the Sentaurus TCAD of 2D device simulation, the PN junction of Double-Gate Tunneling Field-Effect Transistor (PN-DGTFET) with the junctionless concept is investigated in this paper. The results demonstrate a PN-DGTFET of the source region completely overlapped with the gate region can effectively improve on-state current. This PN-DGTFET structure is major relies on the traditional band-to-band tunneling mechanism, and the minimum SS value can reach 8.83mV/decade, the average SS value can get 16.0mV/decade, the I ON /I OFF ratio can achieve $5.98 \times 10^{8}$ , and this device PN stack architecture can successfully reduce the manufacturing cost. Here, it can be found that reduction the drain region and parallel with the gate oxide layer, which can quickly create the depletion region and easily happen the tunneling switch-on state.

For development of high voltage power devices, it is very important to understand local heat generation phenomena of current filaments especially for reliability designs. Current filaments mean high density currents flow only in some parts of active cells and induce large heat generation locally. They appear when excessive current flows for some reasons during device switching. The aim of this paper is to clarify the following by using a modified avalanche model: The local lattice temperature dependence of impact ionization coefficients is a main factor in current filament movements, and the movements significantly suppress local heat generation. In particular, this tendency becomes even stronger when the ambient temperature is low and after the depletion layer reaches the buffer layer on the back surface side of IGBTs.

Negative capacitance FET is a promising CMOS technology booster which may break the limit of 60mV/dec in subthreshold swing (SS) without degrading performance. We investigated the physical mechanism of negative capacitance in ferroelectric FET (FeFET) by considering the dynamics of the polarization in ferroelectric gate insulator: transient negative capacitance (TNC). Polarization switching and depolarization effect are essential to cause negative capacitance effect, that is, apparent surface potential amplification in deep subthreshold region with small depletion layer capacitance. Moreover, unique features of reverse DIBL and negative differential resistance (NDR) are also reproduced by the transient negative capacitance theory. Modeling charged defect in FeFET, hysteresis-free sub-60mV/dec SS can be realized. TNC theory is regarded as a comprehensive framework to model subthreshold characteristics of FeFET.

In this paper, a novel superjunction IGBT with a depletion trench (DT SJ IGBT) is proposed and investigated by simulation. In the on-state, the depletion trench together with gate trench depletes the P-pillar between them and thus forms a hole barrier to realize an enhanced carrier store effect. Unlike the conventional (Con.) SJ IGBT, the DT SJ IGBT maintains bipolar conducting mode in the on-state even with high N/P pillar doping of $8 \times 10^{15}\mathrm{cm}^{-3}$. In the blocking state, P-pillar is shorted to P+ emitter and then protects the corner of trench gate from being prematurely breakdown. During the turning off, the depletion region between the two trenches gradually disappears and forms a hole extraction path to decrease $E_{off}$. Compared with Con. SJ IGBT, the $V_{on}$ is reduced by 38.8% at the same $E _{off}$ and almost irrelevant to pillar doping. Compared with SJ-IGBT with floating P-pillar (FP SJ IGBT), the DT SJ IGBT increases the BV by 19.7% and decreases the $E _{off}$ by 23.4% at the same $V_{on}$.

A lateral trench SiC MOSFET with lateral conduction on the side walls was designed using an ultra-narrowbody (UNB) sandwiched by the trench walls. The p-body is designed to be very narrow in order to avoid any depletion region formed in its body. The structure is similar to a FinFET, but applied to a SiC device. The body width in the channel region of the fabricated UNB MOSFET was 55 nm. The drain current of the UNB and conventional MOSFET were 1.27 μA and 0. 11μA, respectively, at $V_{D S}=30 V$. The UNB structure presented a significant increase in the mobility, reaching values of over 200cm2/Vs. The result indicated a very prominent FinFET effect, resulting in very high mobility and hence very significant improvement in the channel resistance of SiC MOSFETs.

A new double trench, buried-P junction termination extension (JTE) edge termination structure for 1200 V-class SiC devices is proposed and analyzed. The proposed structure features a short JTE followed by two trenches with buried-P layers. The trenches and buried-P layers work together with the JTE to facilitate the spreading of the depletion region toward the end of the edge termination. In particular, the electric field at the end of the JTE region will be reshaped by the first trench and subsequently the second trench, alleviating electric field crowding. Due to the electric field redistribution, the proposed structure can reduce the JTE dose sensitivity and widen the process window. A fabrication process has been designed. The JTE region and the buried-P layers are implanted simultaneously without extra masks. Simulation results show that the proposed structure can nearly achieve the ideal planar junction breakdown voltage of 1503 V with an edge width of only $17\mu \mathrm{m}$. Compared with the conventional guard ring structure, the edge width of the proposed structure is approximately five times shorter.

In this paper, a Feedback-MOS (FB-MOS) structure with C-SenseFET (FMC-SenseFET) is proposed. The FB-MOS region is connected to the Sense terminal of the C-SenseFET by the gate-drain short (diode) connection, which provides negative bias for the G2 terminal. When the temperature changes, the positive temperature characteristic of FB-MOS provides negative feedback for the current drift caused by the J-FET region, while the negative bias will change the width of the depletion layer in the J-FET region, which could further suppress the current drift. Compared with normal structure, the M (Current drift coefficient with temperature) of the charging current in the saturated region can be reduced by 53.8%, besides that, the proposed structure can generate a zero current drifting point at various temperatures in the linear region where the sampling function is realized, which could improve the temperature stability of C-SenseFET in two operating modes.

Introduction of pocket in TFET (Poc-TFET) is one of the most popular techniques to improve the performance of TFET devices. Pocket technique shows the best performance when it is optimally doped according to pocket width. However, when it is doped with smaller concentration to ensure complete depletion, TFET performance degrades drastically. In such a case, the work function engineering is generally employed to regain the lost performance. The work function engineering improves device performance to some extent but it still lag by several factor from the best performance that can be obtained by optimizing pocket doping and width. Also, employing the gate workfunction engineering increases the gate to drain capacitance (CGD). This increases overshoot/undershoot in circuits during switching event. In this paper we have analyzed the impact of the thickness of pocket and gate workfunction engineering at a constant doping. We also propose a double pocket technique which is better than gate workfunction engineering for achieving better ION without increasing CGD.

This paper studies the channel length effect on MAGFinFET. It is a new magnetic device which its structure is FinFET in nanometer scale. It detects vertical magnetic field like as MAGFET. The parameter is channel length of n channel FinFET which is varied at 10, 20, 30, 40 and 50 nm. The sensitivities at biased current 100 μA of varied channel length are 182.49, 186.41, 190.65, 197.22 and 201.00 nA/T, respectively. It depends linearly on the length of MAGFinFET like as MAGFET in micrometer scale. By comparing with bulk fin channel with the concentration 1015 cm−3, the sensitivity of MAGFinFET and fin resistor at biased current 100 μA are 190.65 and 153.50 nA/T, respectively. The current deflection of induced channel of FinFET is more sensitive than bulk resistor channel in same condition. The induced charges can deflect freely pass through depletion layer in thin fin channel by induced magnetic force not less than or better than in bulk resistor channel.

One of the most important parameter of a device is electrostatic potential. A fully analytical potential model shown the distribution of electrostatic potential in a Normally on Double gate Junctionless field effect transistor is presented. In a normally on device work function of gate is lower than that of channel. A negative gate potential is applied to create a depletion layer underneath the gate region to turn the device on. The potential expression is derived from solution of Poisson's equation while considering that flat band voltage is zero. The potential expression in the channel region and source-drain regions are obtained separately. The validation of the model obtained is done with comparison to simulation results obtained from Cogenda VisualTCAD 2-D device simulator. The results obtained from the analytical potential model closely matches with TCAD simulation results. As the model is fully analytical in nature it helps in reducing the computational time.

In this work, we propose surface potential and subthreshold current models for a buried metal layer based junction-less transistor, for the first time, and the proposed models are verified with the simulation results using Sentaurus TCAD. The buried metal layer (BML) induces the bottom depletion layer and its workfunction is important for volume depletion in OFF-state. The buried metal layer workfunction (ϕ BML ) required for full depletion is derived and its impact on short channel effects (SCE) and drain induced barrier lowering (DIBL) is studied. The scalability of the buried metal layer technology is benchmarked against the existing double gate architecture, using its natural length (λ), electrostatic integrity (EI), Vth roll-off and subthreshold slope (SS) as the figure of merits. It is found that the buried metal layer based junctionless transistor (BML-JLT) can be scaled higher than double gate (DG) provided ϕ BML ≥ ϕ BML,FD however, its subthreshold slope needs to be improved further.

The absorption of rear-side irradiance in bifacial solar cells affects carrier generation rates, recombination rates, and series resistance, increasing the complexity of quantifying bifacial cell performance. In this work, recombination rates and the electronic structure of textured bifacial silicon heterojunction solar cells are modelled in Synopsys TCAD Sentaurus. Front and rear illumination conditions vary in air mass from 1.5 to 10.0, while the effect of shifting spectrum and intensity due to snow and dry-grass albedo are applied to rear-side light. Recombination rates in the depletion region remain constant for different illumination scenarios, while throughout the bulk they are ∼1 order of magnitude larger for rear illumination compared to front illumination, resulting in a simulated bifaciality within 0.1% of experiment (97.4%). With increasing air mass, the average c-Si recombination probability varies by

A considerable amount of literature has revealed the effectiveness of surface passivation by charge carrier population control either using dopant profiles or charged dielectrics. Most studies assume that the substrate thickness is far larger than the space charge region. However, this assumption does not hold for nano-structured surfaces such as black silicon. In this work, we use one-dimensional modeling to understand the effect of nano-features on charge carrier population control by dielectric fixed charge $Q_{f}$ . We find that when $Q_{f}$ is smaller than $\sim 1\times 10^{11}\ \text{cm}^{-2}$ , the decreasing two-surface distance will effectively compress the space charge region and intensify the surface carrier asymmetry, which can be considered as an enhancement of charge carrier population control for surface passivation. Nevertheless, when the $Q_{f}$ magnitude is larger than $\sim 1\times 10^{11}\ \text{cm}^{-2}$ , the mirrored charge tends to concentrate at the near-surface region, and the space charge region compression is less effective. This leads to a reduced influence on the charge carrier population control and consequently little enhanced surface passivation.

This study focuses on how the performances of III-V cells with high-speed metalorganic vapor phase epitaxy (MOVPE) are affected by the cell structure: a conventional n-on-p (a thin highly doped n-emitter on a thick lightly-doped p-base), a rear junction (RJ) n-on-p (a thick lightly-doped n-emitter on a thin highly-doped p-base) and a rear hetero junction (RHJ; a thick lightly-doped n-emitter on a highly-doped p-BSF). For the 120-μm/h grown GaAs solar cells, dark current density (J dark ) corresponding to non-radiative recombination in a space charge region (n=2) and the consequent open circuit voltage (Voc) were significantly improved with RJ and RHJ structures. The reason was the lower defect density, most likely native point defects, in n-GaAs compared with that in p-GaAs. However, both short circuit current density and fill-factor were decreased in RJ and RHJ samples, and more accented in the latter. In the case of 30-μm/h grown InGaP solar cells, the RHJ (n-InGaP/p-InAIGaP) structure showed no advantage over the normal n-on-p device in terms of J dark and V oc , probably due to the abruptness/roughness of hetero interface. Nevertheless, the RHJ structure has a good potential for high speed MOVPE growth of multiple junction solar cells because of its simple structure with smaller number of interfaces.

In this paper we present results of DLTS investigating HIT solar cells. Analysis of DLTS spectra gave deep level activation energies and concentrations. However this method hardly allows to find spatial localization of these defect states. Therefore here we developed a method to find separated values of recombination rates corresponding to different spatial regions: a-Si layers, interfaces, depletion region and quasineutral base. We quantity found that recombination in the depletion region and at the interfaces strongly dominate and affect efficiency of the cell. Here we show that this technique is useful for interpretation of DLTS data and investigation of recombination processes in HIT solar cells.

Two-dimensional current flow in the lightly-doped resistive region in a lateral double-diffused MOS (LDMOS) transistor was analyzed through 2D device simulation. While retaining its theoretical backbone of HiSIM_HV, the industry-standard surface-potential-based compact model for high-voltage MOSFETs, a conceptual extension is explored. Owing to a smooth transit of current flowlines from the channel to the lightly doped region adjacent to the channel of the intrinsic MOSFET part of LDMOS, the surface accumulation occurring at the gate-overlapped surface of the lightly doped resistive region is regarded as an extended channel rather than an extended drain. The channel offset length (ΔL) can be expressed within the framework of the drift-diffusion model and can be related with a characteristic quasi-Fermi voltage V dive where accumulation current flowlines have already completely dived away from the surface. The HiSIM_HV’s internal drain node (DP or alternatively d’) is regarded as being placed at an opening bounded by the gate-controlled transverse and the drain-controlled lateral extension of depletion region, while many compact models place DP at the boundary between the channel and the lightly doped region. The intrinsic MOSFET’s effective drain voltage (V dseff ) is related to gate controlled V dive rather than the quasi-Fermi voltage (V dp ) at DP. Hence, a difficulty in that the intrinsic MOSFET’s drain voltage stays almost as high as externally applied drain voltage at the off-state, while it suddenly drops at the onset of on-state of the intrinsic MOSFET part is expected to be mitigated.

It was detected that during irradiation by fast neutrons and electrons the solar cells I – V characteristics shift to the decreasing current and voltage area. The short circuit current decreases from the 582 mA to 533 mA for neutron and upto 544 mA for electron influence. SCs degradation according to I ShC is caused by a decrease in the lifetime and diffusion length in the minority charge carrier structure, which is associated with the recombination centers appearance in the SC base. The most noticeable changes in I – V characteristic are detected at the influence by fast neutrons with a dose more than 6.5 1012 cm-2 and at an electron dose more than 1014 cm-2. Due to the decrease in the operating parameters of solar cells, the efficiency decreases from 21.1 % to 16.3 % for neutron irradiation and upto 17.8 % for electron one. U OC changes are caused by a decrease in the diffusion length of charge carriers. This is due to an increase in the saturation current under the decrease influence in the charge carrier diffusion length (with an increase of the generation component in the space charge region).

Carrier densities in heterostructure solar cell are analytically computed by solving Poisson’s equation where diffusion length is approximated as Gaussian distribution. The root cause of variable diffusion length estimation is that all the generated carriers within the depletion region can’t reach the external contact due to different loss mechanisms, and therefore a certain percentage can contribute to current. Moreover, generated minority carriers are considered as a function of widths for both the material layers, and result is worked out under realistic considerations. Variation of incident wavelength is measured on the carrier densities, and result is computed with that obtained for homojunction device. These findings will help to compute current for quantum wellbased solar cell close to actual findings.

Ge photodiodes with ultra-high responsivities have been demonstrated with gold nanoparticle assistance. The responsivity can reach a value of 37.7 A/W, which corresponds to a gain of 76. Such a high responsivity originates from the amassment of photo-generated holes in Ge under the boundary of gold nanoparticles, which reduces the barrier for electron tunneling from metal to the hole-amassment Ge ring areas. The depletion layer thinning due to hole amassment is not only proved by band diagram simulation but also confirmed by capacitance measurement.

This paper proposes an optimal 4H-silicon carbide trench MOS barrier Schottky (TMBS) Rectifier. The optimal structure of this rectifier is achieved by adding an N− wrapping region at the P+ shielding of the conventional TMBS structure, which significantly reduces the depletion region formed by the P+ shielding region. As a result, the proposed structure provides a lower ON-resistance comparing with the conventional P+ shielding structure. Moreover, we study the electric characteristics of the proposed structure via numerical simulation. Such a structure improves the specific ON-resistance and figure of merit of the conventional P+ shielding TMBS by 32.2% and 48.4%, respectively, and offers a high breakdown voltage, i.e., up to 1908 V.