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TiN/a-Si/TiO x /TiN RRAM devices show non-linear I-V characteristics with analog and self-compliant switching. The non-filamentary switching is significant only above a current threshold, as determined using a soft breakdown detection technique. Pulse monitoring and a-Si thickness variation experiments confirm that the current through the device is the dominant driving force for defect profile modulation in the TiO x switching layer. The current-accelerated defect movements results in self-compliant switching, eliminating the need for external current compliance for these devices.

This paper presents a LDMOS high power high gain peaking device with an optimized pre-matching network implemented in a half 10×32mm air cavity plastic package. This peaking device allows the one package Doherty solution achieved 57.5dBm peak power in the 1.805-1.88 GHz band, and >53% efficiency, >17.5dB gain with 9.9PAR WCDMA signal at 8dB OBO with a classical asymmetrical 2 ways Doherty circuit. This Doherty could be linearized at −57 dBc level with 60MHz 2-carrier LTE signal.

Amorphous Vacancy Modulated Conductive Oxide resistive switching devices (TiN/a-Si/TiOx/TiN) are attractive for storage class memory applications due to their self-rectifying and self-compliant characteristics with low current switching. However, the endurance is intrinsically limited to 103 cycles. Using specific experiments and insights from kinetic defect distribution models, we identify two modes of failure - first, window closure to the middle due to defect loss and profile symmetrization as the consequences of current and field driven-defect profile modulation, respectively, and second, excess defect generation at higher bias culminating in dielectric breakdown. Based on these findings, we suggest improvement to the device stack.

We report high performance, dry etched In 0.53 Ga 0.47 As vertical nanowire and vertical nanosheet devices, fabricated using a VLSI compatible process flow. Scaling the effective-oxide-thickness in combination with (NH4)2S channel treatment and forming gas anneal improves the device performance, in terms of Q (Gm/SS), by over 55%. At V DS = 0.5V, the devices exhibit a minimum SS = 63mV/dec, I on = 397μA/μm at Ioff = 100nA/μm, peak Gm = 1.6mS/μm and maximum Q = 21. These values are the best reported in literature for vertical IIIV devices. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the process flow does not introduce additional interface defects.

We report record breaking values for PMOS source drain (S/D) contact resistivity, ρ c 0.4 Ge 0.6 in combination with subsequent pulsed nanosecond laser anneal (NLA). Cross section transmission electron microscopy (XTEM) shows the pc reduction mechanism is based on Ga and Ge segregation towards the surface.

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

Amorphous Vacancy Modulated Conductive Oxide resistive switching devices achieve non-localized low current switching by electrical modulation of defect distribution. We present for the first time a quantitative model to explain the operation of these devices. The defect movements are accelerated by lowering of potential barrier under electric field. Using this model, we successfully explain the observed switching characteristics of gradual and analog switching, reset during set bias due to over-programming, along with some insight on the fresh state. We also elucidate its endurance and retention characteristics and discuss a methodology to estimate the number of defects responsible for switching.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

Vertical nanowires and for the first time vertical fins, dry etched from the same lattice matched InGaAs on InP, are used to fabricate MOSFETs. Single and multiple pillar array devices exhibit excellent electrostatics with min SS = 68mV/dec (V DS =0.05V) and max G m = 580µS/µm (V DS =0.4V). These are the first IIIV pillar array devices fabricated with top-down approach. Linear I on scaling with effective width and overall V th uniformity makes this result the first step in assessing the manufacturability of this integration scheme. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the IIIV etch does not introduce additional interface defects.

In 0.53 Ga 0.47 As quantum-well (QW) MOSFETs with a novel interfacial layer(IL)/high-k stack on an improved interface were fabricated. Excellent device characteristics (SS∼72mV/dec, I on /I off >106 at V ds =0.5V, DIBL∼26mV/v for a device at EOT∼1.25nm) were obtained. In addition, EOT was scaled down to 1.0 nm without a significant degradation in electrical properties. The extracted field-effect mobility (peak μ eff ∼3100 cm2/V-s for EOT∼1.25nm and μ eff ∼ 2400 cm2/V-s for EOT∼1.0nm) is the highest split C-V mobility reported for surface channel In 0.53 Ga 0.47 As MOSFETs at such small EOT. We demonstrate a record reliability performance using the new IL with an overdrive voltage, V ov ∼0.5V for a 10 year operation (with maximum ΔV th =30mV) at EOT∼1.25nm. We attribute this performance enhancement in mobility to reduced surface roughness (extremely smooth surface) and remote phonon scattering (due to IL), and improvement in reliability to enhanced energy misalignment between defect bands in high-k and charge carriers in the semi-conductor respectively.

Nanoscopic details of the conduction in 3D NAND vertical channels are unraveled by a novel slice-and-view tomographic technique, Scalpel SPM. The structural and electrical properties of poly-Si and single crystalline In 1−x Ga x As of 45 nm channel diameters are explored/revealed. The impact of the grain boundaries (GBs) in poly-Si and of the material segregation in In 1−x Ga x As are shown, thus providing a direct correlation between the channel materials and the electrical performance of the device.

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W NW ≤25nm, H NW ∼22nm), with increased doping enabling ION improvement without I OFF penalty for W NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V T mismatch performance shows higher A VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d NW ≥20–30nm), integrated on the same 300mm Si platform as lateral devices. Low I OFF , I G , and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ c ) of ∼2×10−9 Ω·cm2 on Si 0.3 Ge 0.7 :B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage over MIS. On n-type substrates, on the one hand, we find MIS contacts have relatively high contact resistivity despite the low Schottky barrier height; the low thermal stability of MIS is also worrying. On the other hand, with MS contacts, we use a pre-amorphization based Ti silicidation technique and achieve contact resistivity of 1.5×10−9 Ω·cm2. Therefore, for both NMOS and PMOS, we confirm that MS contacts are still the prevailing contact scheme. Advanced MS interface engineering is able to help reach the target contact resistivity required by advanced CMOS technology.

This paper introduces the investigations on ultralow metal/semiconductor contact resistivity (ρc). First, we build a multiring circular transmission line model (MR-CTLM), a novel ρc test structure with simple process and high accuracy for rigorous ρc study. Based on that, we explore process options to achieve ultralow ρc on n-Si. We obtain high carrier concentration of ∼9e20 cm−3 by in situ P doped Si:P epitaxy followed by ms laser annealing. Besides, we use a pre-contact amorphization plus Ti silicidation technique to fabricate TiSix/Si:P contacts and achieve ultralow ρc of 1.5e–9 Ohm.cm2. Finally, we discuss sub-1e-9 Ohm.cm2 ρc solutions for future CMOS technology node.

Vacancy Modulating Conductive Oxide resistive switching devices use electrical modulation of the defect profile to vary the conductance of tunneling barrier, thereby operating with self-rectification and self-compliance. They have been demonstrated to show low switching current with area scalability, indicating non-filamentary switching, and thus making them very promising candidates for high density memory applications. In this work, we report on room temperature and higher temperature retention, with extensive study on parametric dependence — the impact of electrical, material, and process parameters. In addition, we highlight differences with respect to filamentary switching, and suggest directions for improvement.

Epitaxially grown In1−xGaxAs is integrated for the first time as replacement of polycrystalline silicon (Si) channel down to 45 nm diameter for 3-D NAND memory application. Channels with different compositions are obtained after careful surface preparation by tuning growth conditions such as: temperature, choice of precursors and flow ratio. In1−xGaxAs shows superior conduction properties than poly-Si channel: higher Ion and transconductance (gm). Potentially good memory operations are also found.

© 2015 IEEE. Record-low contact resistivity (pc) for n-Si, down to 1.5×10-9 Q-cm2, is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the pc for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the pc reduction. In situ doped Si:P with P concentration of 2×1021 cm-3 is used as the substrate, and dynamic surface anneal (DSA) boosts P activation. In addition, TiOx based metal-insulator-semiconductor (MIS) contact is also studied on Si:P but is found to suffer from low thermal stability. ispartof: pages:592-595 ispartof: IEEE International Electron Devices Meeting - IEDM vol:2016-February pages:592-595 ispartof: IEEE International Electron Devices Meeting - IEDM location:Washington, D.C. USA date:7 Dec - 9 Dec 2015 status: published

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

This work reports a TiN coated contact implemented in a vertically actuated SiGe-based Nano-Electro-Mechanical (NEM) relay. It is shown that covering the bottom of the movable SiGe beam (the armature) with a TiN layer in the contact region will improve the contact performance of the relay with lowering the on-resistance, R ON , by around 4 orders of magnitude and by enhancing the number of switching cycles without degradation. This NEM relay provides an optimal combination of small motional volume (∼0.02µm3) and long mechanical lifetime (> 1010 in vacuum). Furthermore, with a total contact area of 0.01µm2 (among the smallest reported so far), an on-resistance of ∼1MΩ has been achieved.

In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.

Epitaxially grown Si and Si0.6Ge0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub threshold swing and transconductance (gm). The experimentally observed gm bimodal distribution for epi Si is corroborated and explained through a resistive network model: lower gm conduction occurs when current needs to cross a high resistance boundary, whereas higher gm is obtained when this boundary is not present.

Silicon photonics (SiPh) has been identified as a prime technology targeting cost-effective short-range optical links [1]. Wavelength-division multiplexing (WDM) is an attractive approach for enabling high aggregate transceiver bandwidth without increasing the number of optical fibers used in the link. Ring-based optical modulators and wavelength-selective filters are attractive devices for scalable WDM SiPh transceivers owing to their compact footprint and moderate power required for thermal tuning. In this paper, we report on a thermally controlled ring-based flip-chip integrated CMOS-SiPh transceiver with 4 channels operating at 20Gb/s.

Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

Nominal L G VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the L G is possible and it results in an extra 27% in I EFF in comparison to the nominal L G case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.

Error-free operation is demonstrated up to 20Gb/s for a TIA consisting of seven cascaded inverter-based gain stages in 40nm (LP) CMOS technology, with a current sensitivity of 70μA and an energy efficiency of 575fJ/b.

This paper demonstrates functional NEM cantilever relays fabricated in a CMOS-compatible low-T (400°C) CVD SiGe process flow. Devices with a length in the micrometer range (

The historical built environment is acknowledged as a valuable but complex material and cultural resource that needs to be preserved. Digital technologies give the opportunity to improve and expand the comprehension of the complex artefacts present in this built environment. Building information modelling (BIM) and semantic web technologies are two technologies that are often used for the documentation of the built environment and of cultural heritage resources. With our research, we investigate to what extent those technologies can be integrated and which advantages this combination can produce for the analysis and interpretation of our built environment. In this paper, we present the application of BIM software and semantic web technologies to a case study: the Book Tower in Ghent, Belgium. The Book Tower is one of the most important early 20th century buildings in the city of Ghent. Through the paper we will show how BIM and semantic web technologies were integrated, which advantages this combination can produce and which future developments could be considered. The recorded information can be essential to plan and manage a recovery plan and/or a maintenance program taking into consideration also aspects linked to cultural diversity and environmental sustainability.

This paper presents a design approach for Nano-ElectroMechanical Structures (NEMS) relays taking Casimir or van der Waals forces into account for the static and dynamic modeling of the devices. The goal is to design these structures using the Poly Silicon Germanium process, with several fabrication constraints on the gap, the structure thickness and the critical dimensions. The design approach starts with an analytical study taking the general expression for adhesion forces into account. Considering the van der Waals forces, finite element simulations performed on a simple cantilever confirm these analytical results. More complex structures are then designed, such as cantilevers with larger plates and torsion actuators, in order to increase the performance of the devices and to avoid permanent stiction. Inverters as well as NAND gates are designed and optimized to reach CMOS-equivalent specifications and finally a ring oscillator based on the new inverter and NAND gate is proposed.