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SRAM-based Field Programmable Gate Arrays (FPGAs) represent an attractive solution for mission-critical computationally intensive applications due to their high integration, flexibility, and computational capabilities. However, the static memory cells of SRAM-based configuration memory present a high sensitivity to radiation effects. Due to the increasing interest in using these devices in radiation environments such as aerospace and high energy physics, the evaluation of their reliability through radiation tests is a key role in their validation. Radiation Testing consists in exposing the physical device to radioactive source or radiation beams and represents an accurate solution for evaluating the device sensitivity. However, this implies high costs both in terms of experimental setup and money due to the low availability of the required facilities. Among the possible solutions, neutron generator testing would represent an efficient solution even if challenging from the instrumentation needed for the experimental setup. In this work, we present a test instrumentation and methodology specific for cost-effective short-time neutron generator testing to efficiently evaluate FPGA radiation-induced soft error sensitivity.

Radiation-induced single-event transients (SETs) are the leading cause of mal-operations in CMOS nanometric integrated circuits. The increasing complexity of advanced CMOS digital circuits makes SET effects investigation a rising challenge. In this work, we propose a 3-D-oriented simulation approach able to model the passage of heavy ion particles through the physical structures of modern digital circuits implemented with ultrananometric manufacturing processes. The proposed approach is able to generate the transient voltage pulse in response to a heavy-ion track and identify the effects of the sensitive volume and contact structure. We present heavy-ion radiation test experiments performed on a 65-nm Flash-based CMOS technology process and, as proof-of-concept, we successfully compared the SET cross sections showing comparable results.

Generalized minor component analysis (GMCA) is of great use in modern signal processing. The GMCA algorithms can be simplified to extract the minor generalized eigenvector of the autocorrelation input matrices pencil. In contrast to batching methods, the Hebbian-rule-based algorithm can extract the minor generalized eigenvector online. Few Hebbian-rule-based GMCA algorithms have been reported in the literature, and most of them are not self-stabilizing. Thus, a novel algorithm for GMCA, which is advantageous in terms of good convergence speed, self-stabilizing property, and multiple generalized minor component extraction in sequence, is proposed in this paper. A theoretical analysis verifies these properties via matrix theory and the deterministic discrete-time method. Numerical simulations are conducted to further demonstrate the advantages of the proposed algorithm.

In recent years, topics around machine learning and artificial intelligence (AI) have (re-)gained a lot of interest due to high demand in industrial automation applications in various areas such as medical, automotive and space and the increasing computational power offered by technology advancements. One common task for these applications is object recognition/classification whose input is usually an image taken from camera and output is whether an object is present and the class of the object. In industrial pipeline, this task could be used to identify possible defects in products; in automotive application, such task could be deployed to detect pedestrians for Advanced Driver-Assistance Systems (ADAS). When the task is safety-critical as in automotive application, the reliability of the task implementation is crucial and has to be evaluated before final deployment. On the other hand, Field Programmable Gate Array (FPGA) devices are gaining increasing attention in the hardware acceleration part for machine learning applications due to their high flexibility and increasing computational power. When the SRAM-based FPGA is considered, Single Event Upset (SEU) in configuration memory induced by radiation particle is one of the major concerns even at sea level. In this paper, we present the fault injection results on a Convolutional Neural Network (CNN) implementation on Xilinx SRAM-based FPGA which demonstrate that though there exists built-in redundancy in CNN implementation one SEU in configuration memory can still impact the task execution results while the possibility of Single Event Multiple Upsets (SEMU) must also be taken into consideration.

In recent years, three-dimensional IC (3D IC) has gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation and achievable clock frequencies. However, the reliability of 3D ICs regarding soft errors induced by radiation is not investigated yet. In this work, we propose a method for evaluating the sensitivity of 3D ICs to Single Event Transient induced by Heavy Ions. The flow starts with identifying the characteristics of the generated transient pulses with respect to the radiation profile and 3D layout of the design. Secondly, our method provides a Dynamic Error Rate using a Simulation-based Fault Injection environment. Experimental results achieved applying the approach on a 15nm 3D configurable Look-Up-Table (LUT) designed on two tiers demonstrated the feasibility of the method, showing the vulnerability characterization of four different functional configurations using eight different types of heavy ions.

Partial least square (PLS) is a multivariate statistical analysis method which can distinguish the quality-related and quality-unrelated spaces. Modification of PLS (MPLS) is an improved algorithm for PLS. However, MPLS has the disadvantages of large amount of calculation in batch modeling and cannot overcome the dynamic disturbance in process monitoring. In order to solve this problem, we propose an adapt recursive modified latent structure (AR-MPLS) algorithm, which uses recursive structure to extend to the dynamic domain. Finally, we use the Tennessee-Eastman process to verify the effectiveness of the proposed algorithm in the dynamic domain.

In the time-varying industrial process, the quality of the product is crucial. The existing batch partial least squares (PLS) monitoring model can effectively monitor quality-related faults. In process monitoring, in order to overcome time-varying disturbances, the monitoring model needs to update regularly. How to update the monitoring model efficiently is a serious problem. This paper proposes a recursive concurrent projection to latent structures (RCPLS) algorithm, which can update models more efficiently with historical model parameters and new data, and can also provide better quality-related fault monitoring results than static concurrent projection to latent structures (CPLS). The updated computational quantities of the RCPLS model and the CPLS model are compared through the Tennessee Eastman Process (TEP). The effectiveness of the RCPLS algorithm is verified, and a comprehensive comparison of the quality-related fault detection capabilities of RCPLS and CPLS is performed. The results show that RCPLS can significantly reduce the computational burden and increase monitoring effectiveness.

An adaptive Nesterov acceleration gradient (NAG) algorithm is first developed to extract single generalized principal component (GPC) corresponding to the largest eigenvalue of a stationary sample autocorrelation matrix pencil. A deflation technique enables the proposed algorithm to extract the higher-order GPCs. The proposed algorithm enjoys the advantages of a lower computational load and a highly modular structure for efficient implementation. Simulation results are given to demonstrate the effectiveness of the proposed algorithm for extracting multiple generalized principal components.

General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video processing thanks to their powerful parallel architecture. In the last years, GPGPUs have been considered also for safety-critical applications, such as autonomous and semi-autonomous car driving systems. New GPGPU devices include an increasing number of parallel cores in order to increase throughput and performance. This increment in the number of cores and the requirements in terms of power consumption force designers to use aggressive semiconductor technologies.Nevertheless, those new devices can be seriously affected by radiation effects, modeled as Single Event Upsets (SEUs). SEUs could generate unexpected operation effects in the applications which could be unacceptable for the safety-critical ones. This work analyzes the SEU effects resorting to an open-source model of a GPGPU based on the Nvidia’s G80 architecture and aims at complementing previous analysis based on radiation experiments

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. The decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.

General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applicationssuch as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field.Functional tests adoptingSoftware-based Self-test(, orSBST)are an effective solution since they providebenefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to knownmethods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions.This paper focusesOonone of the most relevant module consists on the scheduler corewhich is in charge of managing different scalar computational cores and the different executed threads.At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we providesome guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.

Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist.

Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-Programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.

Due to rapid technology scaling, electronic devices are becoming more susceptible against soft errors induced by radiation particles, which is a serious challenge for aerospace applications. Meanwhile Field Programmable Gate Array (FPGA) devices have been attracting attention in safety- and mission-critical applications in recent years with the increasing performance and flexibility they provide. Among different types of FPGAs according to the device technology, the SRAM-based FPGA has a higher sensitivity against soft errors as SRAM cell, which is used for storing the configuration data of the circuit design implemented and mapped on the FPGA, is one of the most sensitive devices against radiation induced soft errors. Hence, to guarantee the usage of SRAM-based FPGAs in safety critical environments, the design mapped on it requires an effective verification and validation procedure. Radiation test is one of the verification methods regarding the effects of radiation induced soft errors. In this paper, we present an automated setup for monitoring the soft errors during the radiation test and we compared the measurement obtained from radiation test with the one provided by analytical tools. The experimental results we gained demonstrated the feasibility of the proposed measurement platform.

In this paper, we propose a methodology for executing simulation using analytical models for the execution of SET propagation on System-on-a-Chip implemented on Flash-based FPGAs. Analysis performed on EUCLID-based circuit design demonstrated its effectiveness.

The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.

When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.

In this paper we combine a set of software-based fault tolerance techniques with a hardware module that monitors the trace port, and explore from an experimental point of view the fault coverage against soft errors in COTS processors that can be achieved. The costs in terms of performance and memory are also evaluated. Fault injection results show fault coverage is superior to the state-of-the-art techniques with lower performance and memory overheads.

This paper proposes a mapping tool for selectively mitigate radiation-induced Single Event Transient phenomena within the silicon structure of Microsemi RTG4 Radiation hardened Flash-based FPGAs. Experimental results on three benchmark circuits demonstrated effective SET mitigation.

This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial tool-chain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average.

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.

Technology scaling enables the Field Programmable Gate Arrays (FPGAs) provide increasing computing power while remain low power consumption. Together with the high flexibility for application design and deployment, FPGAs have become popular even in safety- and mission-critical applications. Meanwhile, Commercial Off-The-Shelf (COTS) components are often used in system design to reduce time-to-market and development cost. In this paper, we are proposing a new method for the analysis and mitigation of Single Event Upsets (SEUs) on SRAM-based FPGAs. The method is based on an analytical analyzer algorithm able to accurately estimate the application error rate; furthermore, the same developed algorithm is able to implement mitigation rules. We present the radiation experiment results for analysis and mitigation of Single Event Upsets (SEUs) in an ARM-based SoC implemented on Xilinx Virtex-V FPGA demonstrating the feasibility of the analysis tool and the effectiveness of the mitigation method.

Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude.

In the present paper, we propose a new design flow for the analysis and the implementation of circuits on Flash-based FPGAs hardened against Single Event Effects (SEEs). The solution we developed is based on two phases: 1) an analyzer algorithm able to evaluate the propagations of SETs through logic gates; 2) a hardening algorithm able to place and route a circuit by means of optimal electrical filtering and selective guard gates insertions. The effectiveness of the proposed design flow has been evaluated by performing hardening on seven benchmark circuits and comparing the results using different implementation approaches on 130nm Flash-based technology. The obtained results have been validated against radiation-beam testing using heavy-ions and demonstrated that our solution is able to decrease the circuits sensitivity versus SEE by two orders of magnitude with a reduction of resource overhead of 83 % with respect to traditional mitigation approaches.

Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.