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A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5-\mum Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC. [ABSTRACT FROM PUBLISHER]

Total dose and single-event radiation hardness, and operation over extreme temperatures make silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processes leading contenders for space applications. This paper re- ports noise degradation of 0.35-μm partially-depleted SOI CMOS devices and a micropower, low-noise preamplifier following 63-MeV proton irradiation to 1 Mrad (Si). Proton irradiation, relevant for space mission environments, was considered since it induces both ionizing and displacement damage. Preamplifier input-referred white-noise voltage was minimized at low power consumption by operating input devices in moderate inversion for high transconductance efficiency. Flicker-noise, important for gyros and other mission sensors having low-frequency outputs, was minimized by large-area pMOS input devices and careful management of noninput devices. Measured 1-Hz gate-referred, flicker-noise voltage density increased 24 and 32% for pMOS and nMOS test devices respectively following 1 Mrad (Si) irradiation. Measured 1-Hz input-referred noise voltage density increased 22% between a nonirradiated and radiated preamplifier sample, which agrees closely with the 24% increase expected since noise is dominated by pMOS input devices. Device small-signal transconductance and white-noise were largely unchanged while output conductance appeared to increase over a factor-of-three. This suggests a modest design margin is required to maintain flicker noise performance, while substantial design margin may be required to maintain open-loop voltage gain. [ABSTRACT FROM AUTHOR]

The four-gate silicon-on-insulator transistor (G4 -FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G4-FET are analyzed based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications. [ABSTRACT FROM AUTHOR]

Presents an overview of the measured noise behavior of complementary metal oxide semiconductor MOSFET's fabricated in the Peregrine 0.5 μm fully depleted silicon-on-sapphire process. MOSFET noise; Inversion coefficient representation; Noise measurement system; Experimental results; Conclusion.

Deals with a study which developed a custom mixed-signal complementary metal oxide semiconductor integrated circuit for high performance positron emission tomography front-end applications. Application specific integrated circuit (ASIC) architecture and description; ASIC performance; Conclusion.