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Purpose This paper aims to develop high-pass (HP) negative group delay (NGD) investigation based on three-port lumped circuit. The main particularity of the proposed three-port passive topology is the consideration of only a single circuit element represented by a capacitor. Design/methodology/approach The methodology of the paper is to consider the S-matrix equivalent model derived from admittance matrix approach. So, an S-matrix equivalent model of a three-port circuit topology is established from admittance matrix approach. The frequency-dependent basic expressions are explored to perform the HP-NGD analysis. Then, the existence condition of HP-NGD function type is analytically demonstrated. The specific characteristics and synthesis equations of HP-NGD circuit with respect to the desired optimal NGD value are established. Findings After computing the frequency expressions to perform the HP-NGD analysis, this study demonstrated the existence condition of HP-NGD function type analytically. The validity of the HP-NGD theory is verified by a prototype of three-port circuit. The proof-of-concept (POC) single capacitor three-port circuit presents an NGD response and characteristics from analytical calculation and simulation is in very good correlation. Originality/value An innovative theory of HP-NGD three-port circuit is studied. The proposed HP-NGD topology is constituted by only a single capacitor. After the topological description, the S-matrix model is established from the Y-matrix by means of Kirchhoff voltage law and Kirchhoff current law equations. A POC of single capacitor three-port circuit was designed and simulated with a commercial tool. Then, a prototype with a surface-mounted device component was fabricated and tested. As expected, simulation and measurement results in very good agreement with the calculated model show the feasibility of the HP-NGD behavior. This work is compared to other NGD-type function with diverse number of ports and components.

International audience; The electrocardiogram (ECG) is sensitive to human body motions when it is measured with dry metal electrodes. A common hypothesis in previous literature dealing with these subjects postulate that this is due to the skin-electrode impedance variability. This paper aims to verify this hypothesis by investigating the origin of the noise in the ECG signal and finding suitable solutions to reduce this disturbance. For this reason, experiments are proposed here to explore the relationship between the skin-electrode impedance and the ECG for several motions. Results demonstrate that the noise due to human body motions in ECG equally comes from the electrochemical equilibrium break of the reduction-oxidation reaction at the skin-electrode interface. Moreover, it has been shown that motions lead to sweat thickness variations and equally to skin-electrodes capacitance variations. To model this phenomenon, an electrical model based on a variable capacitor is introduced. Finally, a significant noise reduction solution based on the monitoring of this capacitor is proposed.

International audience; A design method of low-pass (LP) negative group delay (NGD) integrated circuit (IC) implemented in 130-nm BiCMOS technology is investigated. The LP-NGD circuit is composed by RL-network with BiCMOS high Ohmic unsalicided N+poly resistor and symmetrical high current spiral inductor. The design methodology of the investigated LP-NGD circuit is explained by chip layout process. Then, the pre-simulation is performed with the design rule check (DRC) and 225 µm × 215 µm layout versus schematic (LVS) approaches. The LP-NGD design feasibility of the BiCMOS IC implementation is validated by AC frequency domain simulation with realistic component implementation constraints. As expected, the ideally calculated and simulated results show NGD of about-100 ps with 1.12 GHz cutoff frequency and-6 dB attenuation. Moreover, the LP-NGD function is also verified with transient analyses with Gaussian pulse and arbitrary waveform signals. As expected, despite the attenuation, the output signal leading and tailing edges appear in time-advance of about-100 ps compared to the input ones.

This paper presents the design and test of a distributed planar microwave circuit presenting a crab-shape topology. The circuit’s topology consists of transmission lines (TLs) associated in feedback with two cascaded coupled lines (CLs). This topology has the characteristics of a bandpass negative group delay (NGD) function. The analytical model allowing to determine the group delay (GD) is established from S-parameter approach and the analysis of NGD crab topology is described. The NGD existence condition as a function of the topological parameters is presented. The NGD circuit proof-of-concept (PoC) is designed, simulated, and fabricated to understand and validate the proposed NGD functions. The measured, simulated, and theoretical results are in good agreement. As designed, the band pass NGD behavior is observed around 3 GHz with NGD of approximately -4.8 ns.

International audience; Because of its counterintuitive nature, the Negative Group Delay (NGD) remains as an uncommon and unfamiliar electronic function. For this reason, the design and analysis of NGD circuits are not well-known for most of electronic designers. This paper initiates a basic and easy to understand theory, in addition to a design methodology for the low-pass NGD function. The circuit theory on the low-pass NGD function is described using an NGD passive topology which is constituted by a RC-parallel network with a resistive load. The NGD analysis and synthesis equations in function of NGD specifications are provided and a proof-of-concept of 6-dB low-pass NGD circuits has been designed, simulated, fabricated and tested. Frequency and time domain analyses have been performed to validate the low-pass NGD function. Theoretical and simulated results are in very good agreement and an NGD has been obtained in measurement for the proposed structure

International audience; Most of the negative group delay (NGD) circuit recent investigation were focused on the classes of lowpass and bandpass categories. Few research works are currently available in the literature on the typical high-pass (HP) NGD function. This paper introduces an original HP-NGD circuit theory of four-port passive topology constituted by a single lumped capacitor. The S-matrix equivalent model of the innovative topology is established from the admittance matrix. Then, the basic frequency analytical responses are expressed. Then, the GD model is derived in function of the capacitor. It was found analytically that the four-port mono-capacitor passive circuit is susceptible to behave originally as an unfamiliar HP-NGD function. An innovative HP-NGD analysis is explored in addition to the expression of synthesis design equation in function of the expected NGD cutoff frequency which is linked to NGD optimal value. The validity of the established HP-NGD circuit theory is verified with a proof of concept (POC). As expected, the HP-NGD behavior showing a good correlation between analytical model and simulation is obtained.

Purpose The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function. Design/methodology/approach The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC). Findings From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC. Originality/value This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.

This paper focuses on the design of two analog nonlinear transformations dedicated to analog signal processing such as energy detection: the square function and the Teager Energy Operator (TEO). Both requiring an analog multiplier, this paper firstly analyses the design equations of a MOS Gilbert cell in order to operate around the mid supply voltage. Considering this, an analog multiplier, having a differential input range of ±400 mV, has been designed using an AMS 0.35 μm technology and a voltage supply (VDD) of 3.3 V. It has a core area of 620 μm2 and offers power-gating capability, which enables a power consumption of 2.28 μW when a duty cycle of 0.25% is considered. Next, an analog square function and an analog TEO, have been implemented and manufactured using the designed Gilbert cell. The analog square function has a core area of 0.9 mm2 and measurement results show that it is able to compute the square value of its differential input voltage with a mean precision of 2.92% in 5 μs assuming a differential input voltage of ±400 mV with a common voltage of VDD/2. Moreover, it generates 700 mV spikes when 200 mV pulses are applied on its input. Finally, the designed analog TEO has been implemented using its discrete time equation instead of its continuous time equation since it does not require derivatives computing. It has a core area of 2.2 mm2, an active power consumption of 6.21 mW and a standby power consumption of 1.43 nW. Measurement results shows that it generates until 250 mV spikes when 200 mV pulses are applied on its input.

This brief introduces an original reduction method of resonance effect dispersion by using bandpass negative group delay (NGD) function. The dispersion transfer function (TF) is model by lumped RLC circuit. The canonical parameters of NGD passive cell are innovatively formulated as a function of the resonance dispersion specifications. The developed method feasibility is validated with commercial tool frequency domain simulations. Proofs-of-concept constituted by passive RLC-resonant and NGD fully passive circuits are considered. The results confirm an obvious peak reduction of resonance magnitudes and GDs from (15-dB, 20-ns) to better than (11.5-dB, 8.6-ns) are realized in the NGD bandwidth of about 20 MHz. The NGD method robustness is also investigated with simultaneous and individual relative variations of the dispersion parameters.

This study investigates an innovative theory on design of dielectric resonator (DR) based negative group delay (NGD) microwave circuit. The NGD circuit is mainly constituted by a cylindrical bulk of DR as a coupling element with a microstrip line. The developed theory is analytically established from the S-parameters modeling of this innovative DR NGD topology. The NGD analysis and synthesis equations are formulated by considering the key parameters of the DR NGD cell. The NGD existence condition as a function of the DR and microstrip line parameters is also introduced. The behavioral response of the bandpass NGD function is verified with different designed proof-of-concepts (POCs). The developed NGD DR topology was validated with original circuit design by commercial simulations and experimentations with insertion and reflection losses lower than 4 and 10 dB, respectively. The POC prototypes operate with low attenuation losses in mono band and dual bands up to 10 GHz. Single NGD cells with DR coupled with “I” and “U” shape microstrip lines operating at different central frequencies were designed and implemented. Then, dual-band NGD circuits operating at approximately 2.5 and 5 GHz were also tested. The possibility to widen the NGD bandwidth with double DR NGD circuits was investigated.

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International audience; This paper develops an original circuit theory of unfamiliar stop-band (SB) negative group delay (NGD) topology. The proposed NGD topology is implemented without inductor component. The developed theory is established with passive cell constituted by RC-network based high-pass (HP) and low-pass (LP) NGD composite circuits. The analytical investigation of the SB-NGD circuit is introduced from the elaboration of voltage transfer function (VTF). The canonical form enabling to identify SB-NGD circuit is analytically expressed. The different SB-NGD characteristics as GD value, and, center and cutoff frequencies are innovatively formulated in function of the circuit resistor and capacitor components. The existence condition of SB-NGD function is also established. The inductorless SB-NGD topology is validated by a proof-of-concept (POC) circuit implemented by surface-mounted-device (SMD) component based printed circuit board (PCB). The measured VTF magnitude and group delay (GD) are extracted from the experimented S-parameters. A good agreement between the calculated, simulated and measured results is obtained. The SB-NGD behavior has measured center frequency of about 32 MHz. The lower-and upper-NGD cutoff frequencies are about 9.15 MHz and 98.3 MHz. The optimal NGD values at low and higher frequencies are −3.25 ns and −56 ps. INDEX TERMS Circuit theory, negative group delay (NGD), stop-band (SB) NGD function, passive cell, inductorless topology.

International audience; A particularly original negative group delay (NGD) theory of-topology is developed in the present paper. The NGD three-port topology is a passive circuit purely constituted by capacitors network. The model of the proposed-topology impedance 3-D matrix is analytically established in function of the capacitor elements. Then, the S-matrix model is derived by using the Y-to-S transform. By considering the S-matrix frequency responses, a bandpass (BP) NGD analysis of the capacitive-topology is originally elaborated. It is theoretically demonstrated that the passive-topology is susceptible to behave as a BP NGD circuit under an analytical condition between the constituting capacitor values. The design feasibility of the BP NGD function is experimentally verified with lumped capacitor components-based-circuit proof of concept. An electronic circuit board constituted by purely capacitive-network-circuit is fabricated as an original-circuit prototype. The tested board is constituted by arbitrary chosen capacitors, 100 nF, 10 nF and 0.1 nF. As expected, the calculation, simulation and measurement results, which are in very good agreement, confirm the BP NGD behavior. It is observed from measurement that it generates NGD of about −18.1 ns at a frequency of about 0.55 MHz and, lower and upper cutoff frequencies of about 0.33 MHz and 1.71 MHz. It is noteworthy that the transmission and reflection coefficients at very low frequency are independent of the capacitor values and analytically equal to 2/3 and 1/3, respectively. INDEX TERMS Bandpass (BP) negative group delay (NGD), passive topology,-topology, three-port circuit, S-parameter modeling, NGD theory, capacitive network.

International audience; This paper deals with an original equalization method of 3-D electromagnetic (EM) cavity resonance by using bandpass negative group delay (NGD) function. Based on the equivalent circuit, the S-matrix model of the equalized EM cavity is introduced. The design equations of the NGD function are established in function of the cavity physical parameters. The feasibility of the equalization method is validated with a 42×28×3.8 cm rectangular cavity containing two communicating monopole antennas. By considering the TE110-mode, a significant equalization is realized with improvement of transmission coefficient flatness from 4-dB to less than 0.3-dB. In addition to the magnitude, the NGD equalization method enables to outstandingly reduce spikes of 3-D EM cavity group delay. With the proof of concept, the GD is reduced from more than 4-ns into 1-ns.

A transient study of bandpass (BP) negative group delay (NGD) function is devoted in this paper. The transient analysis is applied to an original topology of NGD barcode-shape microstrip circuit. The performed investigation explains how to realize the transient analysis of tri-band NGD circuit. The time-domain (TD) parametrization of the test is established from the BP-NGD specifications of the circuit under test (CUT) based on the S-parameter model. The input signal is a Gaussian pulse characterized in function of the NGD bandwidth (BW) and center frequency. The feasibility of the BP-NGD transient study is illustrated with experimentation based on ultra-wide band (UWB) pulse generator. As proof-of-concept, barcode NGD circuit exhibiting tri-band NGD value-center frequency-bandwidth, (−5.9 ns, 2.128 GHz, 20 MHz), (−7.4 ns, 2.3 GHz, 14 MHz) and (−4.8 ns, 2.42 GHz, 14 MHz) has been fabricated and tested. The transient simulations and experiences confirm that the output signal envelopes of the barcode NGD prototype present leading and tailing edges in time-advance of input ones when the carrier frequency is set equal to the NGD center frequency.

International audience; This paper develops a new reconstruction technique of undesirable signal distortion generated by sensor electronic circuits. The introduced reconstruction technique is originally realized with unfamiliar low-pass negative group delay (NGD) function. The feasibility condition of the proposed reconstruction technique in function of the sensor signal spectrum bandwidth under consideration is elaborated. The reconstruction technique principle is theoretically introduced by means of identification of low-pass NGD function parameters and the appropriated circuit topology. The unfamiliar low-pass NGD function analysis and synthesis equations are established. As an example, for the feasibility study, an RC-network based low-pass active cell is considered to implement the low-pass NGD function. A design method of NGD circuit in function of the sensor distortion transfer function is described in different successive steps. The developed NGD reconstruction technique is validated by different proofs of concept. First, transient simulations are carried out with Gaussian and sinc analytical signals. Then, experimental feasibility study is also performed with arbitrary waveform signal. As expected, the NGD reconstruction technique efficiency is confirmed with improvement of distorted signal integrity parameters and cross correlation better than 97%.

In this paper, the design of a Gilbert analog multiplier is presented from design equations for input dynamic range optimization to measurement results, these last being obtained in the context of a square function dedicated to analog signal processing. The full circuit has been implemented using an AMS $0.35\mu m$ technology with a voltage supply (VDD) of 3.3V. Assuming a differential input voltage of $+/-400mV$ with a common voltage of VDD/2, it is able to compute the square value of its differential input voltage with a mean precision of 2.92% in $5\mu s$. Finally, the analog multiplier itself has a core area of $620\mu m^{2}$ and offers power-gating capability, which enables a power consumption of $2.28\mu W$ when a duty cycle of 0.25% is considered.

A negative group delay (NGD) design of a turtle shape circuit topology is developed in this brief. The topology is comprised of two different length transmission lines (TLs) interconnecting two identical coupled lines (CLs). The S-matrix model is established as a function of the TL and CL parameters. The group delay (GD) at the half wave frequency of the short interconnect TL is derived from the transmission coefficient. To verify the relevance of the proposed turtle circuit theory, a microstrip proof of concept was modeled, designed, simulated, fabricated, and tested. The calculated, simulated and measured results are in good agreement and confirm the turtle prototype bandpass NGD function with approximately 1.97 GHz center frequency and NGD level of approximately −1.3 ns. In addition, this passive circuit operates with very low losses less than −2.5 dB over the reflection coefficient better than −14 dB.

International audience; This paper aims to develop an original circuit theory of inductorless NGD topology. The considered passive cell comprised of resistor and capacitor elements without inductor operates as a bandpass (BP) NGD function. The specifications of NGD functions are defined. Generally, the BP NGD fully lumped circuits available in the literature operate with resonant RLC-network. In the introduced research work, a lumped circuit was first time identified to exhibit the BP behavior without the presence of inductive component. The inductorless BP NGD topology is inspired from the combination of low-pass (LP) and high-pass (HP) NGD passive cells. Therefore, an original LP-HP NGD composite topology is obtained. The identified BP NGD topology is constituted only by passive RC-networks. Then, theoretical development of BP NGD analysis is explored. The inductorless circuit theory starts with the identification of BP NGD canonical form. Then, the expressions of NGD value, center frequency and attenuation in function of RC-network parameters are established. The synthesis equations allowing to determine the resistor and capacitor elements are derived. Proofs-of-concept are designed and prototypes are fabricated to verify the effectiveness of the developed LP-HP NGD composite theory. To validate the developed original circuit theory, two prototypes of RC-network based LP-HP NGD composite were designed, fabricated, simulated and tested. The two prototypes were synthesized with respect to two different NGD center frequencies 13.5 MHz and 22 MHz. As expected, the calculated, simulated and measurement results are in very good agreement with NGD value of about some negative nanoseconds. In the future, the characterized inductorless topology enable to overcome the traditional limitations of RLC-network based BP NGD circuits because of inductance self-effect limitation. INDEX TERMS Bandpass (BP) negative group delay (NGD), low-pass/high-pass (LP-HP) NGD composite, circuit theory, inductorless passive topology.

International audience; The via ground (GND) structure constitutes one of the most useful elements for designing high performance printed circuit boards (PCBs). The electrical interconnections with vias become key regular solutions for the implementation of various electronic functions. However, so far, the vias are never being used for designing negative group delay (NGD) circuit. To answer this curious question, an original study on the design feasibility of low-pass NGD function with via ground is introduced in the present paper. After the topological description, the NGD analysis in function of the via parameters is established. The design equations allowing to synthesize the via in function of NGD function specifications are formulated. The developed NGD theory is verified with comparisons between calculations and simulations with a commercial tool. As expected, NGD value in order of hundred-picoseconds over hundred-megahertz cutoff frequencies is obtained with good agreement between the theoretical model and simulation. Furthermore, time domain analyses confirm that the via NGD structure enables to generate output signals in time-advance of arbitrary waveform input signals presenting limited bandwidth. INDEX TERMS Analytical modelling, cylindrical via, low-pass negative group delay (NGD), microstrip circuit, via-hole ground.

International audience

International audience; This paper elaborates a negative group delay (NGD) analysis of 0IO-shape printed circuit board (PCB) traces. This circuit topology is originally implemented with a tri-coupled line (3CL) six-port element with the lateral side connected through lossy transmission lines (TLs). After description of the electrical equivalent diagram, the S-matrix model is established. The group delay (GD) is formulated from the transmission coefficient as a function of the 0IO topological parameters. The effectiveness of the GD modelling is verified with a microstrip circuit proof-of-concept (POC). Simulations and measurements, which are in good agreement, confirm the dual-band bandpass NGD behavior of the 0IO POC. The fabricated prototype generates NGD levels better than −1 ns at NGD center frequencies of about 2.2 GHz and 3 GHz. In addition, to this good NGD performance, the 0IO POC operates with a low insertion loss better than 2.5 dB and reflection losses better than 12 dB in the NGD bandwidths. INDEX TERMS Microwave theory, distributed topology, negative group delay (NGD), tri-coupled line (3CL), modeling.

This paper presents an investigation on innovative bandpass negative group delay (NGD) control. The bandpass NGD theory is elaborated with patch antenna-based circuit input impedance. The S-matrix ...

Design of a reconfigurable compact digitally controlled oscillator (DCO is proposed in this paper. It uses a gyrator-C based-topology tunable active inductor (TAI) that achieves coarse frequency tuning due to a digitally controlled current source and a variable capacitance bank. The DCO, implemented in 130 nm CMOS process, achieves a frequency tuning from 1.8 to 2.6 GHz when varying the digital control word. It occupies an area of only $57\ \boldsymbol{\mu} \mathbf{m}\times 53\ \boldsymbol{\mu} \mathbf{m}$ . The power consumption is changing from 2.6 mW to 5.3 mW at a supply voltage of 1.1 V, and the phase noise from −86 to −82 dBc/Hz @1 MHz offset. The proposed DCO shows a compact size, wide tuning and low-power consumption making it suitable to reconfigurable low-cost multiband radiofrequency (RF) applications.

This paper presents a design of a CMOS digitally controlled oscillator (DCO) using a tunable active inductor (TAI) to reduce the area and cost for reconfigurable multi-band RF applications. The compatibility of this circuit to different wireless standards shows its potential to be implemented for the Internet of Things (IoT). The proposed TAI, based on a gyrator-C topology, achieves coarse frequency tuning due to a 4-bit digitally controlled current source. Implemented in 130 nm CMOS technology, the DCO occupies an area of only $(52\ \times 48)\ \mu\mathrm{m}^{2}$ . The circuit offers a frequency tuning from 1.65 GHz to 2.5 GHz for a 4-bit digital control word in [1], [15]. The optimal phase noise is about −87 dBc/Hz@1 MHz offset with power consumption varying from 2.6 mW to 5 mW at a supply voltage of 1.1 V when changing the control word digitally from 1 to 15.

In this study, a suitable sub-mW frequency down converter for internet of things is presented. It is based on a single balanced switched transconductance mixer driven by a current-reuse LC voltage controlled oscillator (LC-VCO). For cognitive radio demonstration, the frequency converter is implemented with a tunable low-noise amplifier (LNA) in 0.13 µm standard complementary metal oxide semiconductor (CMOS) technology. Post-layout simulations return a gain conversion of 27 dB with a single-sideband noise figure of 8 dB (LNA included) for a consumption of 0.97 mW under a voltage supply of 1.2 V and an active area of 0.4 mm2. The stand-alone LC-VCO prototype exhibits a measured phase noise of −102 dBc/Hz at 1 MHz offset while showing −114 dBc/Hz in the post-layout simulation. The LC-VCO measured power consumption is only 260 µW from 1 V voltage supply with an active area of 0.173 mm2.

International audience; A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

International audience; Cet article traite d'une étude préliminaire ayant comme objectif de déterminer le matériau le plus approprié pour la réalisation des électrodes nécessaires à la mesure de l'électrocardiogramme à l'aide d'un dispositif utilisable à domicile par les patients et n'utilisant que deux électrodes. En effet, bien que la mesure de l'électrocardiogramme dans le milieu médical ne pose pas de problème particulier (environnement contrôlé, patient immobile, application d'un gel sur la peau favorisant la mesure, etc.), l'utilisation à domicile d'un tel système est plus problématique car cela nécessite tout d'abord sa miniaturisation tout en garantissant une mesure fiable même lorsque le patient est en mouvement et ce, sans qu'il n'y ait besoin d'appliquer au préalable un gel sur la peau favorisant la mesure. Pour cela, une modélisation électrique du circuit vue entre deux électrodes posées sur la peau est ici tout d'abord introduite. Puis, des critères permettant de juger de la qualité d'un électrocardiogramme et notamment de sa sensibilité au mouvement du patient sont proposés. Enfin, une série de mesures électriques et d'électrocardiogrammes sont présentées pour différents matériaux en vue d'en déduire le modèle électrique et la qualité de signal induits par chaque matériau. En plus de dessiner dès maintenant une tendance entre les différents matériaux testés, il est envisagé par la suite d'étudier la corrélation entre les paramètres du modèle et la qualité de l'électrocardiogramme et ainsi d'imaginer à terme l'intégration dans le dispositif de méthodes de compensation améliorant en temps réel la qualité de l'électrocardiogramme mesuré..

International audience; This paper is devoted to an exhaustive presentation of a fast computation numerical tool, dedicated to the simulation of transient currents induced by stochastic events in microelectronic devices. This is a part of a numerical platform, SITARe, combining a spice simulator with the semi-analytical model presented here. The paper describes the theoretical model, the calibration. An instance of application illustrates the ability of the tool.

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In this paper, a preliminary study about the most suitable dry electrode materials is done in the context of electrocardiogram (ECG) measurement systems used at home. Therefore, the electrical equivalent circuit between two electrodes through the body is developed as well as the ECG quality evaluation factors. Finally, an initial series of impedance and ECG quality measurements is presented which led to the conclusion that dry stainless steel electrodes seem to provide the best ECG signal quality.

The development of a new methodology based on Short-Term Fourier Transform (STFT) to detect and track particles is presented. The methodology is investigated based on an CMOS oscillator detection chain optimized for identification of low particle fluxes. The evaluation of the circuit sensitivity to radiation is performed by measuring and processing the oscillator response. In the presented approach, the oscillator output signal is processed using the STFT technique. The CMOS detector is based on SOI technology making it tolerant to radiations.

International audience; A particle detection chain based on CMOS-SOI VCO circuit is presented. The solution is used for the recognition and the tracking of a given particle at circuit level. TCAD simulation of the detector has been performed on a 3×3 matrix of diodes based detector for particles recognition and tracking. The current response of the detector has been used for a case study in order to determine the ability of the chain to recognize an alpha particle crossing a 3×3 detection cell. The detection limit of the proposed solution is investigated and discussed in this paper.

International audience; Internet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm(2). The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of -116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is -107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 mu W from 0.6 V supply voltage, making it suitable for ultra low power applications.

International audience; De nos jours, les maladies cardiovasculaires engendrent autant de décès que le cancer en Europe. Dans le but d'être en mesure de déceler ces maladies, de nombreux projets de télésurveillance médicale ont été lancé. Dans le cas de la surveillance du rythme cardiaque à l'aide d'un signal électrocardiographique, des impulsions appelées complexes QRS et synchrones avec le battement cardiaque doivent être détectées. Pour permettre la détection de ces complexes QRS dans un environnement non maîtrisé contrairement à une salle d'examen médical, un détecteur de complexes QRS tolérant au bruit est proposé dans cet article. Il repose sur un étage de mise au carré intégrable dans un circuit analogique faible coût qui a été simulé à l'aide de la technologie CMOS 0,35µm d'AMS.

This brief presents a reconfigurable inductor-less voltage controlled oscillator (VCO) with low-power and low-cost performances making it suitable for IoT applications and applicable to the multi-standards. It uses an active inductor based on n-bits controlled CMOS inverters for coarse frequency tuning and diode varactor for fine frequency tuning. The example of a 3 bit digitally controlled oscillator has been implemented in a 0.13μm CMOS process. It can cover a frequency tuning of 1.28–2.6 GHz and thus can support the different standards of 2G, 3G, 4G and future 5G wireless systems. The fabricated LC-VCO occupies a small active area of only (54 × 59)μm2. The phase noise is −87 dBc/Hz @ 1MHz with a power consumption less than 4mW at a supply of 1.1V.

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International audience; An analysis and optimization of an oscillator based detection chain, dedicated to the conditioning of low input signals, is presented in this paper. The concept is based on an indirect detection of the current generated at the input of the detection chain, through a Voltage Controlled Oscillator (VCO) response. In order to improve the correlation between the input current and the oscillator response (signal recognition), the full characterization of the VCO is presented. The solution enhances the particle recognition with a simple analysis of the VCO output. The new output parameter variations are analyzed and the system resolution is explored.

This paper presents the architecture of a digitally controlled oscillator (DCO) suitable for multi-standard radio frequency (RF) operation. The presented oscillator has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters control voltages. The oscillator can cover different frequency bands from 1.23 GHz to 2.46 GHz by varying digitally four inverters sequence. It consumes less than 4.4 mW under 1.1 V supply voltage. It occupies a chip area of (54 × 59) μm2 in 130 nm CMOS technology.

A new concept of burst generator architecture dedicated to impulse-radio ultra-wideband wireless communication systems is presented. Bursts are generated by using four elementary baseband pulse generators operating in parallel. Thus, the resulting waveform is the amplitude and phase addition of time-overlapped pulses. The circuit has been implemented in 65 nm CMOS technology under a 1.2 V supply voltage. Simulation results are presented exhibiting a power consumption of 7.24 mW.

International audience; This study is driven by the need to optimize reliability and failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. Nowadays, single event effect (SEE) evaluations due to radiation impacts are critical in fault tolerance and security field. The prediction of a SEE occurring on electronic devices is proposed by the determination and modeling of the phenomena under pulsed laser stimulation. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an inverter in a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals the possible activation change of the parasitic bipolar transistors. Based on these experimental mea- surements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation. Therefore this electrical model could be used as a tool for characterizing more complex CMOS circuits under photoelectrical laser stimulation.

This paper presents a novel design and an optimization methodology of an ultra-low power and low phase noise RF voltage controlled oscillator (VCO). This VCO is based on a PMOS-NMOS cross-coupled topology operating in the subthreshold region. An adaptive body biasing technique is presented in this circuit leading to a high immunity to PVT (P=Process, V=Voltage, and T=Temperature) variations. The VCO, implemented in 130nm CMOS technology, consumes only 63 μW under 0.6 V. The obtained tuning range is about 7.2% from 2.32 GHz to 2.495 GHz; therefore, it can address many wireless communication standards such as Wi-Fi, ANT, ZigBee, IEEE 802.15.4, 6LoWPAN, and Bluetooth.

This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different stages while the desired bandwidth is ensured due to an optimal sizing of the inter-stages connections. This approach has been validated with on chip measurements. Using the proposed techniques more than 55 dB of image rejection over the [1.5; 3.3] GHz bandwidth is demonstrated while achieving zero power consumption and small silicon area in 130nm CMOS technology.

Simple and low cost method based on Built-in-Tuning (BIT) of passive filters in RFIC transceiver is presented, which is used to compensate for variability induced imperfections in RF subsystems. Auto-calibration of filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio (IRR) and the I/Q-accuracy resulting to robust and low-cost solutions in multistandard wireless transceiver.

International audience

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

A digitally controlled oscillator (DCO) suitable for multi-standards radio-frequency (RF) operation is presented. It has an LC topology using an active inductor based on CMOS controllable inverters. The tunability of the oscillator frequency is ensured by varying the digital word applied to the inverters’ control voltages. The proposed DCO has a small area and exhibits a high-frequency tuning range while achieving low power consumption with good stability against process variations.

International audience; Investigations on the feasibility of integration of a readout system dedicated to neutrons detection in harsh environment is presented. This is a very first study taking place in the framework of the I_SMART (Innovative Sensors for Material Ageing and Radiation Testing) European project. First approach on the feasibility of integration of the full system is introduced. In its final release, this system will have to work in harsh environment in terms of temperature and radiation, what makes necessary the development of specifications for operation and reliability of components and the investigation of margins for the interplay of the components. Implementation of the analog conditioning chain is investigated here where electrical performances have been validated at SPICE-level simulations.

Investigation of readout electronic dedicated to electromechanical audio sensor is presented. The circuit is able of reading piezoresistive gauge implemented with silicon nanowire (NEMS) and bring electromechanical signal to high-resolution digital output. Low-noise low-power CMOS operational transconductance amplifier (OTA) is presented. The low-noise amplifier (LNA) has been designed in a 0.28 μm CMOS process with a 2.5 V supply voltage and occupies an area of 120 × 160 μm2. For the Post-layout Simulation, the OTA achieves a 65 dB DC gain. It achieves a noise floor of 6 nV/√Hz within the frequency range from 1 Hz to 10 kHz. The total power consumption including the common mode feedback circuit (CMFB) and the biasing circuit is 150 μW.

The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented. This study takes place in the framework of the I_SMART * European project. This system will have to work in harsh environment in terms of temperature and radiations what makes necessary the development of specifications for operation and reliability of the components and also the investigation of margins of interplay of the components. The specifications of the implemented tool are presented here with the different results of simulation related to the input designed parameters of the readout system.