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The three-dimensional carrier confinement in Quantum Dots (QDs) is the key to achieve superior properties (electronic and optical) compared to the Quantum Well (QWL) for optoelectronic applications, such as semiconductor lasers, photodiodes. After the growth of QDs, the encapsulation is the next crucial step to confine carriers in QDs and achieve the targeted wavelength emission. In this work, we have studied the InP capping of Stranski-Krastanov (S-K) grown InAs QDs on InP(0 0 1) substrate by MOVPE. During the encapsulation, the P/As exchange is a vital process which either transforms the QDs into a 2D layer or reduces QDs’ dimensions. This study shows that a control of Phosphorous concentration on the surface during InP capping facilitates to obtain the expected QDs dimension for 1550 nm wavelength. The emitted photoluminescence peak shifts following the preserved average QDs’ dimensions. By combining simulation with optical response we have proved the Phosphorous incorporation into the InAs structure (QDs or 2D layer) during the encapsulation step. As expected, the carrier lifetime reveals the superior quality of the preserved QDs in InP barrier compared to the 2D layer. Finally, the reduction of the non-radiative recombination sources, e.g. dangling bonds, by passivation treatment demonstrates a further increment in carrier lifetime.

Stranski-Krastanow (S-K) grown self-assembled quantum dots (QDs) are considered as an efficient active layer for many optoelectronic applications, such as semiconductor laser, photodetector, due to the possibility to confine carriers in three dimensions. Towards the device application, the subsequent growth of an encapsulation layer is a key step to obtain the desired QDs-based heterostructures. In this work, we have studied step-by-step the encapsulation process of S-K grown InAs QDs/InP(0 0 1) by InAlGaAs (lattice matched to InP) in MOVPE. A detailed investigation with Electron Channeling Contrast Imaging (ECCI) and cross-sectional Transmission Electron Microscopy (TEM), indicated that after the InAlGaAs capping the partially relaxed, dome shaped InAs QDs are transformed into fully biaxially strained, truncated pyramids however without introducing any defects in the heterostructure. The study also presents the important role of the capping layer thickness on the QDs photoluminescence efficiency. The gradual change of the surface morphology during the encapsulation process, has been investigated step-by-step in-depth by atomic force microscopy. The morphological changes can be explained by a capping model based on the localized growth rates. We show that two growth steps of Non-uniform capping, where growth rates are different from each other, result in the successful planarization of the InAlGaAs capping without forming any defect.

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 μS/μm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high- k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices.

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14.

New materials and device architectures will be needed to extend CMOS scaling.High mobility materials in the channel can boost the performance at scaled supply voltage.Ultimate reduction of power dissipation will require new concepts like Tunnel FET.Vertical devices and 3D stacking allow to further downscale the transistor dimensions. In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore's law to the sub-10nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS.

In this work, we report on the growth of pseudomorphic and highly doped InAs(Si)/GaSb(Si) heterostructures on p-type (0 0 1)-oriented GaSb substrate and the fabrication and characterization of n+/p+ Esaki tunneling diodes. We particularly study the influence of the Molecular Beam Epitaxy shutter sequences on the structural and electrical characteristics of InAs(Si)/GaSb(Si) Esaki diodes structures. We use real time Reflection High Electron Diffraction analysis to monitor different interface stoichiometry at the tunneling interface. With Atomic Force Microscopy, X-ray diffraction and Transmission Electron Microscopy analyses, we demonstrate that an “InSb-like” interface leads to a sharp and defect-free interface exhibiting high quality InAs(Si) crystal growth contrary to the “GaAs-like” one. We then prove by means of Secondary Ion Mass Spectroscopy profiles that Si-diffusion at the interface allows the growth of highly Si-doped InAs/GaSb diodes without any III-V material deterioration. Finally, simulations are conducted to explain our electrical results where a high Band to Band Tunneling (BTBT) peak current density of Jp = 8 mA/μm2 is achieved.

The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications.

From electron internal photoemission and photoconductivity measurements at the (100)GaSb/Al"2O"3 interface, the top of the GaSb valence band is found to be 3.05+/-0.10eV below the bottom of the Al"2O"3 conduction band. This interface band alignment corresponds to conduction and valence band offsets of 2.3+/-0.10eV and 3.05+/-0.15eV, respectively, indicating that the valence band in GaSb lies energetically well above the valence band of In"xGa"1"-"xAs (0=

A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(001) using molecular H"2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer.

Si and Se implantations have been systematically investigated in In"0"."5"3Ga"0"."4"7As. Different implant doses and various activation anneals with temperatures up to 700^oC have been examined. Raising Si implant dose from 1x10^1^4 to 1x10^1^5cm^-^2 was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700^oC implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures.

The energy band alignment between Ge, HfO 2 and Al 2 O 3 was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO 2 , Ge 3 N 4 , Si/SiO x ). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO 2 interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO 2 growth using H 2 O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO 2 and Al 2 O 3 deposition suppresses the formation of the narrow-gap Ge oxide.

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