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Abstract In this paper, single event effects (SEE) in a proposed high voltage 4H-SiC lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor is studied by using the 2D TCAD device simulator. Firstly, the sensitive volume of the proposed device is determined by the single ion striking different parts of the device. Then, effect of different LET and different drain bias on the transient drain current and lattice temperature has also been investigated. Thirdly, the mechanism of single event burnout has been discussed in detail. Finally, electric fields in gate oxide have been studied. According to simulation results, the sensitive volume is related to the device structure. Moreover, there is an amplification bipolar effect in the time evolution of the drain current, which is due to the activation of the parasitic bipolar transistor near the source region in the proposed device. Highlights • Single event effects of a SiC LDMOS with a step compound drift region (SiC SC LDMOS) is investigated and simulated. • Effect of LET s and drain bias on the transient current and lattice temperature of SC LDMOS after ion striking is studied. • The single event effects mechanism and sensitive volume of the SiC SC LDMOS are analyzed. • Compared with the traditional triple RESURF LDMOS, the SiC SC LDMOS can improve breakdown voltage and reduce specific on-resistance combining the technology of multiple RESURF and varied lateral thickness. [ABSTRACT FROM AUTHOR]

In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance (R on,sp), and gate drain charge (Q gd,sp), thus the figure of merit (BV2/ R on,sp) is improved by 130 % and the figure of merit (R on,sp × Q gd,sp) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure. • A method of single-event burnout(SEB) hardening at high linear energy transfer (LET) value range is proposed with combined p-buried layer. • The SEB hardening structure shows great Baliga figure of merit (BFOM) and superior high-frequency figure of merit (HF-FOM). • The threshold voltage of the proposed structure is increased by 66.6 % compared with the conventional p + -SiC shielding layer power gate trench MOSFET. [ABSTRACT FROM AUTHOR]

In this paper, the unclamped inductive switching experimental results of a 1.2-kV rated N-Channel conventional power metal-oxide-semiconductor field-effect transistors are presented. The experimental results show that the sample devices can avoid a drain leakage current degradation under the bias conditions of V ds = 1520 V and I av < 20 A. Notably, a severe avalanche failure current degradation is related to interface fixed trap charges. On this basis, the unclamped inductive switching for the 1.2-KV rated MOSFET with different interface fixed trap charges are given. The simulation results show that interface fixed trap charges determine the avalanche drain current degradation degree, and TCAD simulation shows that the interface fixed trap charges make the channel easier to activate. Thus, improving interface fixed trap charges can significantly reduce the degradation of avalanche drain leakage current in devices and enhance their avalanche robustness. • The interface trap charge degradation of a 1.2-KV rated N- MOSFET is investigated via experiments and simulations under UIS. • The basic electrical characteristics and UIS experimental results are given to prove the simulation accuracy. • A severe drain leakage current degradation is is verified that the interface trap charge is related to channel activation. [ABSTRACT FROM AUTHOR]

A novel PIN-junction gate 4H-SiC UMOSFET with integrated heterojunction (PJG-UMOSFET) is proposed and numerically studied. The integrated heterojunction diode effectively suppresses the conduction of the intrinsic PN diode in the reverse conduction state of PJG-UMOSFET. The device simulation results show that the on-resistance (R on) of the device is reduced by about 20.5 % compared with the traditional SiC UMOSFET, and there is almost no specific conduction resistance decrease. The reverse recovery time (t π) and reverse recovery charge (Q π) are reduced by 42.1 % and 68.4 %, and the gate-to-drain charge is reduced by 41.2 %. In addition, a feasible manufacturing process method for the proposed device is provided. • The reverse recovery performance of the proposed SiC MOSFET is significantly improved. • The gate charge performance of the proposed SiC MOSFET is significantly improved. • The reverse I-V performance of the proposed SiC MOSFET is significantly improved. • The improvement is mainly due to the PIN-junction gate and the heterojunction. [ABSTRACT FROM AUTHOR]

This paper proposes a reverse conducting insulated gate bipolar transistors (RC-IGBT) structure with a raised N-buffer layer (RNB-IGBT) to improve the single-event burnout (SEB) robustness. The electrical and radiation properties of the structure were verified by TCAD simulations. At the same snapback voltage of 0.22 V and the liner energy transfer (LET) of 60 MeVcm2/mg conditions, the SEB threshold of RNB-IGBT is improved by 52 % compared to that of conventional RC-IGBT. This result indicates that the raised N-buffer layer of the RNB-IGBT can effectively reduce impact ionization, so it can suppress excessive heat concentration and avoid induce SEB. [ABSTRACT FROM AUTHOR]

In this paper, we studied the electrical and structural properties of Ni/Si/Al Ohmic contacts to p-type 4H-SiC. The p-type epilayer (N A = 1 × 1019 cm−3) was grown on the N-type epilayer with Al dopants. The properties of Ni/Si/Al contacts were analyzed by changing the thickness of Si film and the annealing temperature. After annealing at 700 °C, the Ni/Si/Al contact forms ohmic contact. Compared to Ni/Al contacts, Ni/Si/Al ohmic contacts are formed at lower annealing temperature. The contact resistivity of Ni/Si/Al (80/20/100 nm) contact is 1.3 × 10−4 Ω·cm2 after annealing at 800 °C. X-Ray Diffraction (XRD) and Scanning Electron Microscopy (SEM) are used to analyze the microstructure and observe the surface topography. The results show that Ni and Si react at low temperature to form Ni 2 Si, which is the reason for the formation of Ni-based ohmic contacts. At the same time, the addition of the Si layer weakens the reaction between Ni and SiC, which reduces the generation of free C elements. The Ni/Si/Al contact shows better ohmic contact characteristics. [ABSTRACT FROM AUTHOR]

• Mo-C alloys with different atomic ratios are used as Schottky contact materials. • Excessive reaction between the metal and the SiC interface should be avoided to form a uniform Schottky contact interface. • Improve the interface homogeneity and electrical characteristics of SBD at high annealing temperature. In this work, we studied different proportions of Mo-C alloy Schottky contacts. Compare the electrical characteristics and SiC interface with the Mo/4H-SiC based diodes. The Schottky interface obtained was studied at different annealing temperatures and its electrical properties were analyzed. Analyze electrical performance through temperature-related current–voltage (I-V) and capacitance–voltage (C-V) measurements. The experimental results showed that the metallic Mo-C alloy (9:1) Schottky contact had good stability and interface characteristics at high annealing temperatures. When annealing at 900 °C, its ideality factor approached 1 and the barrier height reached 1.04 eV. The TEM images also indicated that the Mo-C alloy reduced the solid-state reaction, which improved the inhomogeneity of the Schottky interface. [ABSTRACT FROM AUTHOR]

• The insertion of Al 2 O 3 reduces the diffusion of Ti into SiC. • The introduction of Al 2 O 3 can successfully Increase the forward turn-on voltage. • Al/Ti/Al 2 O 3 /4H-SiC Schottky diode the ideality factor approaches unit. In this paper, an Al/Ti Schottky-electrode was fabricated on a 4H- SiC surface via sputtering, and an Al 2 O 3 layer was inserted into the metal semiconductor contact-surface using atomic-layer deposition. We studied the inhomogeneity of the Schottky-barrier height by inserting the dielectric layer (Al 2 O 3) with different thicknesses. The Schottky-barrier heights and ideality factors were extracted for different measurement temperatures. The experimental results show that the barrier height changes to only 9% and the ideality factor approaches 1. Moreover, with the insertion of Al 2 O 3 , the difference between ∅ eff and ∅ B 0 is most closer. This indicates the Al 2 O 3 layer can passivate the surface defects to improve the contacts inhomogeneity. The TEM images also indicate that the insertion of Al 2 O 3 reduces the diffusion of Ti into SiC to start a solid state reaction to form titanium silicides and carbides co-exist at the interface, which improves the inhomogeneity of the Schottky interface. In particular, the thickness of Al 2 O 3 is 0.8 nm. [ABSTRACT FROM AUTHOR]

This paper describes a single-event burnout (SEB) simulation for a conventional GaN MISFET field plate (FPC-MISFET) and a MISFET with an embedded pn junction (EJ-MISFET). The SEB triggering mechanism is affected by impact ionization. The electrons, which are induced by heavy ion exposure, can rapidly move to the drain, which leads to strong impact ionization around the drain. Compared to the FPC-MISFET, both the peak electric field and the impact ionization around the drain are reduced in the GaN MISFET with the embedded pn junction. The proposed EJ-MISFET also shows improved SEB performance. For a heavy ion, with a linear energy transfer (LET) of 0.6 pC/μm (hitting the devices) vertically, the SEB threshold voltages for the FPC-MISFET and EJ-MISFET are 520 and 760 V, respectively. Unlabelled Image • The SEB performance of GaN MISFET with embedded pn junction is investigated. • Compared to conventional GaN MISFET, the SEB threshold voltage in proposed GaN MISFET is enhanced by 46%. • The improvement of SEB performance is due to embedded pn junction. [ABSTRACT FROM AUTHOR]