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Summary Generating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller. [ABSTRACT FROM AUTHOR]

For the time and frequency signals of Beidou satellites, a high-accuracy phase frequency detection technology based on phase group synchronization is proposed. Using the Beidou receiver and satellite signals as the frequency standard and the measured signals, respectively. The Beidou receiver and the satellite signals are sent to the phase coincidence detector of the different frequencies to generate a phase coincidence point pulse, which is sent to the different frequency phase detector as a control signal to generate the phase differences between the Beidou receiver and satellite signals, and then complete the high-accuracy phase synchronization between the Beidou receiver and satellite signals. Experimental results show that when the delay resolution reaches ps level, the phase synchronization accuracy of the system can reach 10 ps, which has the characteristics of small phase noise, low development cost, simple circuit structure, and high synchronization accuracy compared with the traditional phase synchronization technologies. Therefore, it would be widely used in satellite positioning, astrometry, precision navigation, aerospace, satellite launch, power transmission, communications, radar, and other high-tech fields. [ABSTRACT FROM AUTHOR]

Cosmic microwave background (CMB) experiments have deployed focal planes with O (10 4) transition edge sensor (TES) bolometers cooled to sub-Kelvin temperatures by multiplexing the readout of many TES channels onto a single pair of wires. Digital Frequency-domain Multiplexing (DfMux) is a multiplexing technique used in many CMB polarization experiments, such as the Simons Array, SPT-3 G, and EBEX. The DfMux system studied here uses LC filters with resonant frequencies ranging from 1.5 to 4.5 MHz connected to an array of TESs. Each detector has an amplitude-modulated carrier tone at the resonant frequency of its accompanying LC resonator. The signal is recovered via quadrature demodulation where the in-phase (I) component of the demodulated current is in phase with the complex admittance of the circuit and the quadrature (Q) component is orthogonal to I. Observed excess current noise in the Q component is consistent with fluctuations in the resonant frequency. This noise has been shown to be non-orthogonal to the phase of the detector's responsivity. We present a detailed analysis of the phase of responsivity of the TES and noise sources in our DfMux readout system. Further, we investigate how modifications to the TES operating resistance and bias frequency can affect the phase of noise relative to the phase of the detector responsivity, using data from Simons Array to evaluate our predictions. We find that both the phase of responsivity and phase of noise are functions of the two tuning parameters, which can be purposefully selected to maximize signal-to-noise (SNR) ratio. [ABSTRACT FROM AUTHOR]

This paper introduces a low-complexity start–stop true random number generator (TRNG) utilizing jitter in ring oscillators (ROs). Incorporating phase detectors enhances entropy extraction from the same number of ROs. The raw bits undergo online post-processing using the SHA-1 algorithm, which is widely supported by many programming languages. The output bit streams pass all NIST statistical tests (SP 800-22 and SP-90B). Bits are generated on demand, enhancing security by preventing eavesdropping during continuous bit production. The TRNG maintains its performance regardless of the FPGA manufacturer. [ABSTRACT FROM AUTHOR]

A phasemeter as a readout system for the inter-satellite laser interferometer in a space-borne gravitational wave detector requires not only high accuracy but also insensitivity to amplitude fluctuations and a large fast-acquiring range. The traditional sinusoidal characteristic phase detector (SPD) phasemeter has the advantages of a simple structure and easy realization. However, the output of an SPD is coupled to the amplitude of the input signal and has only a limited phase-detection range due to the boundedness of the sinusoidal function. This leads to the performance deterioration of amplitude noise suppression, fast-acquiring range, and loop stability. To overcome the above shortcomings, we propose a phasemeter based on a tangent phase detector (TPD). The characteristics of the SPD and TPD phasemeters are theoretically analyzed, and a fixed-point simulation is further carried out for verification. The simulation results show that the TPD phasemeter tracks the phase information well and, at the same time, suppresses the amplitude fluctuation to the noise floor of 1 μrad/Hz1/2, which meets the requirements of GW detection. In addition, the maximum lockable step frequency of the TPD phasemeter is almost three times larger than the SPD phasemeter, indicating a greater fast-acquiring range. [ABSTRACT FROM AUTHOR]

This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable. [ABSTRACT FROM AUTHOR]

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s. [ABSTRACT FROM AUTHOR]

In this paper, a frequency discrimination method using a multiplicative-integral and linear transformation network is proposed. In this method, two preset differential frequency signals and frequency modulation signals are transformed by multiplication and integration, and then the instantaneous frequency parameters of the frequency modulation signal are accurately analyzed by the linear transformation network to restore the original modulation signal. Compared with the phase discriminator, the simulation results show that this method has a higher frequency discrimination bandwidth. In addition, this method has better anti-noise performance, and the frequency discrimination distortion caused by noise with a different Signal-to-Noise Ratio is reduced by 33.80% on average compared with the phase discriminator. What is more, the carrier center frequency error has little influence on the frequency discrimination quality of this method, which solves the problem that most common frequency discriminators are seriously affected by the carrier center frequency error. This method requires a low accuracy of carrier center frequency, which makes it extremely suitable for digital frequency discrimination technology and can meet the needs of various frequency discrimination occasions. [ABSTRACT FROM AUTHOR]

The results of a study of three methods for determining the phase of signals from a heterodyne microwave interferometer are presented: phase calculation by processing digitized signals using software methods; direct phase measurement with an AD8302 detector; and phase measurements by quadrature detection. The results of phase measurements obtained by these methods are compared. The values of errors of each method are estimated and ways to minimize them are considered. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator. Post-layout simulations show that phase noise suppression is about 13 dB at 100 MHz offset for a division ratio of 2. [ABSTRACT FROM AUTHOR]

To measure the micro-displacement reliably with high precision, a single-ended eddy current sensor based on temperature compensation was studied in detail. At first, the principle of the eddy current sensor was introduced, and the manufacturing method of the probe was given. The overall design plan for the processing circuit was induced by analyzing the characteristics of the probe output signal. The variation in the probe output signal was converted to pulses with different widths, and then it was introduced to the digital phase discriminator along with a reference signal. The output from the digital phase discriminator was processed by a low-pass filter to obtain the DC component. At last, the signal was amplified and compensated to reduce the influence of temperature. The selection criteria of the frequency of the exciting signal and the design of the signal conditioning circuit were described in detail, as well as the design of the temperature-compensating circuit based on the digital potentiometer with an embedded temperature sensor. Finally, an experimental setup was constructed to test the sensor, and the results were given. The results show that nonlinearity exists in the single-ended eddy current sensor with a large range. When the range is 500 μm, the resolution can reach 46 nm, and the repeatability error is ±0.70% FR. Within the temperature range from +2 °C to +58 °C, the voltage fluctuation in the sensor is reduced to 44 mV after temperature compensation compared to the value of 586 mV before compensation. The proposed plan is verified to be feasible, and the measuring range, precision, and target material should be considered in real-world applications. [ABSTRACT FROM AUTHOR]

We demonstrate coherent optical frequency dissemination over a distance of 972 km by cascading two spans where the phase noise is passively compensated for. Instead of employing a phase discriminator and a phase locking loop in the conventional active phase control scheme, the passive phase noise cancellation is realized by feeding double-trip beat-note frequency to the driver of the acoustic optical modulator at the local site. This passive scheme exhibits fine robustness and reliability, making it suitable for long-distance and noisy fiber links. An optical regeneration station is used in the link for signal amplification and cascaded transmission. The phase noise cancellation and transfer instability of the 972-km link is investigated, and transfer instability of 1.1 × 10−19 at 104 s is achieved. This work provides a promising method for realizing optical frequency distribution over thousands of kilometers by using fiber links. [ABSTRACT FROM AUTHOR]

The Simons Observatory (SO) is a cosmic microwave background instrumentation suite being deployed in the Atacama Desert in northern Chile. The telescopes within SO use three types of dichroic transition-edge sensor (TES) detector arrays, with the 90 and 150 GHz Mid-Frequency (MF) arrays containing 65% of the approximately 68,000 detectors in the first phase of SO. All of the 26 required MF detector arrays have now been fabricated, packaged into detector modules, and tested in laboratory cryostats. Across all modules, we find an average operable detector yield of 84% and median saturation powers of (2.8, 8.0) pW with interquartile ranges of (1, 2) pW at (90, 150) GHz, respectively, falling within their targeted ranges. We measure TES normal resistances and superconducting transition temperatures on each detector wafer to be uniform within 3%, with overall central values of 7.5 m Ω and 165 mK, respectively. Results on time constants, optical efficiency, and noise performance are also presented and are consistent with achieving instrument sensitivity forecasts. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246. [ABSTRACT FROM AUTHOR]

This paper presents a low-power multi-rate clock and data recovery (CDR) for receivers of serial links. Its basic structure includes a current-mode logic bang–bang phase detector sampled by low-mismatch half-rate quadrature clocks, which are generated by voltage-controlled delay line (VCDL) and two-stage time-average circuits. The total delay of VCDL can be adjusted to accommodate a wide frequency range by its bias voltage, which is generated by a delay-locked-loop-based bias generator. The quadrature clocks are 64-phase adjustable with high linearity, which is realized by phase interpolator with a compensating structure. The parameters of phase detection loop are well designed to satisfy both high jitter tolerance and low clock jitter. Fabricated in a 40 nm CMOS technology, the CDR occupies an active area of 0.036 mm 2 only. With a wide operating range of 2–20 Gb/s, the chip consumes 62.5 mW, corresponding to an energy efficiency of 3.1 pJ/bit. The measured root-mean-square jitter and peak-to-peak jitter for the recovered clock at 9 GHz are 1.9 and 10.8 ps, respectively. [ABSTRACT FROM AUTHOR]

The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was 103.2μW demonstrating the effectiveness of 10T PFD over other conventional PFDs. [ABSTRACT FROM AUTHOR]

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure. [ABSTRACT FROM AUTHOR]

Abstarct: In this work, a new Charge Pump (CP) design including a Phase and Frequency Detector (PFD) is presented. The PFD is designed using the common topology of two D Flip Flops, AND gates and a controllable reset delay for the DFFs to compensate for process and tem-perature variations. The Charge Pump is using a bias cell which generates the necessary bias voltages, the clock driving cells which convert the single-ended UP and DOWN signals to differential and the core cell which comprises of six slices, each one contributing the same amount of current to the low pass filter. The output current is programmable with minimum and maximum values of 25 uA and 150 uA respectively. An extra option to double the output current is also added. A new technique has been adopted in terms of layout floorplan of the charge pump slices to eliminate the clock feedthrough mismatch between the differential UP and DOWN sig-nals. The technology used in this work is TSMC 65nm, while the supply voltage is 1 V. The main characteristics of the proposed design are modularity, low power, low noise, great linearity, small area, simplicity and performance. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

The sensitivity of future gravitational wave (GW) detectors, such as the Einstein Telescope (ET), is constrained by quantum noise across the entire frequency range (10 Hz–10 kHz) and by magnetic noise at low frequencies (a few Hz to around 100 Hz). This article examines optimizing mechanisms to achieve efficient squeezing for reducing quantum noise, and also highlights the need to mitigate magnetic noise, through ongoing strategies. [ABSTRACT FROM AUTHOR]

Natural deep eutectic solvents (NADES) have been used in chromatography as extraction media and HPLC mobile phase additives, but only once have they been used as HPLC major mobile phase component. This review illustrates current knowledge and major limitations on use of NADES in HPLC mobile phase as well as to propose possible NADES may be ready for use as HPLC mobile phases and the detectors they can be used with. High viscosity is one of the major roadblocks encountered when using NADES as a mobile phase component in HPLC regardless of detectors employed. A comprehensive review of published literature was conducted to identify articles that focused on using NADES as extraction solvents for natural products, particularly polyphenols or reported NADES viscosities to establish a database of NADES which could be used as HPLC mobile phases under various conditions. Other identified challenges that limit NADES application in HPLC mobile phase include low volatility, NADES wavelength cutoff (UV and Fluorescent detectors) and impurities. Methods for overcoming these limitations are discussed so that NADES may be more integrated into HPLC systems in the future. • NADES have been utilized as additives or a major component in HPLC mobile phase. • Current limitations on use of NADES in HPLC mobile phase were discussed. • Only 20% of NADES used for polyphenol extraction had their viscosities ascertained. • Possible NADES candidates to be investigated as a HPLC mobile phase were suggested. • Future research directions to overcome current limitations were discussed. [ABSTRACT FROM AUTHOR]

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ -V characteristics of the PFD were found to have better linearity across the range of − π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μ W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2. 95 μ s , and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm 2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems. • The simple circuit of Phase Frequency Detector avoids the use of reset path to achieve zero dead zone and high operating frequency. • Pass transistor logic employed to the second stage of PFD which enhance the operating frequency and simplify the circuit. • Taguchi DoE and ANOVA optimization methodology have been used to find out the sizes of MOS transistors and supply voltage to achieve optimized results. • Optimized PFD has lower phase noise, low power dissipation, lesser delay and high maximum operating frequency thus beneficial for low power and high speed frequency synthesizer applications. • Significant high speed, low power dissipation, low THD and lesser chip area of Frequency synthesizer making it suitable for use in high-speed devices such as radio receivers and GPS systems. [ABSTRACT FROM AUTHOR]

A new optical beam splitting method is proposed, based on which the optical frame camera capable of capturing multiple frames in a single exposure is designed and experimentally verified. The operation of the frame camera is based on an ultra-fast response semiconductor detector. It is equipped with an optical beam splitter and an optical imaging module. The ultrafast semiconductor detector receives an optical pulse that produces a transient refractive index change, and ultrafast physical processes are recorded by diffracting the probe laser through the transient phase grating. The interaction of an X-ray pulse with a semiconductor detector to produce a phase grating is simulated, based on the Monte Carlo method. The optical beam splitting mode separates a laser into two optical pulses with a certain time difference in the direction of polarization perpendicular to each other. The imaging module filters the diffracted probe laser in the spectral plane and then images multiple frames. The frame camera was used to record the temporal and spatial distribution characteristics of femtosecond laser pulses with a temporal resolution of 4.1 ps. This frame camera has great potential and value for applying to experimental studies of inertial confinement fusion. [ABSTRACT FROM AUTHOR]

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0. 18 μ m mixed-signal CMOS technology with an active area of 0.109 μ m 2 . The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications. [ABSTRACT FROM AUTHOR]

In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μ A. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μ m 2 . • The reference spur in a PLL is minimised in this paper. • The reset pulse width of the phase frequency detector (PFD) is reduced. • The current mismatch of the charge pump (CP) is decreased. • A novel replica technique based dead zone free PFD is proposed. • To reduce the reset pulse width of the PFD, replica technique is adopted. • A self-cascode current-splitting CP is proposed. • To reduce current mismatches in the CP, self-cascode current-splitting technique is used. [ABSTRACT FROM AUTHOR]

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm 2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100 MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoM J) of −238.0 dB. [ABSTRACT FROM AUTHOR]

Electricity generated from the present-day large-capacity wind turbine generators (WTGs), i.e. doubly-fed induction generators (DFIGs), is commonly accumulated at the collector station by intricate collector lines (CLs) and then evacuated through the transmission line (TL) to the utility grid. The traditional over-current protection of such CLs may face difficulty due to variable control action of the WTG and power electronic-based voltage support devices (e.g. STATCOM) at collector substation bus (CSB). In this paper, a superimposed least-square approach based transient detector phase coefficient of modal current for detecting faulty CLs/TL and magnitude coefficients of phase currents for identifying the accurate faulty phase of the CLs for two standard multi-segment test systems. The algorithm is also validated through the modified IEEE 9-bus system. The detection and phase identification times of faults are found less than 8 ms and 15 ms, respectively from 3600 fault cases. These test systems are modeled in RSCAD software and validated through RTDS hardware simulator. Further, the traditional over-current scheme is verified using SEL-451 PMU and SEL-3573 PDC data. Finally, the proposed algorithm is performed in MATLAB and validated through OPAL-RT (OP5600) using the generated data from RTDS. The use of single-end data at a lower sampling rate (1 kHz), obtained results and real-time validation justify the efficacy of the proposed method. [Display omitted] • Improved fault diagonosis for collector lines of DFIG-wind farm. • Performance of overcurrent protection is verified through SEL-451. • Features extracted fromvlocal modal current using least square transient detector. • Detection and phase identification of fault at less than 8 ms and 15 ms respectively. • Simulation performed by RSCAD/RTDS and algorithm validated through OPAL-RT (OP5600). [ABSTRACT FROM AUTHOR]