A novel replica technique based dead zone free phase frequency detector and a self-cascode current-splitting charge pump for a low-spur low power phase-locked loop architecture.

In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μ A. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μ m 2 . • The reference spur in a PLL is minimised in this paper. • The reset pulse width of the phase frequency detector (PFD) is reduced. • The current mismatch of the charge pump (CP) is decreased. • A novel replica technique based dead zone free PFD is proposed. • To reduce the reset pulse width of the PFD, replica technique is adopted. • A self-cascode current-splitting CP is proposed. • To reduce current mismatches in the CP, self-cascode current-splitting technique is used. [ABSTRACT FROM AUTHOR]