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For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (V t ) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., V t reduces), whereas conversely, we see a negative V t shift under positive stress and V t increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed.

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS2 layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS2, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT's advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. [ABSTRACT FROM AUTHOR]

At present, germanium (Ge) as a high-mobility material is considered as a possible replacement for Si in microelectronics. The main obstacle in the method is the large vacancy concentration obtained after the implantation of shallow donors. This prevents the formation of n + regions and has a negative impact on device performance. One way to eliminate the detrimental effects of such defects is through the codoping approach. In this study, the behavior of Na impurities in germanium together with the formation of defect complexes with vacancies, divacancies and shallow donors (P and As) were investigated using hybrid density functional theory calculations. The site preference, diffusion barriers, charge states and binding energies of various complexes, as well as the activation of donor–vacancy complexes with both F and Na codoping were investigated. For this purpose, two extreme cases were considered. Firstly, we calculate the concentrations of substitutional and interstitial Na together with monovacancies in the case of quasi-equilibrium conditions realized for doping from melt. Another extreme case is Na codoping during ion implantation. Our calculations show that Na passivates vacancies, divacancies and donor–vacancy complexes (E-centers) with a large energy gain, which prevents rapid donor diffusion similar to the case of doping with fluorine. We have shown that the passivation of E-centers with both F and Na impurities leads to the back transformation of such complexes into shallow donors. This means that codoping with Na may neutralize the harmful effects of vacancies and is a perspective for defect engineering. [ABSTRACT FROM AUTHOR]

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell–Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10−15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10−11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities. [ABSTRACT FROM AUTHOR]

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. [ABSTRACT FROM AUTHOR]

Vertical Nanosheet Transistors serves as a potential substitute for the Nanowire and FinFET architecture at advanced technology nodes on account of higher drive current and superior control of short channel effects. In this article, a novel analysis of various stacked high-K dielectrics in n-type Vertical C-shaped Silicon Channel Nanosheet Field Effect Transistor (nVCNFET) is implemented. In-depth analysis is done on the effects of stacked high-K dielectrics on nVCNFET device performance and short channel effects. The nVCNFET with optimized gate oxide stack of Al2O3-TiO2 exhibits a remarkable current ratio of 3.2 × 1016, which is 107 times efficient over the reported Vertical Nanosheet FETs (NSFET) up to date. The Device performance and scaling compatibility of nVCNFET for sub-10 nm and 5 nm technology nodes are demonstrated to certify the device's reliability. On the contrary, the proposed nVCNFET maintains ideal Subthreshold Swing (< 60 mV/decade) and yields 60% lesser DIBL value (8 mV/V) over the other Silicon-NSFETs. This concludes nVCNFET, a befitting candidate for low power and Dynamic Random Access Memory (DRAM) applications. [ABSTRACT FROM AUTHOR]

Non-quasi-static small-signal models are essential for exploring the high-frequency (HF) behavior of the FinFET. In this paper, we propose a modified small-signal model for a multi-fin (MF) FinFET to extract the intrinsic and extrinsic parameters using Y-parameters extracted from TCAD. The gate resistance plays a significant role in optimizing the HF behavior with the varying numbers of fins in the MF configuration. We also test the model's accuracy with increasing temperature up to 425 K. Using well-calibrated TCAD models, we further analyze the analog and linearity figures of merit, including cutoff frequency (f T ), the maximum frequency of oscillation (f max ), transconductance (g m ) and higher-order derivatives such as g m 2 , g m 3 , VIP 2 , and VIP 3 . Thus, the behavior of intrinsic and extrinsic parasitic resistance and capacitance is worth exploring to determine the device operation in the frequency range of >100 GHz. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. [ABSTRACT FROM AUTHOR]

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling. [ABSTRACT FROM AUTHOR]

This paper investigates the design and analog the behaviour of an L-Patterned Negative-Capacitance Dual Tunneling Vertical TFET (L-NC-DT-VTFET) device with the idea of corner tunnelling and vertical tunnelling. In this proposed structure, the tunnel junction can be used over a large region in a perpendicular alignment to the channel direction. Furthermore, the gate of an L-NC-DT-VTFET is positioned vertically in the L-shaped to boost ON current. Moreover, adding the p+ pocket in the channel helps reduce ambipolar current and improves the ON current. By adjusting the thicknesses of the ferroelectric layer and pocket, the device design is created deliberately to improve the on current to off current ratio $${{({I_{ON}}} \mathord{\left/ {\vphantom {{({I_{ON}}} {{I_{OFF}}}}} \right. \kern-\nulldelimiterspace} {{I_{OFF}}}})$$ (I O N / I O F F ). The tunnelling current generated by dual tunnelling and negative capacitance extricates the collected holes, minimising the kink effect. The characteristics of the proposed L-NC-DT-VTFET structure are examined to those of known TFET architectures, and the suggested design appears to be a better match for high-performance, low-power applications as the device design maximise vertical tunnelling over corner tunnelling. [ABSTRACT FROM AUTHOR]

In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed. [ABSTRACT FROM AUTHOR]

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as ‘More Moore’1 but also introduces multifunctionalities for ‘More than Moore’2 technologies. Although silicon-based 3D integrated circuits are commercially available3–5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7–10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.Monolithic three-dimensional integration of two-dimensional field-effect transistors enables improved integration density and multifunctionality to realize ‘More Moore’ and ‘More than Moore’ technologies. [ABSTRACT FROM AUTHOR]

With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling. [ABSTRACT FROM AUTHOR]

Hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on the computation-in-memory (CIM) architecture are contemplated as the future generation of digital integrated circuits. It overcomes the limitations of von-Neumann architecture by offering solutions to problems such as memory wall and standby power dissipation. In this work, we have developed hybrid logic gates, such as AND/NAND, OR/NOR, and XOR/XNOR, for CIM architecture by integrating three terminal spin-Hall effect assisted spin transfer torque (SHE + STT) MTJs with standard CMOS. To write the MTJs an auto-write-stopping (AWS) circuit is adopted, whereas to perform the logic operations and produce the corresponding outputs, an improved sense amplifier circuit (ISA) is employed. All the hybrid logic gates are investigated for key performance indicators such as power, delay, device count, and power delay product (PDP). The results are compared with their conventional counterparts. The comparison reveals that the ISA + AWS-based hybrid gates dissipate 50.52% lower total power. The worst-case read delay of ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates are 27.41%, 13.4%, and 21.28% lower. Meanwhile, the reduction of read PDP (write PDP) is 47.64% (37.09%), 25.78% (36.29%), and 39.31% (35.48%) observed with ISA + AWS hybrid AND/NAND, OR/NOR, and XOR/XNOR gates in comparison with the conventional counterparts. Hence the ISA + AWS gates are superior in terms of total power dissipation, worst read delay, and read/write PDP. Further, we have conducted Monte-Carlo simulations on all the logic circuits to study the parameter variations during fabrication. [ABSTRACT FROM AUTHOR]

A novel hybrid double gate junctionless transistor with gate engineering using a dual gate oxide stack has been proposed to improve short-channel effects and gate controllability for digital applications. The performance analysis and comparison of the proposed device with a DGLK junctionless transistor has been reported, hybrid Junctionless double gate transistor device has provided SS 61.4 mV/decade which is close to the ideal value of 60 mV/decade and 27.91% improvement, DIBL of 7.368 mV/V with 88.487% improvement, off current is 35.6 fA/µm, which is nearly 1.6 x10-6 times less and very high switching ratio of 1.648x 1010 which is 5.455 x106 times higher than junctionless double gate transistor. Also, the effect of variations in gate dielectric, spacer length has been studied. [ABSTRACT FROM AUTHOR]