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As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. To address the realities of process integration, we describe the features and issues associated with integrating this DRAM into SOI technology, including deep trench processing and floating body effects. After a brief description of the macro architecture, details are provided on the three-transistor micro sense amplifier scheme, which is key to achieving a high transfer ratio with minimal area overhead. The paper concludes with hardware results and a summary.

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with

A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.

A multiply-adder that achieves a 56-b X*X+Z function with cycle time of 18 ns in a 1- mu m CMOS technology is discussed. The organization requires only two pipeline stages, ensuring quick recovery from branch instructions. The design is for the fraction part of a 64-b multiply-adder and is itself 56 b wide at input and output. To achieve high performance and reasonable density, it uses Booth encoding and a Wallace tree array. Data are captured at the input latches and routed immediately to the Booth encoders, which, in addition to encoding the X input, also provide driven Y and Y-bar signals for the array. The Z input is also captured and routed to the Z shifter. Encoded X, Y-bar, and Z and shifted Z signals are all routed to the partial product array. Booth encoding for 56 b produces 29 partial products; the Z input raises the number of terms to be added to 30. The partial product array reduces this to three, at which point a second latch captures the reduced result. After the latch, the three terms are reduced to two in a full adder, and the resulting two terms added and renormalized. >