Search

This paper presents a time-resolved (TR) CMOS image sensor (CIS) using two-tap near-infrared (NIR) lock-in pixels with background light (BGL) cancelling capability for remote heart rate (HR) detection. Aimed to the application, the sensor features a 1024 (V) $\times $ 1280 (H) spatial resolution with 412 (V) $\times $ 1280 (H) region-of-interest-readout (ROI-readout) at 30 fps, a high sensitivity of 134.8 ke−/lux $\cdot $ s, and an ultra-low temporal random noise of 1.13 $\mathrm {e}_{\mathrm {rms}}^{\mathrm {-}}$ at analog gain of 64. A maximum charge modulation ratio of 90.1% is obtained for realizing lock-in operation by means of in-pixel lateral electric field charge modulator (LEFM). The remote HR detection is achieved by capturing the heart-beat-induced temporal variation of the oxy-hemoglobin (HbO2) concentration by the developed TR CIS with NIR lock-in technique, and larger than 98% detection accuracies are attained under both non-visible-light condition and fluctuant brightness ambient-light environments. This remarkable feature demonstrates the superiority of the proposed method for driver monitoring applications in particular.

Controlling and engineering the particle composition of semiconductor alloys is one of the topmost targets in the field of semiconductor materials science and technology. Quantum dot (QD) nanocrystals offer an unmatched opportunity to obtain a wide range of composition-controlled alloys and have captivated a great deal of interest recently. Herein, we report on band gap engineering via tuning and controlling the sulphur molar fraction (ternary shell layer) of quaternary/ternary core/shell alloyed CdZnSeS/ZnSeS QDs. Varying optical properties were exhibited by the alloyed QDs but a uniform particle size distribution was maintained across all the compositions. The alloyed QDs displayed bright emission colours under UV irradiation, whereas the photoluminescence quantum yields (PL QY) were in a remarkable range of 36–98%. Non-linearity of the lattice parameter was an indication of gradient alloying of the nanocrystals, whereas the kinetics of the optical properties unravelled the effect of intrinsic optical bowing. Displacement of bond length and anion mismatch influenced the optical properties of the QDs with respect to the variation in the PL QY. Alloyed CdZnSeS/ZnSe1.0S1.3 QDs with a spectacular PL QY were exploited as an ultrasensitive fluorescence reporter in a conjugated molecular beacon (MB) assay to detect influenza virus H1N1 RNA. Our detection system was rapid and highly sensitive for detecting extremely low concentrations of H1N1 RNA (down to 2 copies per mL), specific and versatile (detects H1N1 RNA in human serum). For proof of concept, the alloyed CdZnSeS/ZnSe1.0S1.3 QD-MB bioprobe exhibited a superior 12-fold sensitivity over an alloyed CdZnSeS-MB probe, while a conventional CdSe/ZnS-MB probe could not detect extremely low concentrations of influenza virus H1N1 RNA.

A programmable sub-nanosecond time-gated four-tap CMOS lock-in pixel (LIP) image sensor that uses an in-pixel pulse generator (PG) is developed for time-resolved (TR) biomedical imaging applications, such as a fluorescence lifetime imaging microscopy (FLIM). We demonstrate the system’s effectiveness with simulations and measurements. Using pixel-level PG circuits, very narrow time windows (TWs) that are less than 0.8 ns can be used for charge modulation. This rapid gating allows very weak signals from living cells to be captured with a high signal-to-noise ratio (SNR). The prototype CMOS imaging system displays a fast intrinsic response of 170 ps at 472 nm and a very low temporal random noise of 0.85 e-rms at 45 frames/s under truly correlated-double-sampling operation using two-stage charge transfer. Four outputs from the LIPs allow real-time fluorescence lifetimes (FLTs) measurement, even from samples with multiple FLT components.

A large full well capacity (FWC) for wide signal detection range and low temporal random noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two in-pixel storage diodes (SDs) has been developed and presented in this paper. For fast charge transfer from photodiode to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal random noise of 1.2e-rms at 20 fps with true correlated double sampling operation and fast intrinsic response less than 500 ps at 635 nm. The proposed imager has an effective pixel array of ${\text{128}}{\text{(H)}}\times {\text{256}}{\text{(V)}}$ and a pixel size of ${\text{11.2}}\times {\text{11.2}}\, \mu {\text{m}}^{2}$ . The sensor chip is fabricated by Dongbu HiTek 1P4M 0.11 $\mu {\text{m}}$ CIS process.

In this paper, a wide dynamic range (WDR) CMOS image sensor (CIS) with a charge splitting gate (SG) and two storage diodes (SDs) is presented. By using single-gate on/off control with the SG, photocurrent path to the first (SD1) or second storage diodes (SD2) is switched alternatively and periodically during exposure and signal electrons generated in a photodiode (PD) are transferred to and accumulated in the SD1 or SD2. By setting a large ratio of the off-time to on-time of the SG, two different sensitivity signals, which are originated by the same photodiode, are generated and a WDR image signal is obtained. This technique has a distinct advantage on mitigating the problem of motion artifact in WDR imaging with high and low sensitivity signals and flexible dynamic control of the dynamic range. An experimental WDR CMOS image sensor with 280 (H) &times, 406 (V)-pixel array consisting of 14 sub-arrays, each of which have 20 (H) &times, 406 (V) pixels, was implemented and tested. For the SG on/off-time ratio of 30 and 279, the DR of 93 dB and 104 dB, respectively, was demonstrated. The effect of the proposed WDR imaging operation on the reduced motion artifact was experimentally confirmed.

A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with two-tap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of $1.75{\text{e}}^{-}_{\text{rms}}$ with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results.

We propose a novel full-electronically controlled laser confocal microscope in which a liquid-crystal-on-silicon spatial light modulator and a custom CMOS imaging sensor are synchronized for performing multi-beam confocal imaging. Adaptive wavefront modulation for functional multi-beam excitation can be achieved by displaying appropriate computer generated holograms on the spatial light modulator, in consideration of the numerical aperture of the focusing objective. We also adopted a custom CMOS imaging sensor to realize multi-beam confocal microscopy without any physical pinhole. The confocality of this microscope was verified by improvements in transverse and axial resolutions of fluorescent micro-beads.

A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of $220~\mu \text{V}/\text{e}^{ {{-}}}$ and a low read noise of 0.27e $^{-}_{\text {rms}}$ using correlated multiple-sampling-based readout circuitry.

We have developed and evaluated the large full well capacity (FWC) for wide signal detection range and low temporal noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two storage-diodes (SDs). In addition, for fast charge transfer from photodiode (PD) to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large FWC of approximately 7000e-, low temporal random noise of 1.17e-rms at 45fps with true correlated double sampling (CDS) operation, and fast intrinsic response less than 500ps at 635nm. The proposed imager has an effective pixel array of 128(H)×256(V) and a pixel size of 11.2×11.2μm2. The sensor chip is fabricated by a Dongbu HiTek 1P4M 0.11μm CIS process.

Recently, CMOS time-resolved imaging devices are being widely used for scientific and medical applications. A fluorescence lifetime imaging microscopy (FLIM), which is a powerful analysis tool in fundamental physics as well as in the life science, is a typical application for the time-resolved imaging devices. For better time-resolution in the lock-in pixel design, a multi-tap pixel architecture is very effective and useful. In this paper, we have proposed an 8-tap CMOS lock-in pixel with lateral electric field charge modulator (LEFM) and demonstrated the effectiveness of designed pixel by CAD simulation. The proposed pixel makes possible to measure the highly time-resolved images with a high signal to noise ratio (SNR) and to observe various images of cells even if a sample has a multi-lifetime component. An 8-tap time-resolved CMOS image sensor chip is developed by 0.11μm 1P4M CIS process technology.

Fluorescence-based time-resolved (TR) analysis techniques are fundamental and effective methods in life science and medicine. Among others, fluorescence lifetime imaging microscopy (FLIM) is one of the representative measurement techniques for biomedical applications. Recently, advanced all-solid-state imaging devices for FLIM, e.g., a CCD with optional electron-multiplication (EM) readout, a single-photon avalanche diode (SPAD), and a TR CMOS image sensor (CIS), have been reported [1–3]. These devices can be implemented compactly in comparison with the typical FLIM systems such as a time-correlated single-photon counting (TCSPC) system [4]. However, imaging devices based on the CCD or SPAD still have some issues, including the need for specialized fabrication processes, use of higher voltages, and greater circuit complexity. The recent TR CIS with two taps in a pixel [3] shows us a way to realize real-time lifetime imaging, but the two-tap CIS has a limitation that a sample's lifetime cannot be measured in real time if the sample has multi-exponential decay components.

In the past several years, CMOS image sensors (CISs) with sub-single-electron noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high pixel conversion gain (CG) [1,2], and a high-gain readout circuitry with noise-reduction capabilities [3,4]. Recently, a reset-gate-less (RGL) CMOS image sensor has been reported [5]. It shows an excellent read noise performance using an optimized pixel structure for high CG and high-gain column ADC with multiple sampling. In this technique, however, a very high pulsed voltage of approximately 25V for the FD reset is essential to cause a punch-through effect. It is not suitable for image sensors with high pixel resolution and high-speed signal readout.

In extremely low-light conditions, random telegraph signal (RTS) noise and dark current white defects become visible. In this paper, a multi-aperture imaging system and selective averaging method which removes the RTS noise and the dark current white defects by minimizing the synthetic sensor noise at every pixel is proposed. In the multi-aperture imaging system, a very small synthetic F-number which is much smaller than 1.0 is achieved by increasing optical gain with multiple lenses. It is verified by simulation that the effective noise normalized by optical gain in the peak of noise histogram is reduced from 1.38e- to 0.48e- in a 3 × 3-aperture system using low-noise CMOS image sensors based on folding-integration and cyclic column ADCs. In the experiment, a prototype 3 × 3-aperture camera, where each aperture has 200 × 200 pixels and an imaging lens with a focal length of 3.0 mm and F-number of 3.0, is developed. Under a low-light condition, in which the maximum average signal is 11e- per aperture, the RTS noise and dark current white defects are removed and the peak signal-to-noise ratio (PSNR) of the image is increased by 6.3 dB.

An extremely low temporal noise and wide dynamic range CMOS image sensor is developed using low-noise transistors and high gray-scale resolution (17b) folding-integration/cyclic analog-to-digital converter (ADC). Two types of pixel are designed. One is a high conversion gain (HCG) pixel with removing the coupling capacitance between the transfer gate and the floating diffusion, and the other is a pixel for wide dynamic range (WDR) CMOS imager with a native transistor as a source follower amplifier. The CMOS image sensor that is in combination with the proposed pixels and the high performance column ADC has achieved a low pixel temporal noise of 1.1erms-, a wide dynamic range of 87.5 dB with the video rate operation (30 Hz) and the vertical fixed pattern noise of 1.08-μVrms. The implemented HCG CMOS imager and WDR CMOS imager using 0.18 μm technology have the pixel conversion gain of 73.2- and 22.8-μV/e-, respectively.

A 1.3-megapixel CMOS image sensor (CIS) with digital correlated double sampling and 17-b column-parallel two-stage folding-integration/cyclic analog-to-digital converters (ADCs) is developed. The image sensor has 0.021-erms- vertical fixed pattern noise, 1.2-erms- pixel temporal noise, and 85.0-dB dynamic range using 32 samplings in the folding-integration ADC mode. Despite the large number of samplings (32 times), the prototype image sensor is demonstrated at the video rate operation of 30 Hz by the new architecture of the proposed ADCs and the high-performance peripheral logic (or digital) parts using low-voltage differential signaling circuit. The developed 17-b CIS has no visible quantization noise at very low light level of 0.01 lx because of high grayscale resolution where 1LSB = 0.1-. The implemented CIS using 0.18- μm technology has the sensitivity of 20 V/lx ·s and the pixel conversion gain of 82 μV/e-.

A CMOS lock-in pixel image sensor with embedded storage diodes in a pixel and lateral electric field modulator (LEFM) is developed for time-resolved measurements such as a fluorescence lifetime imaging microscopy (FLIM) and near-infrared spectroscopy (NIRS). The time-resolved CMOS image sensor (CIS) with two-tap lock-in pixels achieves a very high time resolution of 10ps when images are averaged over 30 frames, a very short intrinsic response time of 180ps at 374nm, and a low temporal random noise of 1.75e-rms with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated by the device simulations and the measurements. Then, we confirmed that the developed imager is very suitable for the scientific applications such as a biomedical imaging and multifunctional cameras.

A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e− rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

In the work described in this paper, an image reproduction scheme with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor was demonstrated. The sensor captures an object by compressing a sequence of images with focal-plane temporally random-coded shutters, followed by reconstruction of time-resolved images. Because signals are modulated pixel-by-pixel during capturing, the maximum frame rate is defined only by the charge transfer speed and can thus be higher than those of conventional ultra-high-speed cameras. The frame rate and optical efficiency of the multi-aperture scheme are discussed. To demonstrate the proposed imaging method, a 5×3 multi-aperture image sensor was fabricated. The average rising and falling times of the shutters were 1.53 ns and 1.69 ns, respectively. The maximum skew among the shutters was 3 ns. The sensor observed plasma emission by compressing it to 15 frames, and a series of 32 images at 200 Mfps was reconstructed. In the experiment, by correcting disparities and considering temporal pixel responses, artifacts in the reconstructed images were reduced. An improvement in PSNR from 25.8 dB to 30.8 dB was confirmed in simulations.

A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10-V/lx·s, the conversion gain of 67- μV/e-, and linear digital code range of more than 4 decades.