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Strained-SiGe, with high-Ge-content, has recently drawn significant attention as an alternate p-channel option for advance FinFETs. Among various technological challenges, gate stack is so critical to enable high-performance FETs. In this paper, key process details of the optimized gate stacks in high-Ge SiGe, such as IL formation and passivation, are disclosed and feasibility of Vth tuning by an ultra-thin replacement metal-gate scheme down to 15nm LG is demonstrated, for the first time. Moreover, near ideal SS, excellent reliability and mobility at scaled EOTs are achieved, which has led to high transconductance devices with proper junction engineering. In addition, we demonstrate the most aggressively-scaled SiGe fins reported to date formed by 3D-Ge-condensation, exhibiting excellent short-channel characteristics.

FinFETs with strained-SiGe channel have recently drawn significant attention due to their built in uniaxial strain, higher mobility and better reliability over conventional Si FETs. Research on pure Ge has been the major focus of many institutes over the past few years. However, with high-Ge-content (HGC) SiGe one can benefit from competitive or better performance over pure Ge and overcome the thermal budget constraints required for Ge. In this paper, we briefly review our latest advancements in high-Ge-content strained-SiGe FinFETs featuring gate first and Replacement HK/MG (RMG) flows with record mobility and short-channel performance to extend the roadmap for advanced FinFET and FDSOI generations.

We demonstrate high-performance (HP) High-Ge-Content (HGC) SiGe pMOS FinFETs with scaled EOT and improved junction. For the first time, SiGe FinFET EOT scaling down to ∼7A has been achieved. In addition, improved junction and series resistance has been demonstrated for HGC SiGe, by a proper choice of spacer thickness and interface-layer as well as hot ion-implant (I/I), resulting in significant R on reduction down to 250 and 200Ω.µm, respectively. We report the highest “SiGe extrinsic g m ” reported to date with g m, LIN =0.5mS/µm and g m, SAT =2.7/2.5mS/µm at V DD =1.0/0.5V, the highest HGC SiGe I on =0.45mA/µm at fixed HP I off =100nA/µm at V DD =0.5V and the highest pMOS FinFET performance reported to date at sub-35nm L G .

Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted.

Schottky source/drain (S/D) MOSFETs hold the promise for low series resistance and extremely abrupt junctions, providing a path for device scaling in conjunction with a low Schottky barrier height (SBH). A S/D junction SBH approaching zero is also needed to achieve a competitive current drive. In this letter, we demonstrate a CMOS process flow that accomplishes a reduction of the S/D SBH for nFET and pFET simultaneously using implants into a common NiPt silicide, followed by a low-temperature anneal (500°C-600°C). These devices have high-κ/metal gate and fully depleted extremely thin SOI with sub-30-nm gate length.

Nearly damage free etching of a high mobility Si SiGe heterostructure is obtained by using very low power reactive ion etching and precise end-point detection. Conductance versus wire width plots of 0.08 μm to 1 μm wide Si SiGe quantum well wires show the combined nonconducting width at the edges to be 0.13 μm ± 0.01 μm, in agreement with weak localization studies. Mobility vs. sheet concentration measurements indicate little or no degradation in electron mobility after processing. Furthermore, our study demonstrates very little difference between wires with and without post-RIE (reactive-ion etching) annealing and passivation treatment. Application of this process for fabricating point contacts and other quantum effect devices is demonstrated.

The electronic properties of Si/${\mathrm{Si}}_{0.7}$${\mathrm{Ge}}_{0.3}$ quantum-well wires fabricated by reactive ion etching are investigated. The width of the nonconducting layer produced by the dry-etch damage and surface depletion is determined by plotting the conductance vs wire width for wires with lithographic widths ranging from 0.10 to 1.0 \ensuremath{\mu}m. The combined width of the so-called ``dead layers'' on each edge of the wire is determined to be as small as 0.13\ifmmode\pm\else\textpm\fi{}0.01 \ensuremath{\mu}m. Quantum interference effects are studied in wires with lithographic widths of W=0.23 \ensuremath{\mu}m. One-dimensional (1D) weak localization is evident in these wires at T=1.3 K in the form of a pronounced negative magnetoresistance for |B|\ensuremath{\leqslant}0.3 T. A back-gate contact is used to study the electron-transport properties in the wires, as a function of the electron sheet concentration, ${\mathit{n}}_{\mathit{s}}$. The data have been fitted to the 1D theory of weak localization, and indicate that the inelastic mean free path ${\mathit{L}}_{\mathrm{\ensuremath{\varphi}}}$ increases from 0.2 to 1.2 \ensuremath{\mu}m as ${\mathit{n}}_{\mathit{s}}$ is increased from 4.2\ifmmode\times\else\texttimes\fi{}${10}^{11}$ to 5.9\ifmmode\times\else\texttimes\fi{}${10}^{11}$ ${\mathrm{cm}}^{\mathrm{\ensuremath{-}}2}$ at T=1.3 K. \textcopyright{} 1996 The American Physical Society.

In this paper first results on electron beam lithography with a microcolumn are presented. Our miniaturized e-beam writer is designed to explore the energy range below 1 keV. This range is attractive because the mean free path of the electrons has a minimum at approximately 100 eV. It is expected that resists are extremely sensitive at these energies and that proximity effects are highly reduced. Both effects could help to accelerate the lithography process or to allow the exploration of new processes. Test exposures were made on spin-coated, 50-nm-thick films of PMMA, hydrogen-passivated silicon and self-assembled monolayers on gold-coated silicon. The patterns were analyzed by means of optical, atomic force and scanning electron microscopy where appropriate, as well as with a profilometer. As expected, the depth of the profiles in PMMA were very shallow. Typical values lay between 2 and 7 nm for energies between 100 and 200 eV.

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

A sub-micron trenching technique has been developed to fabricate Aharonov-Bohm ring structures in a high mobility Si/Si"0"."7Ge"0"."3 modulation doped heterostructure. Scanning electron-beam lithography is used to expose the area defining the ring contour, and reactive-ion etching follows to recess this area, thus forcing electrons to flow inside the ring. Conductance in the Si/SiGe rings exhibits oscillations in magnetoresistance, which is the first observation of this effect in Si-based materials. The amplitude of the oscillations is comparable to that of similar devices on similar mobility GaAs/GaAlAs heterostructures.

A new combination of long millisecond (1–2.5 ms) flash anneal at high peak temperature(1200–1300°C) and a new absorber with low deposition temperature (

Conduclng polyaniline is found to be suitable for several lithographic applications. With the use of onium salts, polyaniline is made radiation sensitive and shown to be a high resolution conducting photo and electron-beam resist. Conducting lines of 0.25 μm have been patterned with e-beam irradiation. Thin films of conducting polyaniline are found to be effective discharge layers for e-beam lithography. Insulating resist systems charge during e-beam exposure, which results in pattern displacements. When polyaniline is used as a conducting layer below the imaging resist, no pattern displacements are observed

A novel dual-gate MODFET structure with two gates (

The observation of negative differential conductance (NDC) in simple nanostructure geometries fabricated on high-mobility Si/SiGe strained-layer heterostructures is reported. The NDC is observed in the drain characteristic of etch-defined “point contacts” with lithographic width and length of 0.22, and 0.12 μm, respectively. Current peak-to-valley ratios as large as 2.0 are observed at T=1.3 K. The NDC is also observed in “wire” geometries as long as 19 μm, and can persist to temperatures as high as 83 K, with a minimum in the differential conductance observable at 103 K. The NDC in long wires is accompanied by the formation of a high-field domain at the drain end of the wire. The effect is only observed in laterally constricted geometries, but is not a result of quantum confinement or impurity-related trapping. We suggest that the NDC and the attendant domain formation are caused by phonon emission by hot electrons within the constricted geometry.

The operation of a negative differential conductance (NDC) transistor fabricated on a high-mobility Si/Si/sub 1-x/Ge/sub x/ heterostructure wafer is described. The drain characteristic of this device shows a large NDC with current peak-to-valley ratios as high as 600 (100) at T=0.4 K (T=1.3 K). The NDC can be modulated over a wide range of current levels by either of two separately-contacted gate electrodes. The device shows bistable switching behaviour in both current- and voltage-controlled circuit configurations. The novel operating principle of this transistor is described, along with its potential for future logic and memory applications.

A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-/spl mu/A's), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology.

The operation of a laterally patterned negative differential conductance (NDC) device based on hot-electron effects in strained Si quantum wells is demonstrated. The device consists of a small, etch-defined dot region connected to narrow leads on either side via point-contact tunnel barriers. The entire device is fabricated on a high-mobility Si/Si1−xGex heterostructure wafer using electron-beam lithography and low-damage reactive-ion etching. At T=0.4 K (T=1.3 K), the drain characteristic of this device shows a pronounced NDC region with a peak-to-valley ratio (PVR) greater than 600 (100). The PVR is reduced with increasing temperature, with remnants of the NDC observable to 30 K. The NDC is attributed to phonon emission by hot electrons injected into the dot region.

The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.

In this work, the channel design space for scaled strained Ge (s-Ge) buried channel (BC) MOSFETs is examined by simulations and experiments. The identified Ge channel layer structure is scalable to sub-30nm devices. Furthermore, strained Ge buried-channel MOSFETs with an ultra thin (1.5nm) Si cap are demonstrated with a 6/spl times/ hole mobility enhancement over the Si universal hole mobility. Compared with surface channel Ge MOSFETs. buried strained Ge channel structures can be integrated with fewer processing challenges to achieve a significantly enhanced hole mobility and an improved electron mobility.

The diffusion of implanted boron in strained Si/Si/sub 1-x/Ge/sub x/ is investigated. A continuum segregation model (CSM) is presented to describe the phenomenon of B pile-up into the germanium profile. An analytic formula is obtained for Ge pre-amorphization and a modified pre-amorphization model is used in TSUPREM4 in order to accurately model our measurement data. Our simulations of boron diffusion are in reasonable agreement with our SIMS data. Comparison of the CSM with the model of immobile boron-germanium clusters is also discussed.

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Very high performance sub-0.1 /spl mu/m channel nMOSFET's are fabricated with 35 /spl Aring/ gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V/sub dd/=1.5 V is recorded from a 0.08 /spl mu/m channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f/sub T/) of a 0.08 /spl mu/m channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 /spl mu/m channel device. Good subthreshold characteristics are achieved for 0.09 /spl mu/m channel devices with a source-drain halo process. >

In this work, we describe the operation of a novel, three-terminal, laterally patterned NDC device fabricated in a high-mobility strained Si quantum well. We call this device a hot-electron phonon-emission field-effect transistor (HEPEFET), because the NDC is caused by phonon emission of energetic electrons injected into a constricted geometry. We describe the characteristics of the HEPEFET, and point out some of the features that make it potentially attractive for future high-density circuit applications.

Tantalum nitride (TaNx) amorphous thin films with varying nitrogen content were grown on SiO2/Si using ionized physical vapor deposition. The composition of the films was examined by Rutherford back scattering spectrometry. The carrier density and the resistivity of TaNx films were measured by Hall effect and Van Der Pauw's method. TaNx thin films showed increased electrical resistivity and reduced carrier density as the amount of nitrogen was increased. By controlling the nitrogen content, the carrier density can be tuned within a large range of 1019–1022 cm−3 for 3 and 15 nm thick TaNx films. The metallicity of the films was confirmed using ultraviolet photoemission spectroscopy. For 3 nm thick TaNx films, carrier densities of ∼1021 cm−3 were obtained with the N2 flow rate in the range of 10–15 sccm. Such films have potential application in a quantum metal field effect transistor.

A MODFET with two 30-nm-long gates (separated by 40 nm) has been fabricated using ultrahigh-resolution electron-beam lithography. The proximity of the two gate fingers along with the ability to independently bias them results in the following features: (a) tunability of the threshold voltage, (b) enhancement of the transconductance, especially at low current levels, (c) reduction in short-channel effects, and (d) high-voltage gain and cutoff frequency. >

X-ray microdiffraction was applied to study the thermal and electromigration strains in 10 μm-wide Al conductor lines with 10 μm spatial resolution. X-rays were collimated either by pinholes or by tapered glass capillaries to form x-ray microbeams. Measurements were made in a symmetric-reflection geometry so that the strains normal to the sample surface could be examined at different positions along the conductor lines. Results of thermal strain measurements show that the SiO2 passivation plays an important role in limiting relaxation of in-plane compressive thermal stresses in the Al lines, but that the passivation is not effective in confining the overall thermal expansion of the Al line along the film normal. Electromigration strain measurements show that a linear stress gradient developed within the first hour of electromigration. The magnitude of the stress gradient changed little until fast stress relaxations occurred near the anode end of the line. Possible mechanisms are discussed in light of these observations.

We have used transmission electron microscopy to examine in detail how microstructural changes take place in aluminum/copper lines adjacent to tungsten contacts. A structure that could be powered in a probe station was deposited directly on an electron transparent silicon nitride window to allow direct observation of the structure of the line after different intervals of electromigration testing. Observations made on aluminum-4% copper lines show that significant changes in the grain structure surrounding precipitates occur during testing even under conditions where no normal grain growth is observed in the lines. Elecromigration testing at 260°C resulted in grain coarsening and the formation of new diffusion blocking structures in the lines. By making measurements of the volume of individual precipitates as a function of time, the flux of copper through specific segments of the microstructure of the line could be measured. The results indicate that the presence of a single grain boundary can increase the electromigration flux of copper along the line by an order of magnitude. In line segments where a bamboo grain occurred copper diffusion appears to be controlled by diffusion along the Al/oxide interface at the surface of the lines. It is also shown that, in polycrystalline lines, the rate of copper depletion frorr the cathode is largely determined by the rate of dissolution of the precipitates. In mixed structure lines the migration of copper can become quite complex as changes in diffusion paths can occur as precipitates dissolve or grow.

We describe how x-ray microbeam diffraction is being used to measure strain with micronscale spatial resolution. Micron-scale x-ray beams can be obtained using tapered glass capillaries. With the high brightness and broad energy spectrum of synchrotron radiation and the energy dispersive capabilities of commercially available, liquid nitrogen cooled x-ray detectors, spatially resolved strains in a sample can be determined along different directions without having to rotate the sample, in contrast with more conventional methods using monochromatic x-ray diffraction. This is a major advantage in achieving micron-scale spatial resolution. Strain sensitivities on the order of 2×10−4 have been achieved in such measurements. White beam x-ray microdiffraction has been applied for the first time in real-time studies of thermal and electromigration related strain distributions in passivated Al-on-Si conductor lines. Results of measurements on a single 10μm-wide line are described.

Onium salts and amine triflate salts decompose upon exposure to radiation or thermal treatment respectively to generate protonic acids. These salts can be blended with polyaniline and upon decomposition the resulting acids act as insitu dopants for the polymer. These novel doping techniques eliminate the need for external dopant solutions and thereby simplify the processing of conducting polyaniline.

A new experimental complimentary metal–oxide semiconductor (CMOS) technology is presented, fabricated with Schottky source and drain and a T-shaped gate. The process results in a significant reduction in the number of steps required to fabricate CMOS, and no longer relies on implantation of the source and drain. The gate resistance and the source/drain contact resistance are very low compared to conventional designs. Performance of 0.25 and 0.15 μm channel length devices has been measured and the technology is readily scalable to sub-0.1 μm dimensions.

Lithography with an array of miniaturized scanning electron‐beam columns presents one of the most promising high‐throughput possibilities for fabrication of devices with feature sizes less than 100 nm. With scanning electron beams no mask is required and the necessary resolution and alignment of overlay structures are realizable. With arrays of microcolumns, the lithography throughput of a single column can be multiplied. The approach can also be used for a number of lithography related applications such as metrology, inspection, testing, etc. We review the status of the microcolumn program and discuss opportunities and challenges of this approach to high‐throughput nanolithography and related applications. Special emphasis is given to lithography in the 100 nm regime.

A miniaturized 1 kV electron beam column with a 20×20 mm square footprint for application in arrayed lithography was developed. The actual beam forming optics measured from the electron emitter to the last electrode in the beam focusing Einzel lens is only 3.5 mm in length. The electron source is a miniaturized, high brightness (120 μA/sr), low heating power (

ZEP‐520 and KRS resist systems have been evaluated as candidates for use in low voltage electron beam lithography. ZEP‐520 is a conventional chain scission resist which has a positive tone for over two orders of magnitude in exposure dose. KRS is a chemically amplified resist which can be easily tone reversed with a sensitivity ∼8 μC/cm2 at 1 keV. Both resist systems are shown to have sensitivities ∼1 μC/cm2 for positive tone area exposures to 1 keV electrons. A decrease in contrast in 50 nm thick resist layers is seen when exposure voltage is lowered from 2 to 1 keV, indicating nonuniform energy deposition over the resist thickness. High resolution single pass lines have been transferred into both Si and SiO2 substrates at both low and high voltages in each resist system without using multilayer resist masks. The ZEP‐520 and KRS resists are shown to have resolutions of 50 and 60 nm, respectively, at 1 kV, within a factor of 2 of their high voltage resolutions under identical development conditions. A cusp shaped etch profile in Si allows high aspect ratio 20 nm wide trenches to be fabricated using these resists on bulk Si. Low voltage exposures have been used to pattern gratings with periods as small as 75 and 100 nm in ZEP‐520 and KRS, respectively. Low voltage exposures on SiO2 show no indications of pattern distortion due to charging or proximity effects.

In this article we present the preliminary results regarding the performance characterization of a metal–semiconductor–metal low‐energy (≤1 keV) electron detector fabricated by electron‐beam lithography on metal–oxide chemical vapor deposition grown GaAs. These devices display very low dark currents, ≤3 nA at 1 V and 300 nA at 9 V. Also, under electron‐beam irradiation very high gain values (≳1000) have been noted, which could be evidence of avalanche multiplicative effects. In addition, the input/output response of the device shows a high degree of linearity even in the high gain regime. The signal‐to‐noise response of the devices is well within the acceptable range of operation for low current sensitivity.

This article describes a new negative‐tone photoresist, SU‐8, for ultrathick layer applications. An aspect ratio of 10:1 has been achieved using near‐ultraviolet lithography in a 200‐μm‐thick layer. The use of this resist for building tall micromechanical structures by deep silicon reactive‐ion etching and electroplating is demonstrated. Using SU‐8 stencils, etched depths of ≳200 μm in Si and electroplated 130‐μm‐thick Au structures with near‐vertical sidewalls have been achieved.

We have built and tested a 1 keV electron‐beam microcolumn that focuses 1 nA of beam current into a 10 nm full width half‐maximum beam diameter at a working distance of 1 mm. The electron source is a miniaturized Zr/O/W Schottky field emitter with 150 μA/sr angular emission current density operating at about 1800 K at a distance of only 100 μm from a silicon membrane extractor electrode. The actual microcolumn is 3.5 mm long assembled mainly from silicon membrane electrodes. Improved einzel lens design and fabrication allowed the operation of this beam focusing element in the accelerating mode. Spherical and chromatic aberrations were reduced by factors of about 2–3, respectively, as compared to the retarding lens mode. Excellent beam current stability with less than 1% variation over several hours has been observed.

Electron-beam-induced deposition of materials has been known for almost 40 years from contamination writing. It has developed into “additive lithography” with nanometer resolution employed in scanning electron microscopes, in dedicated lithography systems, in reducing image projection systems, and in scanning tunneling microscopes. The technique allows deposition of nanometer- to micrometer-size structures with nanometer precision in three dimensions without supplementary process steps such as lift-off or etching procedures. Depending on the deposition conditions, novel compound materials are created from organometallic precursors which form resistors with a resistivity ranging from 103Ω· cm to 2×10-3Ω· cm and sustain current densities higher than 5×105A/cm2without damage. High-resolution transmission electron microscope analysis of the deposits reveals a new class of nanocrystalline compound materials. Crystals of metals or metalcarbides and oxides are immersed in a matrix of carbonaceous material. The deposition process is compatible with conventional VLSI technology. Tips for atomic force and scanning tunneling microscopy can be produced with radii of curvature as small as 5 nm. Field electron emission is obtained from deposited tips starting at an extraction voltage of 8 V and yielding 180 µ A of current at 20 V. Three-dimensional conducting structures can be produced as sensors.

A new fabrication process for sub‐0.1 μm silicon n‐metal–oxide–semiconductor field effect transistors with composite metal/polysilicon gates is described. Gate resistance is reduced below that of plain polysilicon or silicided gates, so that higher speed performance is obtained from shorter gate length devices. The process has resulted in 0.08 μm channel length ring oscillators with record per stage delays of 10.5 ps at 85 K and 13 ps at room temperature, and unity‐current‐gain cutoff frequencies of 119 GHz at 85 K and 93 GHz at 300 K. Record high transconductances of 1040 mS/mm at 85 K and 740 mS/mm at 300 K have been measured in 0.05 μm channel length devices.

Coupled GaAs/GaAlAs rings have been fabricated using electron‐beam lithography and wet chemical etching. We report the first observation of conductance steps associated with e2/h in etched structures, and clear Aharonov–Bohm oscillations in multiple rings connected in parallel. The amplitude of the oscillations is found to be dependent on the number of rings indicating the possibility of phase coupling between electrons traversing different rings.

Electrically conducting polyaniline is found to be suitable for several lithographic applications. Because the polyaniline is not significantly soluble in the conducting state, the material has generally been processed by first applying the soluble, nonconducting version of the material, and in a second step externally doping the polymer film with aqueous acids. We have eliminated the need for this type of external doping by developing methods of inducing the doping in a dry fashion in situ in the polymer. This is accomplished by incorporating onium salts or amine triflate salts in the polyaniline which decompose upon radiation or thermal treatment, respectively, to generate the active dopant species, i.e., protonic acids. The use of these in situ dopants simplifies the processing of the conducting polyaniline and makes the material more convenient for lithographic applications. With the use of onium salts, the polyaniline is made into a high resolution negative conducting resist. 0.25 μm conducting lines...

This paper demonstrates a novel method for fabricating two‐dimensional lateral surface superlattices. The technique involves etching a grid into a GaAs/GaAlAs modulation‐doped heterostructure using a mask consisting of an array of 50‐nm diam Ni/Au dots with a 100–150 nm period. Bias applied to a Schottky gate deposited over the structured surface varies the coupling strength between dots. The devices can be tuned to operate in the superlattice (weak and strong coupling) or the quantum dot (no coupling) regimes. Low‐temperature characterization of the superlattices fabricated specifically for transport and capacitance measurements reveal novel magnetic field effects.