Search

Nearest neighbor (NN) search computations are at the core of many applications such as few-shot learning, classification, and hyperdimensional computing. As such, efficient hardware support for NN search is highly desired. In-memory computing using emerging devices offers attractive solutions for NN search. Solutions based on ternary content-addressable memories (TCAMs) offer high energy and latency improvements for NN search at the expense of accuracy. In this work, we propose a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. We evaluate the efficacy of FeFET MCAMs in the context of few-shot learning applications with different datasets. As an example, we achieve a 78.54% accuracy for a 5-way, 5-shot classification task for the mini-ImageNet dataset (only 1.5% lower than software-based implementations) when using a 3-bit MCAM for NN search. We consider the effects of FeFET threshold voltage variations on the application accuracy and analyze the area and search energy requirements of FeFET MCAMs for accurate operations. Our results indicate that MCAMs require 2x lower area and search energy than TCAMs to achieve the same accuracy. Furthermore, we experimentally demonstrate a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate the design concept.

The ferroelectric properties of hafnium oxide films are strongly influenced by the crystallization process due to the interaction of thermodynamics, kinetics, and mechanical stress. In this work, the influence of annealing temperature on the crystallographic properties and microstructure of Si-doped hafnium oxide thin films as well as their ferroelectric properties are investigated by X-ray diffraction, transmission Kikuchi diffraction, and electrical characterization. The findings reveal the emergence of a [100] and [110] out-of-plane texture for metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) capacitor structures with increasing annealing temperature, respectively. In combination with observed stress relaxation at higher temperatures and the evolution of the wake-up behavior, insights into the crystallization process and the influence of the interplay of microstructure and stress on the ferroelectric properties of hafnium oxide thin films are given.

In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation. Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising. Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching. In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications. Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance. Here, we demonstrate good device properties even for highly scaled devices ( $100\,\,nm \times 100$ nm).

This article presents a systematic empirical modeling approach in fully depleted silicon-on-insulator (FDSOI) CMOS for large-signal simulation in power amplifier applications. The model is constructed from multibias S-parameter measurements up to 67 GHz. The frequency dispersions in transconductance and output conductance are addressed by two independent radio frequency (RF) current sources. Angelov’s current formula is modified to adapt to the FDSOI transistors. Load-pull measurements are performed for the large-signal verification in a non-50- $\Omega $ environment. The model accurately predicts the nonlinear characteristics of the device under test and the harmonic components. The time-domain waveforms also show excellent agreement to the simulation.

We report on the temperature-dependent operation of fluorite-structure-based ferroelectric FET (FeFET) emerging memory. A temperature range (− 40 °C to 40 °C) is used to explore the FeFET characteristic relation to operating temperature. The memory window (MW) shows a modulated response that features a reciprocal MW dependence on temperature, such that a maximum of the MW is realized at − 40 °C. The gradual MW closure upon temperature increase is attributed to the ferroelectric (FE) polarization change with temperature. On the contrary, the FE coercive field shows a minor variation with operating temperature. The FeFET state readout shows a trend of ${V}_{\text {th}}$ shift with temperature such that the decrease in remnant polarization, as well as the substrate effects, causes a maximized shift for erase (ER) state compared to the program (PG) one. The benchmark of Si-doped hafnium oxide (HSO) and hafnium zirconium oxide (HZO) shows comparable trends for dependence on temperature. The temperature cycling by repetitive sweep from − 40 °C to 40 °C shows reproducible MW and PG/ER readout trends with a predictable FeFET response over temperature. This suggests system design techniques for mitigating the variation effects. The FeFET characteristics are explored with insight on physical mechanisms and FE response to temperature variation.

We report on the high-temperature operation and reliability of the Si-doped hafnium oxide (HSO) ferroelectric FET (FeFET) emerging memory. In this study, we explore the role of high-temperature operation of the ferroelectric (FE) material on the FeFET in the temperature range of 40–120 °C. The inverse memory window (MW) dependence on temperature leads to a very small MW size ( $\sim 300$ mV) at 120 °C. The recovery of MW size at room temperature (RT) indicates a potential pyroelectric effect as a cause for MW closure upon high-temperature operation. The FeFET state readout shows pronounced effects to erase (ER) threshold voltage ( ${V}_{\text {th}}$ ) shift, due to the decrease in remnant polarization and improved substrate ${V}_{\text {th}}$ shift as the temperature increases. The endurance reliability measured for temperature range ( $- 40\,\,^{\circ }\text{C}$ to 40 °C) with $10^{{5}}$ cycles shows a maximized initial MW at low temperatures, whereas higher postcycling interface trap generation occurs as the temperature increases. The FeFET 10 h retention tests at 0 °C and 40 °C were extrapolated to ten years and indicated stable properties independent of temperature. The depolarization field ( ${E}_{\text {d}}$ ) dependence on the FeFET stack parameters is studied based on an analytical formula. The ${E}_{\text {d}}$ decreases with increased permittivity of the FE, interface layer (IL), and increased FE film thickness. Substrate doping and temperature seem to have a small impact on ${E}_{\text {d}}$ , whereas the FE–IL area ratio tuning below unity lowers the ${E}_{\text {d}}$ . The role of pyroelectric effect on the FeFET memory and operating temperature-induced endurance and retention reliability concerns are discussed.

Ferroelectricity in crystalline hafnium oxide thin films is strongly investigated for the application in non-volatile memories, sensors and other applications. Especially for back-end-of-line (BEoL) integration the decrease of crystallization temperature is of major importance. However, an alternative method for inducing ferroelectricity in amorphous or semi-crystalline hafnium zirconium oxide films is presented here, using the newly discovered effect of electric field-induced crystallization in hafnium oxide films. When applying this method, an outstanding remanent polarization value of 2P$$_{\mathrm{R}}$$ R = 47 $$\upmu$$ μ C/cm$$^{2}$$ 2 is achieved for a 5 nm thin film. Besides the influence of Zr content on the film crystallinity, the reliability of films crystallized with this effect is explored, highlighting the controlled crystallization, excellent endurance and long-term retention.

This paper investigates reconfigurable physical unclonable function (PUF) design by exploiting the polarization switching variation and stochasticity in ferroelectric field-effect-transistors (FeFETs). The proposed PUFs include 1-transistor/cell (1T/C) and 2T/C designs. The denser 1T/C PUF splits random ‘0’ and ‘1’ states using a tactically pre-defined reference. The 2T/C PUF needs no dedicated references and obtains unbiased random states by differentiating two FeFETs under a proposed sensing error cancellation scheme. Experimental measurements have shown the uniform randomness, uniqueness, repeatability and reconfigurability of the response. Further simulations using an experimentally calibrated multi-domain FeFET model show high energy efficiency and robustness on design parameters.

This article presents a fully differential power-tuning heterodyne on-chip sensing readout system at 240 GHz. The chip enables the measurement of not only the transmission parameter but also the reflection parameter to sense the permittivity of different materials by using four heterodyne mixer-based receiving channels connected to a dielectric sensing element. To facilitate the operation and characterization, three frequency multiplier chains are included to generate the required two identical radio frequency (RF) and one local oscillator (LO) subterahertz signals. RF frequency multiplier chain is configured to enable a tunable power level of the RF signal by using a variable attenuator. A chip prototype using 130-nm silicon-germanium (SiGe) BiCMOS is implemented with a size of 11 mm 2 and dc power consumption of 2.7 W. The measured 10-dB bandwidth of 20.8% is achieved in a frequency range from 207 to 257 GHz with 14-dB measured power-tuning range. The transmission and reflection parameters' measurements for copper and gummi show a differentiated value in terms of magnitude and phase, which demonstrates the sensing function of the proposed readout system.

We employ a modified atomic layer deposition process utilizing in-situ mixing of precursors to obtain doped hafnium oxide thin films with improved ferroelectric properties. The method is demonstrat...

A microwave characterization at UHF band of a ferroelectric hafnium zirconium oxide metal-ferroelectric-metal (MFM) capacitors for varactor applications has been performed. By using an impedance reflectivity method, a complex dielectric permittivity was obtained at frequencies up to 500 MHz. Ferroelectric Hf0.5Zr0.5O2 of 10 nm thickness has demonstrated a stable permittivity switching in the whole frequency range. A constant increase of the calculated dielectric loss is observed, which is shown to be an effect of electric field distribution on highly resistive titanium nitride (TiN) thin film electrodes. The C-V characteristics of a “butterfly” shape was also extracted, where the varactors exhibited a reduction of capacitance tunability from 18.6% at 10 MHz to 15.4% at 500 MHz.

In this work, the tuning properties of hafnium zirconium oxide (HZO) metal-ferroelectric-metal (MFM) thin film varactors are investigated. It is shown that varactors with 1:1 Hf:Zr stoichiometry and 10 nm thickness, crystallized with rapid thermal annealing (RTA) at 400°C for 60 s, show a maximum capacitance tunability of 32% at room temperature without electric field pre-cycling. The cycling and accompanying wake-up effect lead to a reduction of tunability. Furthermore, the influence of the temperature on the ferroelectric properties and tunability is explored. Upon increase of measurement temperature to 200°C, the maximum tunability decreases to 24%. An elevated temperature leads to an increase in aniferroelectric-like (AFE) behavior, which is consistent with recent studies of ferroelastic nature of AFE switching.

The back-end-of-line (BEoL) integration of ferroelectric hafnium zirconium oxide (HZO) has many advantages for applications like non-volatile memories and sensors. Using transmission Kikuchi diffraction (TKD), the influence of process parameters like annealing conditions and Zr content on the microstructure are investigated here. TKD analysis allows to map the local crystallographic phase and orientations as well as grain size and shape. The results of this study present thereby no significant dependence of the grain size, shape and phase on the annealing time. However, Zr content affects the microstructure strongly, and decrease in grain size and monoclinic phase as well as changes in the crystallographic texture are observed for higher Zr content. How this affects the polarization behavior is investigated as well.

Ferroelectric and antiferroelectric Hf/Zr-based oxide films have recently gained interest for memory and AI applications due to their promise of low power and CMOS compatibility. As Hf/Zr-based oxides are not ‘new’ materials, this paper will start with an overview of past learning on this material system. Recent results on fundamental understanding of the mechanism of ferroelectric and antiferroelectric switching will be presented. Challenges in implementation of this material system in high volume manufacturing will be discussed.

One of the critical issues in spintronics-based technologies is to increase the data storage density. Current strategy is based on shrinking the devices size down to tens of nanometers, or several nanometers, which is reaching its limit. A new proposal is to use multi-level cells (MLCs) to store more than two bits in each cell. In this work, the multi-level switching is realized in CoFeB/MgO/CoFeB based nano-scale single perpendicular magnetic tunnel junctions (p-MTJs) with three or four stable resistance states. A large range of writing currents for each state is obtained, accompanying with a good repeatability of set-reset operations between different states. The developed multi-domain model perfectly matches the experimental results, reflecting the magnetic behaviors during multi-level switching. Furthermore, current-driven domain wall (DW) motion is revealed in the circular p-MTJs, where the DW position can be reversibly manipulated by applied current. To design high-performance multi-level p-MTJs, the parameter diagrams are calculated, suggesting various feasible strategies to improve the multi-level switching through materials optimization and devices geometry. In summary, the demonstration of multi-level switching in single p-MTJ shows the high potential of realizing the new generation of p-MTJ-based multi-level spintronic devices, such as multi-level memories and spin-neuron devices.

Applying transmission Kikuchi diffraction (TKD) allows us to fundamentally investigate the Si-doped-hafnium-oxide (HSO) microstructure that results from the interface layer present in ferroelectric field-effect transistors. In addition to the predominant orthorhombic phase, dendritic HSO grains larger than 100 nm govern the microstructure composition. Furthermore, the observed strong out-of-plane texture aligned along the [110] and [011] axis clearly differs from features found in hafnium oxide thin films grown on TiN layers. Our TKD analysis shows that the texture intensity strongly varies for samples annealed at different temperatures. Additionally, intra-granular misorientation and chemical composition analyses of the layers provide insight into the crystallization process of these ferroelectric thin films.

This article presents a reflectometer-based on-chip dielectric sensor with integrated transducers at 240 GHz. The chip simplifies the measurement of a vector network analyzer (VNA) to sense the incident and reflected waves by using two heterodyne mixer-based receivers with a dielectric sensing element. Radio frequency (RF) and local oscillator (LO) submillimeter waves are generated by two frequency multiplier chains, respectively. Two back-to-back identical differential side-coupled directive couplers are proposed to separate the incident and reflected signals and couple them to mixers. Both transmission line and coplanar stripline transducers are proposed and integrated with reflectometer to investigate the sensitivity of dielectric sensors. The latter leads to a larger power variation of the reflectometer by providing more sufficient operating bands for the magnitude and phase slope of $S_{11}$ . The readout of the transducers upon exposure to liquids is performed by the measurement of their reflected signals using two external excitation sources. The experimental dielectric sensing is demonstrated by using binary methanol–ethanol mixture placed on the proposed on-chip dielectric sensor in the assembled printed circuit board. It enables a maximum 8 dB of the power difference between the incident and reflected channels on the measurement of liquid solvents. Both chips occupy an area of 4.03 mm2 and consume 560 mW. Along with a wide operational frequency range from 200 to 240 GHz, this simplified one-port-VNA-based on-chip device makes it feasible for the use of handle product and suitable for the submillimeter-wave dielectric spectroscopy applications.

A novel hybrid antiferroelectric (AFE)-based charge trap (CT) memory is reported focusing on an amplified tunnel oxide field ( ${E} _{\text {TO}}$ ) via the dynamic of an AFE hysteresis dipole switching. The role of dynamic permittivity increase and the saturated polarization at the instant of the write operation are explored for enhanced ${E} _{\text {TO}}$ . The hybrid CT concept is studied by benchmarking the controlled properties of the HfO2 CT layer via the Si elemental doping in order to stabilize the linear dielectric (DE), ferroelectric (FE), or AFE response. The Si-doped HfO2 (HSO) with AFE stabilized phase shows the largest memory window (4.5 V) compared to the DE- or FE-based CT layers. The dynamic AFE dipole switching enables a maximized ${E} _{\text {TO}}$ at the instant of switching such that a high-speed and low-power CT memory is realized. The role of the tailored hysteresis shape on the ${E} _{\text {TO}}$ magnitude is studied for different Si contents and benchmarked to the Zr-doped hafnium oxide (HZO). The AFE CT multilevel coding as 1–3 bit/cell, the role of the pass voltage disturb, and a mini-NAND array operation are demonstrated. The global variability and area scalability of the HSO CT devices are studied to indicate the effect of Si content distribution and the area dependence of the AFE film variability. AFE CT devices are characterized for a switching speed ( $ ), ten-year data retention, and $10^{{5}}$ endurance. Moreover, the improved CT characteristics by the AFE dipole switching are explored for enhanced long-term potentiation and depression of a synaptic device.

Abstract Reliability is a central aspect of hafnium oxide-based ferroelectric field effect transistors (FeFETs), which are promising candidates for embedded non-volatile memories. Besides the device performance, understanding the evolution of the ferroelectric behaviour of hafnium oxide over its lifetime in FeFETs is of major importance for further improvements. Here, we present the impact of the interface layer in FeFETs on the cycling behaviour and retention of ferroelectric silicon-doped hafnium oxide. Thicker interfaces are demonstrated to reduce the presence of antiferroelectric-like wake-up effects and to improve endurance. However, they show a strong destabilisation of one polarisation state in terms of retention. In addition, measurements of the Preisach density revealed additional insight in the wake-up effect of these metal-ferroelectric-insulator-semiconductor (MFIS) capacitors. Graphic abstract

Abstract Non-volatile memories based on ferroelectric hafnium oxide, especially the ferroelectric field-effect transistor (FeFET), have outstanding properties, e.g. for the application in neuromorphic circuits. However, material development has focused so far mainly on metal–ferroelectric–metal (MFM) capacitors, while FeFETs are based on metal–ferroelectric–insulator–semiconductor (MFIS) capacitors. Here, the influence of the interface properties, annealing temperature and Si-doping content are investigated. Antiferroelectric-like behavior is strongly suppressed with a thicker interface layer and high annealing temperature. In addition, high-k interface dielectrics allow for thicker interface layers without retention penalty. Moreover, the process window for ferroelectric behavior is much larger in MFIS capacitors compared to MFM-based films. This does not only highlight the substrate dependence of ferroelectric hafnium oxide films, but also gives evidence that the phase diagram of ferroelectric hafnium oxide is defined by the mechanical stress. Graphic Abstract

Advanced non-volatile memory concepts such as the 1T1C ferroelectric (FE) random-access memory (FeRAM) and the 1T1C FE field-effect transistor (FeFET) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) of a microchip to the drain and gate contacts of a standard logic device, respectively. With the vertical distributed select devices in the front-end of line (FEoL) and the storage elements in the BEoL, both concepts increase the effective memory density of a microchip without introducing major changes in the FEoL fabrication technology. However, for advanced neuromorphic computing architectures, the 1T1C FeFET is the device of choice, since it provides non-destructive readout. The most promising material for the integration of FE non-volatile memory functionalities into the BEoL is Zr doped HfO 2 (HZO). It crystallizes at low temperatures in the orthorhombic phase (the one with FE properties) and with a polycrystalline structure. The latter is important to enable analogue like switching in synaptic devices. Herein, the above-mentioned memory concepts are introduced and key steps to optimize the HZO films for the BEoL integration and for the neuromorphic computing use case are described.

Nonvolatile memories especially the ferroelectric (FE)-based ones such as ferroelectric tunnel junctions (FTJs) and ferroelectric field-effect transistors (FeFETs) have recently attracted a lot of attention. FTJs have been intensively researched for the last decade and found to be very promising memory devices due to their significant nondestructive readout advantage as compared to conventional ferroelectric random access memory (FRAM). However, more research is needed on FTJ devices to obtain reliable endurance and retention behavior. In this article, we demonstrate the characteristics and performance of zirconium-doped hafnium oxide-based FTJ devices in terms of FE switching and reliability. This is investigated for FTJ stack structure tuning as well as for the FE switching process in FTJ devices. The FTJ memory switching characteristics, the effects of polarization switching on the write conditions, and the impact of pulse width and pulse amplitude on switching are investigated. The impact of FE layer thickness and interface layer type/thickness are reported to obtain a maximum FTJ ION/IOFF ratio (memory window) and reliable performance. The maximum ION/IOFF ratio changes depending on the FE layer (zirconium-doped HfO 2 layer) thickness (12, 8, 6, and 4 nm), the interface layer type (SiO 2 , Al 2 O 3 ), and thickness (1 and 2 nm), indicating the maximum value of ION/IOFF ratio for a 1 nm SiO 2 interface layer stack. Moreover, a stable endurance of 10 4 cycles is reported and extrapolated measurements suggest stable retention for more than ten years. Time-dependent breakdown analysis was performed to investigate the reliability of devices indicating a lifetime of ten years.

Abstract In this article, we investigate the capacitance–voltage (C–V) characteristics of $$\text {Hf}_{x}\text {Zr}_{1-x}\text {O}_{2}$$ Hf x Zr 1 - x O 2 metal-ferroelectric-metal (MFM) thin-film capacitors with various Zr doping for varactor applications. The impact of field cycling during the wake-up process on the capacitance was analyzed. In addition, the effect of antiferroelectric-like (AFE) behavior on tuning was investigated. The transition between ferroelectric (FE) and AFE regime is particularly interesting for varactor application, as a reduced bias is required for tuning. The cycle dependence of the FE and AFE properties at elevated temperatures was also investigated, where it was shown that with an increase of temperature, the tunability is reduced. Temperature measurements also comply with recent studies of ferroelastic nature of AFE behavior. Graphic abstract

In this article, we present the capacitance–voltage ( ${C}$ – ${V}$ ) characteristics of Hf x Zr1− x O2 metal–ferroelectric–metal (MFM) thin-film capacitors with various Zr doping, thicknesses, and annealing temperatures. The influence of doping, electric field cycling, and annealing temperature on tuning characteristics (tunability) was analyzed and an optimized bias region for the maximum tunability was defined. Additional focus was made on an antiferroelectric-like (AFE) behavior, which occurs for > 50% Zr doping. The presence of both the ferroelectric and the AFE phase manifests itself in specific ${C}$ – ${V}$ behavior, where a reduced bias range is required for tuning, however, at the cost of a smaller tunability. The suitability of this behavior for varactor applications is also discussed.

We report on antiferroelectric (AFE) hybrid charge trap (CT) memory with amplified tunnel oxide field via dynamic AFE hysteresis dipole switching. Memory window (4.5V), switching speed (

We demonstrate the feasibility of thermal energy recovery in the back end of line (BEoL) employing CMOS-compatible ferroelectric hafnium oxide. Efficient pyroelectric energy harvesting with a sizable power density of 92 mWcm-3 under typical thermal conditions is achieved. Our energy harvesting approach exceeds the efficiency limit of commonly-used thermoelectric materials, without using a heat switch. The low-voltage operation, scalability, and abundance in CMOS manufacturing make HfO 2 -based ferroelectrics promising candidates for integrated energy harvesting and solid-state refrigeration applications.

Content addressable memory (CAM) is widely used for data-centric computing for its massive parallelism and pattern matching capability. Though the CAM density has been improved by replacing the area-consuming SRAM with compact emerging nonvolatile memories (NVMs), its implementation has been limited to single level cell. To further boost the CAM density for data-intensive workloads, exploiting the multi-level cell NVMs is highly desirable. In this work, we demonstrate: 1) a novel scalable and ultra-compact multi-bit 2FeFET1T CAM design based on two ferroelectric FETs (FeFETs) and one transistor; 2) successful operations of the proposed CAM cell and array in experiment based on 2-bit FeFET memory, and sufficient sensing margin for an 1x32 CAM array through statistical analysis considering the device variation; 3) 22.6x area per bit saving compared with SRAM CAM; 4) 16x search speedup, and 29x reduction in energy delay product over the SRAM CAM approach in accelerating a database query processing application.

Nearest neighbor (NN) search is an essential operation in many applications, such as one/few-shot learning and image classification. As such, fast and low-energy hardware support for accurate NN search is highly desirable. Ternary content-addressable memories (TCAMs) have been proposed to accelerate NN search for few-shot learning tasks by implementing $L_\infty$ and Hamming distance metrics, but they cannot achieve software-comparable accuracies. This paper proposes a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (FeFETs) to perform a single-step, in-memory NN search. Moreover, this approach achieves accuracies comparable to floating-point precision implementations in software for NN classification and one/few-shot learning tasks. As an example, the proposed method achieves a 98.34% accuracy for a 5-way, 5-shot classification task for the Omniglot dataset (only 0.8% lower than software-based implementations) with a 3-bit MCAM. This represents a 13% accuracy improvement over state-of-the-art TCAM-based implementations at iso-energy and iso-delay. The presented distance function is resilient to the effects of FeFET device-to-device variations. Furthermore, this work experimentally demonstrates a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate proof of concept., To be published in DATE'21

Computing-in-memory (CIM) is a promising approach to improve the throughput and the energy efficiency of deep neural network (DNN) processors. So far, resistive nonvolatile memories have been adapted to build crossbar-based accelerators for DNN inference. However, such structures suffer from several drawbacks such as sneak paths, large ADCs/DACs, high write energy, etc. In this paper we present a mixed signal in-memory hardware accelerator for CNNs. We propose an in-memory inference system that uses FeFETs as the main nonvolatile memory cell. We show how the proposed crossbar unit cell can overcome the aforementioned issues while reducing unit cell size and power consumption. The proposed system decomposes multi-bit operands down to single bit operations. We then re-combine them without any loss of precision using accumulators and shifters within the crossbar and across different crossbars. Simulations demonstrate that we can outperform state-of-the-art efficiencies with 3.28 TOPS/W and can pack 1.64 TOPS in an area of 1.52mm2using 22 nm FDSOI technology