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In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-terminal synapse with unique back gate high tuning of the post-synaptic current (PSC). Our device consists of a double-gate 11nm-thin film Fe-JLFET with 10nm Si-doped HfO2 ferroelectric, mimicking the functionality of a tripartite synapse. The gradual ferroelectric switching is exploited to fully reproduce the synaptic plasticity. The back-gate voltage emulates the function of an astrocyte, being used to tune the synaptic weight by more than 400x. Compared to other implementations, the newly proposed tripartite Fe-JLFET synapse device shows simplicity in fabrication, extended programmability, and robustness. We report plasticity until 2000 cycles of operation. Overall, this device concept is promising for CMOS-compatible energy-efficient implementation of future neuromorphic ICs.

As conventional Complementary Metal Oxide Semiconductor (CMOS) reaches extreme limitation to implement the digital circuits with high density and low power dissipation, alternate devices are necess...

This article contains the results of research on the topical problem of highly sensitive express registration of biological objects using field-effect transistors with the surface open for analyte access, which are made based on silicon-on-insulator (SOI) films. The possibilities of dielectrophoretic effects for controlling the concentration of the analyte in the area of sensory elements are considered on the example of the indication of viruses of nuclear polyhedrosis and vaccinia. It is shown that the use of the dielectrophoresis (DEPh) effect makes it possible to solve (1) the key tasks for creating sensor systems: increasing the detecting ability, as well as exrtacting and verifying the signal from the target particles; and (2) the fundamental task: determining the charge state of the analyte in solutions without modifying the sensors’ surface. The problems and prospects of the mass application of nanowire (NW) biosensors, including those with the dielectrophoretic effect, in biotechnology, virology, etc., are discussed.

Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.

The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.

The effect of the source/drain parasitic resistance (RS) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on RS has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.

Gate-induced drain leakage (GIDL) is a serious problem in nanoscale transistors. In this paper, GIDL induced by longitude band-to-band tunneling (L-BTBT) in gate-all-around (GAA) nanowire transistors is investigated by 3D TCAD simulation. Effects of critical process parameters are analyzed, such as sidewall spacer characteristics, nanowire diameter, gate length and doping gradient in the source/drain extension region. The corner spacer and dual κ spacer are found to suppress L-BTBT current without degrading the dynamic performance. An underlap structure, a smaller nanowire diameter, and a gentle doping gradient at the source/drain extension are separately found as best choices, with regard to decreasing L-BTBT current. The underlying physical mechanisms are analyzed, and results indicate that increased L-BTBT width contributes to decreasing L-BTBT current. The results obtained here are reliable for optimizing the device structure, and help in low power circuit design based on nanoscale GAAFET.

This paper discusses the nature of degradation by NBTI effect in MOS junctionless devices when varying the density of interface traps and surface potential. The data obtained in simulations are compared with results from physical devices and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping concentration and the gate bias are varied.

Gate leakage current in lateral GaN wrap-gate nanowire transistors (WG-NWT) was investigated using current density–voltage (Jg–Vg) characteristics at room temperature. We found that the gate leakage current is strongly dependent on the top corner angle of the gate architecture. This leakage current was characterized by considering hopping (Poole–Frenkel emission) and trap-assisted thermionic emission mechanisms. Despite its smaller gate area, the gate leakage current of the lateral GaN WG-NWT without a 2DEG channel was higher than that of the device with a 2DEG channel for all applied gate biases. The reason for this is that the lateral GaN WG-NWT without 2DEG channel has a triangular cross-section with a sharp top corner angle resulting in a strong electric field due to geometrical field enhancement.

In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl2-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

This paper discusses the nature of degradation by NBTI effect in pMOS junctionless devices when varying the temperature. The results were obtained through simulations validated to experimental data. Devices with different dimensions and doping, have been subjected to a temperature range that varies between 270 and 380 K. The simulations were performed for different values of V GT and as a result it is possible to observe that when increasing temperature up to 340 K, the threshold voltage variation due to NBTI is also increased. However, for larger temperatures the NBTI effect seems to stabilize or even reduce.

In this article, a current mirror built with junctionless nanowire transistors (JNTs) is investigated for the first time. The study explores the influence of transistors’ width on the mirroring precision for input and output devices with different dimensions. The work has been performed through numerical simulations validated with experimental data and showed that the variation of devices’ width impacts the output characteristics differently from usually observed in current mirrors formed by inversion mode devices.

This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.

We propose an efficient method for subband calculations of cylindrical nanowire transistors with an arbitrary channel orientation. To perform the subband calculation efficiently, the wavefunctions are expanded using Fourier harmonics. It is confirmed that the use of an approximate isotropic effective mass introduces an error in the subband calculation due to the incorrectly calculated potential energy. A comparison with the results obtained in the Cartesian coordinate system confirms the accuracy of our method. Moreover, the simulation time required to obtain the self-consistent solution is significantly reduced.

This project is to study about characteristics of nanowire transistor. The simulation is done by SILVACO software to find the characteristics of nanowire transistors. Here simulation is more important to understand the device physics and performance limits of the nanowire transistors. By the support of the simulation tools experimental work can be done for nanowire transistor. With the help of simulation, we can know the weakness and strength of nanowire transistors. That will help to reduce the fabrication cost. As we go for the smaller size for the transistor then nanowire transistor comes into the picture. For electronic device Silicon, Germanium and Gallium Arsenide semiconductor materials are generally used. Here production of Silicon simple as compare to Gallium Arsenide but when high speed device is required then we go for Gallium Arsenide material.

This paper presents the proposal of a compact analytical model for the transcapacitances of long-channel triple gate junctionless nanowire transistors. The model is validated using comparisons against 3D TCAD simulations showing very good agreement, with continuous transitions between all regions of operation.

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides are used in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

This paper deals with the behavior of degradation by NBTI effect in MOS junctionless nanowire transistors (JNTs). The analysis has been performed through experimental measurements followed by 3D numerical simulations and has shown that the increase in the number of traps close to the interface leads to the saturation in the NBTI effect, which can be correlated to the operation regime of the devices. When the devices operate in partial depletion due to the threshold voltage reduction, ΔVTH tends to saturate.

In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

GAA p-type poly-Si junctionless nanowire transistor have been fabricated and evaluated. It exhibits excellent subthreshold characteristics close to ideal subthreshold slope (60mV/dec.) as well as high on/off current ratio (~1.2x108) and low off-current (

As a promising alternative to the fundamental device structure, the gate-all-around silicon nanowire transistor (GAA SNWT) has been studied extensively for decades. In this chapter, the device physics, compact modeling, and fabrication process of GAA SNWT are systematically reviewed, as well as its potential applications in terms of different technology diversities. In the first part, the bulk-Si based integration scheme, quasi-ballistic transport characterization, parasitic capacitance, and self-heating modeling of GAA SNWT are presented. Following that, the variability and reliability physics and models of GAA SNWT are studied in-depth. Finally, the application examples in electrostatic discharging, radio frequency/analog circuit, and bio-sensor of GAA SNWT are demonstrated.

© 2018, Brazilian Microelectronics Society. All rights reserved.— This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p-and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones. 13 1 1 7

Introduction: In the past few years junctionless nanowire MOSFETs appeared as one of the candidates for future technological nodes having great potential in digital and analog applications [1,2]. In these devices the fin height (HFIN) and the fin width (WFIN) have a strong influence on the electrostatic coupling that in turn becomes important for the ION/IOFF ratio [3]. Fig.1 shows the cross-section of a junctionless nanowire transistor with its geometrical parameters. This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher ION/IOFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased ION/IOFF ratio. Results: To study the effect of the HFIN on these devices, simulations were made using Sentaurus TCAD from Synopsys. The simulations were calibrated with experimental data for long channel devices as a function of the WFIN and extrapolated for a study with variable HFIN. Fig. 2 shows the experimental and calibrated simulation for several WFIN as a function of the gate voltage with a drain voltage of 50mV [4]. The simulated devices used doping concentration of 4.1018 cm-3, Equivalent Oxide Thickness (EOT) of 1.38nm and work-function of 4.7eV. The box thickness of 150nm, WFIN of 13nm and 18nm, variable HFIN from 10nm to 60nm, channel length (LG) of 100nm, 50nm and 30nm and channel extensions of 30nm. The devices have either doped extensions with 5.1020cm-3 (to reduce the series resistance (RSD) [5]) or extensions with the same doping of the channel (referred as non-doped in this work). For these simulations, the crystallographic orientation of the device was considered and its effects on carrier mobility. Fig. 3 shows the subthreshold slope (SS) as a function of HFIN and one can see that doping the extension increase the SS for all devices, showing the degradation caused by short channel effects [6]. One can see that for long channel (LG=100nm), the SS decreases as HFIN is increased, while the opposite occurs to the short channel devices (LG=30nm), i.e. the HFIN reduction improves the SS. Fig. 4 shows the threshold voltage (VTH) and the DIBL as a function of HFIN. For devices tending to double-gate architecture (HFIN>>WFIN) the VTH is weakly sensitive to HFIN while for smaller HFIN the VTH increases due to the electrostatic coupling of the gate. The same occurs with the DIBL and the improvement on these devices comes from a smaller HFIN. Fig. 5 and Fig. 6 shows the On and Off currents (ION and IOFF, respectively) as a function of HFIN , respectively. The ION has been extracted at a gate voltage overdrive (VGT) of 0.8V and IOFF at VGT=-0.3 V. The ION values were compensated by the effect of the RSD. The use of doped extensions increase the ION, effect that is more pronounced on smaller HFIN and LG, whereas it induces a higher degradation on the IOFF for short LG than the long LG. The devices with non-doped extensions have better IOFF because of lower SS but the ION is much lower. Fig. 7 shows ION/IOFF ratio as a function of the HFIN . We can see that for LG=100nm a higher ION/IOFF ratio comes from the increase in HFIN while for LG=30nm the better ratio comes from the decrease in the HFIN. It indicates that the better ION/IOFF is obtained moving towards double-gate shape for long-channel devices to nanowire shape for short channel ones. Also, the LG=50nm has values close to LG=100nm, but for the doped extensions the device has tendency similar to the LG=30nm. Conclusions: For this work, we analyzed the main parameters of junctionless transistors with different HFIN and the effects for short LG with and without doped extensions shows a greater advantage with smaller HFIN (nanowire), while for long LG the advantage becomes more pronounced by the increase of HFIN as the device tends to become double gate. Acknowledgements: The authors acknowledge Sylvain Barraud, Maud Vinet and Olivier Faynot for providing the samples and the founding agencies CNPq, CAPES and FAPESP [grant #2016/10832-1]. References: [1] C.-W. Lee, et al. IEEE TED, 57,620-625,(2010). [2] R. T. Doria et al. IEEE TED, 58,2511-2519,(2011) [3] R. Yan et al. Microelectronics Reliability, 51,1166-1171,(2011). [4] T. A. Ribeiro, et al. 32nd SBMicro,1-4,(2017). [5] C.-H. Park et al, SSE, 73,7–10,(2012). [6] A. Cerdeira, et al. 30th SBMicro,1-4,(2015). Figure 1

The low-frequency noise behavior of junctionless (JL) gate-all-around (GAA) nanowire (NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It is shown that the predominant 1/f-like noise is governed by carrier number fluctuation (CNF) around threshold voltage operation, while for the p-channel transistors, a pronounced increase in the noise power spectral density is observed at higher gate voltage overdrives. This is due to the impact of the access region to the flicker noise. While the CNF noise is roughly one decade higher for the n-channel than for the p-channel transistors, the opposite holds for the access-related component for both IM and JL GAA NWFETs. It is, finally, observed that the CNF noise is on the average slightly lower in the JL devices compared with their IM counterparts; the origin of this trend will be discussed.

We investigate ultrascaled $\langle 100\rangle $ -, $\langle 110\rangle $ -, and $\langle 111\rangle $ -oriented p-type silicon nanowire transistors using a quantum transport simulator based on the: 1) six-band $\text{k}\cdot \text{p}$ method and 2) sp $^{3}\text{d}^{5}\text{s}^{*}$ tight-binding model. The hole transmission probability from source to drain at low gate voltages shows discrepancies between both models in the $\langle 110\rangle $ and $\langle 111\rangle $ cases. The origin of this phenomenon can be traced back to the nonparabolic band behavior of the imaginary dispersion that is not captured by the six-band $\text{k}\cdot \text{p}$ method. In order to accurately reproduce the full-band (FB) wave function attenuation in the bandgap, the hole energy must be corrected. This approach is validated by comparison with FB calculations. The results suggest that the observed failure of the six-band $\text{k}\cdot \text{p}$ method at ultrashort gate lengths can be avoided, thus extending the applicability of this computationally efficient model.

Sustaining Moore's law requires the design of new materials and the construction of FET. Herein, we investigated theoretically the electronic transport properties of PbSi nanowire Schottky-clamped transistors with a surrounding metal-insulator gate by employing MD simulations and the NEGF method within the extended Hückel frame. The conductance of PbSi nanowire transistors shows ballistic and symmetrical features because of the Schottky contact and the resonance transmission peak, which is gate-controlled. Interestingly, the PbSi(8,17) nanowire FET shows a high ON/OFF ratio and proves to be a typical Schottky contact between atoms as described by the EDD and EDP metrics.

Three-dimensional nanowire transistors with curvilinear tips record intracellular signals from neurons.

This paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime. Such effect can be associated to the change in the flatband voltage to more negative values as well as the threshold voltage with the increase in the precursor density. In the sequence of the work, it was shown that, as the operation temperature rises, there is an increase in the degradation of the threshold voltage due to NBTI, which is more pronounced for larger gate voltages. It was concluded that this effect could be associated to the increase in the recombination rate with the temperature, which enables the occupation of a larger amount of traps.

Flexible In2O3 nanowire transistors gated by microporous SiO2-based solid electrolytes are fabricated on paper substrates at room temperature. Low-voltage (1.0 V) operation of these devices is realized owing to the large electric-double-layer capacitance of (1.73 μF/cm2 at 20 Hz) of the microporous SiO2 solid electrolytes, which were deposited at room temperature. The subthreshold swing, current on/off ratio, and field-effect mobility of the paper-based nanowire transistors are estimated to be 74 mV/decade, 1.7×106, and 218.3 cm2/V·s, respectively. These low-voltage paper-based nanowire transistors show promise for use in portable flexible paper electronics and low-cost portable sensors.

The aim of this work is to propose a compact analytical model for the Low Frequency Noise (LFN) in Junctionless Nanowire Transistors (JNTs). Since JNTs work differently from inversion mode transistors, the noise is also expected to behave differently. To the best of our knowledge, no analytical models have been presented for LFN in these devices. The proposed model is validated through numerical simulations. Experimental results are also used to demonstrate its applicability.

A study of Junctionless Nanowire Transistors (JNTs) is presented in this work, with emphasis on verifying the applicability of the charge pumping method for the analysis of interface traps. To the best of our knowledge, this is the first work to use this method in JNTs. The first step is the analysis of the performance using numerical simulations. It is stated that a transient current is observed in the devices with the charge pumping method application and increases with the trap density. Simulated and experimental data of Junctionless Nanowire Transistors show how this method can be useful and its applicability to verify the JNTs interface quality.

Gate-all-around (GAA) cylindrical channel Si nanowire field effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3-D TCAD simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3nm gate length. The performance of n-type silicon nanowire transistors is benchmarked using predictive TCAD device simulation.

In this work, we have designed and analyzed the performance characteristics of n-type silicon based multi-channel junctionless nanowire transistors (JLNTs) for both single gate and double gate configurations. Numerical simulations using CVT (lambardi) model has been carried out to investigate the effects of different device parameters such as gate insulator dielectric, gate insulator thickness, and separating materials between channels. To illustrate and evaluate the performances, input characteristic curves, transconductance, and Ion/Ioff ratio of the devices have been extracted. It is observed that Ion/Ioff ratio are directly affected by the variation of dielectric and thickness of the gate. Devices having a high-κ dielectric provides steeper characteristics and better Ion/Ioff ratio for both the structures. The value of transconductance is also found to be greater for high-κ dielectric in both configurations with the double gate providing a higher value compared to the single one.