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In this paper, the adaptive fuzzy control of switched stochastic nonlinear systems with set-time prescribed performance based on event-driven mechanism is studied. The creative part of this paper is that based on the set-time performance function, a modified event-triggered strategy that considers asynchronous switching to deteriorate system performance without strict assumptions is presented, which avoids Zeno behavior and saves communication resources. Then, by using backstepping recursive design technique, It $\hat {o}$ ’s differential lemma and mode-dependent average dwell time (MDADT) method, a novel adaptive performance control scheme is proposed, which can ensure that all the variables in the system are semiglobally uniformly ultimately bounded (SGUUB) in probability and the tracking error gets into prescribed boundary no later than an arbitrarily adjusted setting time. Finally, the proposed algorithm is applied to a RLC circuit and its practicability is verified via simulation results. [ABSTRACT FROM AUTHOR]

Hybrid dynamical systems are characterized by intrinsic coupling between continuous dynamics and discrete events. This paper has adopted a differential-algebraic impulsive switched (DAIS) model to capture such dynamic behavior. For such systems, trajectory sensitivity analysis provides a valuable approach for describing perturbations of system trajectories resulting from small variations in initial conditions and/or uncertain parameters. The first-order sensitivities have been fully described for hybrid system and used in a variety of applications. This paper formulates the differential-algebraic equations (DAE) that govern second-order sensitivities over regions where dynamics are smooth, i.e., away from events. It also establishes the jump conditions that describe the step change in second-order sensitivities at discrete (switching and state reset) events. These results together fully characterize second-order sensitivities for general hybrid dynamical system. [ABSTRACT FROM AUTHOR]

This paper studies the composite refined anti-disturbance control problem of a 2-degree-of-freedom robot arm system modeled by a semi-Markov jump system with multiple disturbances, which includes harmonic disturbances with unknown frequency and amplitude as well as energy bounded disturbances. Firstly, the semi-Markov jump system model is proposed to construct a novel linear model of the 2-degree-of-freedom robot arm subject to two types of disturbances. Next, in order to estimate the uncertain harmonic disturbance, a novel higher order disturbance observer is introduced to convert the uncertain harmonic disturbance into some parameter uncertainty and then estimate the parameter uncertainty. In addition, a corresponding composite anti-disturbance control scheme is formulated to reject and attenuate the above two types of disturbances, respectively. Furthermore, sufficient conditions that can guarantee that the system is stochastically stable are given. Finally, a simulation study of the obtained model is carried out to illustrate the validity of the composite control design method proposed in this paper. [ABSTRACT FROM AUTHOR]

An index of authors and the subjects for the December 2012 issue of "IEEE Transactions on Circuits & Systems. Part I: Regular Papers" is presented.

Provides a listing of current staff, committee members and society officers. [ABSTRACT FROM PUBLISHER]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

This article presents the author's views on the publication of the journal "IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I." It is informed that apart from regular issue papers, the editorial board of the journal has approved three special issues during the past year. The first one on Biomedical Circuits and Systems is the current issue. The other two are on Life Science Circuits and Systems, and Smart Sensors, respectively, and will be published in the last quarter of 2006. The author states that it has been a pleasure for him to serve as the editor-in-chief of the journal during the years 2004 and 2005.

In 1971, Dr. Leon Chua, known as the father of nonlinear circuits and cellular neural networks, postulated the existence of memristor, a portmanteau of memory resistor, in his seminal paper: “Memristor—The missing circuit element” published in IEEE Transactions on Circuit Theory, the predecessor of IEEE Transactions on Circuits and Systems—I: Regular Papers. In 2008, Hewlett-Packard researchers made nanomemristor devices for the first time, setting off an upsurge of memristor research. The emergence of nanomemristor devices is expected to realize nonvolatile RAM. Moreover, the integration, power consumption, and read–write speed of the RAM based on memristor are superior to those of traditional RAMs. The hardware network based on memristor synaptic devices is an important development direction of neuromorphic computing. It is a powerful technical candidate to break through the traditional von Neumann computing architecture in the post-Moore era, which will provide a feasible scheme about a technological breakthrough for surpassing Moore’s law. [ABSTRACT FROM AUTHOR]

A subject and author indexes for the 2010 issue of "IEEE Transactions on Circuits and Systems Part I: Regular Papers" is presented.

The article offers information on the LCD technology used by manufacturers in the electronic paper (e-paper) display. It states that today's e-paper has readability, low power and liquid crystal display (LCDs) have brilliant colors as well as full video motion. Moreover, the multimode display from Pixel Qi, in San Bruno, California, has taken a brute-force approach, which combines reflective and transmissive liquid crystal technologies.

The article focuses on the liquid crystal display (LCD) created by Mary Lou Jepsen of Pixel Qi Corp. It states that Pixel Qi display offers black and white reflective mode for power savings and sunlight readability electronic paper (e-paper). Moreover, the prototype screen has outperformed 3Qi display and has beaten E Ink Corp. by its color quality and video playback. It mentions that Jepsen is finding ways to improve the screen like adding touch-sensitive overlays and flexible back planes.

A well-performed capacitive power transfer (CPT) system highly depends on its compensation to achieve load-independent (LI) output and zero phase angle (ZPA) operation. It is particularly meaningful to maintain these objectives under various misalignments. This paper is devoted to a general and comprehensive method to study and explore all the potential high-order compensations. The coupler parameter variation is evaluated under different types of misalignment, and misalignment-insensitive (MI) parameters are properly designed for MI resonance. A general and straightforward decomposition and synthesis method is then proposed to generate the high-order resonant tanks. With the help of inverse ABCD parameters, all tank candidates are further judged by their capability for LI output and ZPA operation. Finally, two example CPT systems are built to verify the LI output and ZPA operation under misalignment. [ABSTRACT FROM AUTHOR]

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

Chaotic image encryption is widely used in the field of information security. This paper proposes a novel chaotic image encryption method with spiral-transform-based fractal sorting matrix (STFSM). First of all, the theory of STFSM with good scrambling effect is introduced, which has good irregularity and iterative. Then, the iterative algorithm and calculation example of STFSM are introduced. STFSM can be used as the map of spatial location transformations to implement the design of image encryption. Based on the complete STFSM theory and iterative algorithm, a chaotic image cryptosystem based on STFSM is proposed to achieve a good image encryption process. To test the security of the proposed algorithm, security tests and analyses such as entropy analysis, correlation analysis, resistance to differential attacks analysis, and robustness analysis are used for the proposed algorithm. The experimental analysis illustrates that the algorithm has a better encryption effect, whether using conventional tests or the attacks simulations described in this paper and can also effectively resist the attacks. [ABSTRACT FROM AUTHOR]

For a class of nontriangular nonlinear systems in presence of unknown disturbances, we propose a predictor-based neural dynamic surface control (PNDSC) strategy in this paper. This nontriangular system is transformed via the mean value theorem, and a predictor is then constructed. To avoid an algebraic loop problem, partial state vectors are employed as input signals of neural networks (NNs) for approximating unknown dynamics, and compensation items are designed to compensate for approximation errors from NNs. Different from the traditional NDSC, the PNDSC in this paper utilizes prediction errors to update learning parameters for improving NNs’ learning behaviors with overlarge adaptive gains. On the basis of improved NNs’ approximation behaviors, a predictor-based NNs disturbance observer (PNNDO) is constructed for compensation for external disturbances and approximation errors from NNs. Furthermore, with predictors, a normalization method of weights is developed to reduce the number of online learning parameters. On the basis of the aforementioned result, measurement noises are taken into account in our predictor-based neural control strategy. We employ predictor states, rather than measurement information paralyzed by noises, in design of our control strategy. This reduces high-frequency oscillations in control input. A Lyapunov-based stability analysis shows that all signals are ultimately bounded in the closed-loop system. Finally, the effectiveness of the proposed control strategy is verified by a numerical example and a permanent magnet brushless DC motor system. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) with large scales of artificial neurons are increasingly used in recognition and classification tasks. In power-constrained scenarios, the tradeoff between performance and hardware consumptions must be carefully evaluated before silicon tape-out. In this paper, we proposed a systematic approach to design ultra-low power NN system. This work is motivated by the facts that NNs are resilient to approximation in many of the computations and NNs are outputting statistical tensors which are acceptable to less-than-perfect results. We resort to the front-back end approach with a twofold aim: (1) a fast and accurate design approach is proposed by estimating the computing quality of low-power approximate adder arrays, and it is adopted to evaluate the neural network system; (2) a quality configurable engine with different approximation degrees while processing NNs is implemented. The proposed work is demonstrated with a comprehensive keyword spotting (KWS) system as an ultra-low power NN engine. The experimental environment is setup with ten keywords from the google speech command dataset (GSCD) using an industrial 22-nm ultra-low-leakage (ULL) process. Comparing to the state-of-the-art KWS processors, the proposed approximate NN engine can demonstrate over 60% improvement in power efficiency and $1.1\times $ area efficiency while achieving similar recognition accuracy. [ABSTRACT FROM AUTHOR]

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%. [ABSTRACT FROM AUTHOR]

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

In this paper, aiming to systematically derive single-inductor multi-input multi-output (SI-MIMO) converters having favorable merits of high-density and low-cost, a basic model is firstly extracted from the working principle. Theoretically, by enumerating all possible connections of the basic model and one-by-one manually judging their effectiveness according to working criterions, multiple viable SI-MIMO topologies can be obtained, but with heavy workload. To simplify the topology derivation process, this paper also proposes a computer-aided method to replace the manual effort. By modelling the basic model and working criterions with graph theory, MATLAB codes can be developed to automatically screen out the effective topologies. With the proposed method, 8 three-port, 28 four-port and 115 five-port converters with single inductor are conveniently obtained, including both the existing and new topologies. Moreover, by configuring ports and switches in each derived topology, multiple specific converters can be further expanded. These converters can provide more options for practical engineering applications, and a new topology is also introduced and experimentally verified in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

Welcome to this Special Issue, a collection of selected papers presented at the 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016), held in Montreal, QC, Canada, 22–25 May 2016. More than 1000 delegates attended the conference, where 781 papers were presented, selected from 1687 papers submitted across 15 tracks. [ABSTRACT FROM PUBLISHER]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

Presents institutional listings relating to this publication. [ABSTRACT FROM PUBLISHER]

This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (Mth-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted \ell 1-norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures. [ABSTRACT FROM AUTHOR]

Newsha Ghaeli reached down an open manhole one morning in April and grabbed a hose dangling in the rushing streams of the sewer below. As she pulled up the hose, she spotted a wad of toilet paper clinging to its end and recoiled in disgust, accidentally splashing a few drops of dirty water on strands of exposed hair sticking out from her face mask. A Cambridge, Mass., sanitation worker offered comfort: "A little caca won't hurt you," he said. [ABSTRACT FROM PUBLISHER]

This paper examines the long-standing problem of linear quadratic regulation and stabilization for Itô stochastic systems with input delay. This problem remains a primary challenge because the separation principle does not hold for Itô stochastic systems. This paper presents a complete solution to the problem: 1) The (sufficient and necessary) solvability condition of the optimal control and the analytical controller are given based on the modified Riccati differential equation defined herein. 2) The sufficient and necessary stabilization condition in mean square sense is explored. We show that the Itô stochastic system with input delay is stabilized if and only if the modified algebraic Riccati equation developed in this paper has a unique positive-definite solution. The essential obstacle encountered in this paper concerns a Delayed Forward-Backward Stochastic Differential Equation (D-FBSDE), which is mathematical challenging. [ABSTRACT FROM PUBLISHER]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM AUTHOR]

Printed in U.S.A. Digital Object Identifier 10.1109/TCSI.2021.3061831 Copyright of IEEE Transactions on Circuits & Systems. Postmaster: Send address changes to IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS - I: REGULAR PAPERS, IEEE, 445 Hoes Lane, Piscataway, NJ 08854. IEEE CIRCUITS AND SYSTEMS SOCIETY The IEEE Circuits and Systems Society is an organization of IEEE members with professional interest in the field of circuits and systems theory. [Extracted from the article]

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal. [ABSTRACT FROM PUBLISHER]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication. [ABSTRACT FROM AUTHOR]

In this paper, we first address the dynamics of the elegant multivalued quaternionic Hopfield neural network (MV-QHNN) proposed by Minemoto et al. Contrary to what was expected, we show that the MV-QHNN, as well as one of its variation, does not always come to rest at an equilibrium state under the usual conditions. In fact, we provide simple examples in which the network yields a periodic sequence of quaternionic state vectors. Afterward, we turn our attention to the continuous-valued quaternionic Hopfield neural network (CV-QHNN), which can be derived from the MV-QHNN by means of a limit process. The CV-QHNN can be implemented more easily than the MV-QHNN model. Furthermore, the asynchronous CV-QHNN always settles down into an equilibrium state under the usual conditions. Theoretical issues are all illustrated by examples in this paper. [ABSTRACT FROM AUTHOR]

This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continuous dynamics is stable and the case that the discrete dynamics is stable. To implement multiple Lyapunov functions, there are two subcases considered in this paper: the subcase that the estimates on the derivatives of the multiple Lyapunov functions are the same and the subcase that the growths of the multiple Lyapunov functions by the jumps are the same. For aforementioned different cases, sufficient stability conditions are established for stochastic impulsive switched systems. Finally, the developed theory is illustrated through examples from networked control systems and synchronization problem of 3-D novel chaotic circuit systems. [ABSTRACT FROM PUBLISHER]

This paper proposes a hybrid dynamic model of thyristor controlled series compensators (TCSCs). The objective is to demonstrate, through advanced circuit theory tools and numerical simulations that some modeling aspects are not properly taken into account in the existing literature. In particular, we consider those related to the role of the TCSC impedance when the line current is polluted by harmonics and to the phase-locked loops (PLLs). Shooting methods and periodic small signal analyses are utilized to compute the impedance of the TCSC at sub-harmonics that are typical of the sub-synchronous resonance phenomenon. The case study focuses on the impact of sub-harmonics, on the behavior of the TCSC and on the synchronization of the firing angle through the PLL. Modeling recommendations are finally drawn based on the results presented in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2k feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. [ABSTRACT FROM PUBLISHER]