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At present, one of the main issues in electric power networks is the reduction in conventional generation and its replacement by low inertia renewable energy generation. The balance between generation and demand has a direct impact on the system frequency and system inertia limits the frequency rate of change until compensation action can be undertaken. Traditionally generation managed frequency. In future, loads may be required to do more than just be able to be switched off during severe under frequency events. This thesis focuses on the development and practical implementation of the control structure of a smart adaptive load for network power-frequency support applications. The control structure developed makes use of advanced demand side management of fan loads (powered by AC drives) used in heating, ventilation, and air conditioning systems; where a change in power at rated load has little effect on their speed due to the cubic relationship between speed and power. The AC drive implemented in this thesis is based on an induction motor and a two level voltage source converter. To achieve the smart adaptive load functionality, first a power-frequency multi-slope droop control structure (feedforward control) is developed; relating the frequency limits imposed by the network supplier and the fan power-speed profile (Chapter 2, Fig 2.19). Secondly, this control structure is combined with the control developed, in Chapter 3, for the AC drive powering the fan load. The full development of the control structure of the AC drive, its tuning process and its practical implementation is given; an equation is developed to find suitable tuning parameters for the speed control of the nonlinear load (fan load), i.e. Eq. (3.59).The analysis and simulation results provided in Chapter 4 conclude that a fast control of the active power drawn by the AC drive is possible by controlling the electromagnetic torque (hence current) of the induction motor without disturbing the fan load overly. To achieve this, changes between closed loop speed control and open loop torque control (power control) are performed when needed. Two main issues were addressed before the hardware implementation of the smart adaptive load: the estimation of the network frequency under distorted voltage conditions, and the recovery period of the network frequency. In this thesis two slew rate limiters were implemented to deal with such situations. Other possible solutions are also outlined. Finally, experimental results in Chapter 5 support results given in Chapter 4. A full power-frequency response is achieved by the smart adaptive load within 3s.

Frequency synthesizers play a crucial role in modern wireless communications as the local oscillator in a transceiver’s upconverter and downconverter. One type of frequency synthesizer utilizes a phase-locked loop (PLL) to generate a frequency that is a multiple of a fixed reference. Integer-N PLLs are typically insufficient in modern wireless standards due to tight channel spacing putting a restrictive limit on reference frequency and bandwidth. Fractional-N PLLs, however, can precisely generate an output frequency that is a fractional multiple of the reference by toggling between division ratios. This thesis covers the design and simulation of a 1.2GHz low-power fractional-N PLL-based frequency synthesizer in 65nm CMOS. System-level and circuit-level design choices and simulations are shown, including a true single phase clock phase frequency detector, a charge pump, a 3rd order loop filter, a voltage-controlled oscillator, a toggleable frequency divider, and a 16-bit 2nd order delta sigma modulator.

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz.

This thesis addresses a real power sharing method of electronically interfaced dis tributed generation (DG) units in the context of a multiple-DG micro-grid system where there is no synchronous generator. The emphasis is primarily on electronically interfaced DG (EI-DG) units like DFIG connected wind generator, PV system and battery storage. In this dissertation, the main goal is designing and testing of a new algorithm to distribute the load changes among intermittent distributed generators according to their power ratings. The power sharing by the commercial distributed energy resource (CDER) unit is mainly based on locally measured signals without communications. In the controller, proposed in this thesis, the voltage source inverter of the battery energy storage system (BESS) changes the frequency of the network with the change in load demand. The real power of each CDER unit is controlled based on a frequency-droop characteristic and a complimentary frequency restoration strategy. A systematic approach to develop a small-signal dynamic model of a multiple-DG micro grid, with a real power management method, is also presented. The model is used to investigate the sensitivity of the design to the changes in parameters and operatingpoint and to optimize performance of the micro grid system. Finally, the performance of the proposed algorithm is tested on a benchmark medium voltage network.

In modern communication systems, the voltage-controlled oscillator is an important circuitry that has applications such as clock generations, wireless communication, synchronization, and frequency synthesis. The most concentration in VCO research has been lower phase noise, higher frequency, low power consumption, and wide tuning range. Each of the goals is reachable on its own at the cost of other goals in VCO design. There are tradeoffs in the design where in this thesis, the middle ground is found in order to achieve low phase noise and low power consumption. This paper will provide a detailed analysis of Low Phase Noise and Low power consumption VCO using 65nm technology. The design of the PLL is analyzed where the VCO effect is explained. The types of noise in the VCO that lower the phase noise are discussed in section 2.2.3. The circuit simulation will be demonstrated in order to achieve the goal of low phase noise and power consumption. Isolation techniques will be provided in order to make sure VCO operates properly. This paper will include full layout techniques used to make the VCO for the SSPLL application. Fabricated stand-alone VCO will be measured and compared to the simulation.

Abstract: Sampling, employed as a special type of mixing, allows using a low local frequency to down-convert the high-frequency RF signal. Existing work of sampling is limited to analog sampling. If a high-speed digital sampler is directly applied to sample the RF signal, the generated output will be the 1-bit digitized alias signal corresponding to the RF input. We show in simulation that a digital sampler, implemented with a sense amplifier such as a StrongARM latch or a current mode logic (CML) latch, can greatly extend the operating frequency when compared to static digital dividers implemented with the same circuit (i.e., through 130 GHz for circuit implemented in TSMC 40nm bulk CMOS process). In a traditional high-frequency PLL implementation, analog frequency dividers that typically use inductors are needed when exceeding the frequency operation range of digital dividers. Unfortunately, these analog dividers not only cost in power consumption and large silicon areas but also suffer from limited frequency ranges. To solve this problem, another circuit architecture, named the alias-locked loop (ALL), which utilizes the advantage of digital sampler and applies it in the feedback path to replace the dividers, was proposed [15]. An ALL has several advantages including wide frequency range of operation, saving silicon area and design cost, but suffers from several drawbacks, including spurs and the need for two reference clocks. One significant drawback of an ALL is that the feedback signal to the PFD (phase frequency detector) may not be single-tone periodic in most cases, which therefore introduces periodic spurs. To solve this problem, another circuit architecture, named coresidual alias-locked loop (C-ALL), which uses a digital circuit and the sampling clock to synthesize the reference signal, is proposed. By predicting the expected pattern of 1's and 0's and providing this signal to the phase detector, a C-ALL can mitigate the periodic PFD pattern that generates frequency spurs in an ALL output (by as much as 27.7 dB in simulation). In addition, a C-ALL does not require a second reference clock. The C-ALL control loop has a “dead zone” in lock when the phases are close, but no net charge pump signal is generated. This dead zone results in only a coarse phase lock and no effective suppression of phase noise. To solve this problem, we propose a new type of locking mechanism and a new type of circuit architecture we call a Phase Shift Coresidual Alias-Locked Loop (PS-CALL), which guarantees feedback at every active edge of the alias signal, thus eliminating the dead zone and achieves fine phase lock. Our simulations show that a PS-CALL can not only achieve phase lock but also reduces the spur level by 16.2 dB compared to a normal C-ALL. We propose another circuit architecture named the differential alias-locked loop (D-ALL) to avoid the second reference clock required by an ALL. In a D-ALL, two feedback signals are generated from two samplers clocked at different sampling frequencies (divided down from a common clock), and the sampled signals fed into the phase frequency detector (PFD). Spectre post-layout extracted circuit simulations have verified the proposed design can achieve lock at programmable frequencies in the range of 21–23.3 GHz. In addition to digital sampling and its applications in high-speed PLLs, other issues in PLLs are also discussed in this thesis. The capacitor in the loop filter is either an off-chip discrete component preventing full integration, or on-chip consuming significant silicon area. Moreover, the voltage ripples on the loop filter output can result in large spurs at the VCO output. To address these two issues, a new circuit architecture is presented with a VCO-based integrator to replace the charge pump and loop filter. Instead of using a charge pump and capacitor as the integrator, a VCO is used to implement the integrator with the phase being the output in the proposed PLL architecture. To ensure loop stability, a voltage-controlled delay line (VCDL) is developed to introduce a zero in the loop transfer function. Spectre simulation has verified the proposed design with a VCO-based integrator can successfully synthesize the targeting frequency at 3 GHz with 39% of total silicon area saving at a cost of 109% increase in total power consumption, without compromising on phase noise performance.

This thesis applies the concept of a virtual-synchronous-machine- (VSM-) based control to a conventional 250-kW utility-scale photovoltaic (PV) inverter. VSM is a recently-developed control scheme which offers an alternative grid-synchronization method to the conventional grid-tracking control scheme, which is based on the dq phase-locked-loop- (PLL-) oriented vector control. Synchronous machines inherently synchronize to the grid and largely partake in the stabilization of the grid frequency during power system dynamics. The purpose of this thesis is primarily to present the design of a grid-forming control scheme based on the VSM and the derivation of the terminal dq-frame ac impedance of the small-signal model of the inverter and control scheme. This design is also compared to the design of the conventional grid-tracking control structure, both from a loop design and terminal dq-frame ac impedance standpoint. Due to the inherent lax power-balance synchronization, the grid-forming control scheme results in 1 to 2 decades' lower frequency range of negative incremental input impedance in the diagonal elements, which is a favorable condition for stability. Additionally, the stability of the grid-forming control scheme is compared to the conventional grid-tracking control using the generalized Nyquist criterion (GNC) for stability under three modes of operation of active and reactive power injection. It is found that the connection is stable for both control schemes under unity power factor and fixed reactive power modes; however, the grid-forming control is able to inject twice the amount of active power under the voltage regulation mode when compared to the grid-tracking control.

In a wide-band RF system, the RF channel is located within 50 MHz to 9 GHz. A high-frequency resolution phase-locked loop (PLL) with 100$\%$ tuning range oscillator is the core to generate the RF carrier frequency which covers such a wide range. The phase noise and spurs of the PLL are required to be low to avoid degrading RF system performance. A PLL applies $\Sigma \Delta$ modulation to increases its resolution and is known as a fractional-N PLL, but $\Sigma \Delta$ modulation introduces considerable quantization noise into the loop. The nonlinearity of the PLL also converts part of the noise into fractional-N spurs. Noise cancellation is usually applied to eliminate this quantization noise. Calibration, often with long settling time, is necessary to maintain cancellation efficiency. Power intensive calibration is also required to notch spurious tones. In this thesis, we first investigate the delay-locked loop (DLL) and attempt to use DLL to replace PLL as an RF frequency synthesizer. An LTI model of DLL is established, which indicates the limitation of DLL as a high-performance synthesizer. Then, the thesis focuses on PLL again. A calibration-free triple-loop PLL is introduced. The merits of heterodyne PLL are rediscovered, which applies a mixer in the loop to translate the VCO frequency to a low-frequency feedback signal. By implementing the harmonic mixing concept, the designed prototype effectively reduces the pulling risk of a traditional heterodyne PLL, allowing it to be integrated on a single chip. This PLL provides higher-order noise filtering and can naturally reduce fractional-N PLL noise and spurs. An analytical model for this PLL is also presented, which allows us to fully appreciate this PLL and optimize the loop design. After this, a sub-sampling PLL-based low-noise frequency extender is introduced, which increases the tuning range of an oscillator from 30$\%$ to 100$\%$, and requires only a small chip area. By combining the triple-loop PLL and the frequency extender, a synthesizer which can support a wideband radio system is achieved.

Low-power wireless receiver design has been an active area of research during thelast decade. One of the most difficult part of the design is generating a spectrally pureclock signal for demodulation in an energy efficient manner. The clock generation is usuallydone through either a phase-locked loop, and the energy cost of implementing a PLL isusually more power expensive than the the rest of the receiver. Therefore, the solutionsthus far have been to use a simple modulation schemes such as On-Off-Keying(OOk).However, such modulation schemes are spectrally inefficient, and as the density of wirelessdevices grow larger, more stringent spectral efficiency will be demanded even for low-powerxivapplications. This dissertation presents a search for an alternative to an envelope-detector.We have investigated a PLL-less coherent detection, as well as an ultra-low power PLLfor an alternative to an envelope detector. Chapter 1 describes the general link budgetrequired for such low-power applications. Popular low-power receiver architectures aredescribed in this chapter. Chapter 2 presents a PLL-less receiver architecture that employs asuper-regenerative oscillator as a phase storage element. The chapter details the system leveland circuit design as well as the measurement results. Chapter 3 presents a mathematicalmodel for super-regenerative reception of phase-modulated signal. The theoretical modelneeded to build the receiver presented in chapter 2 was not available at the time of the design.The authors investigated the behavior of super-regenerative receivers when it is used toreceive phase-modulated signals employing modulations such as phase-shift-keying (PSK).Chapter 4 describes a low-power PLL architecture that is promising enough to meet boththe power and the noise requirement of low-power wireless communication applicationsat 2.4 GHz. The in-band phase noise of sub-sampling PLL can approach the theoreticallimit of the reference phase noise. However, SSPLL can suffer from a significant spurioustone. This chapter presents a sub-sampling PLL architecture that can lower the spurioustone significantly without relying on a power-expensive calibration scheme. Furthermore,the entire loop (except the oscillator) consumes less than 500 microwatts of power, and thetotal power consumption of the PLL is less than 1 mW, suitable for low-power wirelesscommunication applications

Mixed signal circuit design often involves circuits that are time-varying or highly non-linear, which further results in systems that are difficult to characterize using established methodologies for linear time-invariant systems, thus designers are more than often forced to rely on intensive simulations for design. This dissertation explores design optimization for comparators, phase locked loops and ADC from three different perspectives.First, a complete analysis for regenerative comparators is presented including noise, offsets and speed for the first time. Despite the fact that the comparators are time-varying and regenerative with infinite gain, simple equivalent circuits still accurately capture their operation. Design guideline are provided for different comparator architectures.Second, a linearized analysis for phase locked loops using bang-bang phase detectors is presented. The high non-linear bang-bang phase detector is ascribed to an effective gain, whose physical meaning is interpreted in signal space. Closed form expressions for loop gain, output jitter and phase noise profile are obtained using transfer functions for the first time. Design guidelines are also provided.Last, a 2.5GS/s 10bit 65mW ADC in 28nm CMOS FD-SOI without active amplifier and intensive digital calibration is presented. This highlights the potential of circuit design based on complete understandings. The fabricated ADC with considerably less complexity achieves comparable performance with state-of-arts. Different imperfections are quantitatively studied and compared with measurement.

As fabrication technology improves, computation ability has increased accordingly and enables new applications such as biomedical and health monitoring system, internet of things (IoT) and home security surveillance. To satisfy stringent requirements such as limited supply, power and area for these new specs of emerging applications, critical circuit blocks must operate under low supply voltage and if possible generate power from ambient environments. Besides, these new applications can be further popularized if costly off-chip passive components which occupies large PCB footprint can be avoided.This thesis firstly introduces fundamentals of phase locked loop (PLL) which provides clock to all analog and digital circuits in systems. Then a 0.75V 0.014mm2 2.6GHz digital bang-bang PLL with dynamic double-tail phase detector and supply-noise-tolerant gm-controlled DCO is proposed. At last, this thesis introduces a fully integrated CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mV startup voltage. Both circuits adopt no off-chip devices and can operate under low voltage or harvest energy from ambient environments. The prototype DBBPLL has been implemented in a mainstream 28nm CMOS process and consumes 2.9mW at the same time achieves low in-band phase noise of -105dBc/Hz. The energy harvester is implemented in 28nm CMOS, it achieves a self-startup voltage of 110mV without RF input and 85mV at -16dBm input. The boost converter power conversion efficiency (PCE) is 25% and the harvester overall PCE is 10%.

Signal generation at high frequency has become increasingly important in numerous wireline and wireless applications. In many gigahertz and millimeter-wave frequency ranges, conventional frequency generation techniques have encountered several design challenges in terms of frequency tuning range, phase noise, and power consumption. Recently, injection locking has been a popular technique to solve these design challenges for frequency generation. However, the narrow locking range of the injection locking techniques limits their use. Furthermore, they suffer from significant reference spur issues. This dissertation presents novel frequency generation techniques based on envelope detection for low-phase-noise signal generation using injection-locked frequency multipliers (ILFMs). Several calibration techniques using envelope detection are introduced to solve conventional problems in injection locking. The proposed topologies are demonstrated with 0.13um CMOS technology for the following injection-locked frequency generators. First, a mixed-mode injection-frequency locked loop (IFLL) is presented for calibrating locking range and phase noise of an injection-locked oscillator (ILO). The IFLL autonomously tracks the injection frequency by processing the AM modulated envelope signal bearing a frequency difference between injection frequency and ILO free-running frequency in digital feedback. Second, a quadrature injection-locked frequency tripler using third-harmonic phase shifters is proposed. Two capacitively-degenerated differential pairs are utilized for quadrature injection signals, thereby increasing injection-locking range and reducing phase error. Next, an injection-locked clock multiplier using an envelope-based frequency tracking loop is presented for a low phase noise signal and low reference spur. In the proposed technique, an envelope detector constantly monitors the VCO's output waveform distortion caused by frequency difference between the VCO frequency and reference frequency. Therefore, the proposed techniques can compensate for frequency variation of the VCO due to PVT variations. Finally, this dissertation presents a subharmonically injection-locked PLL (SILPLL), which is cascaded with a quadrature ILO. The proposed SILPLL adopts an envelope-detection based injection-timing calibration for synchronous reference pulse injection into a VCO. With one of the largest frequency division ratios (N=80) reported so far, the SILPLL can achieve low RMS jitter and reference spur.

3G and 4G wireless networks have been recently proposed for Machine to Machine (M2M) communications in order to achieve ubiquitous coverage, robust security and high reliability. The most critical design consideration in transceivers for several portable Internet of Things (IoT) wireless communication applications is often power efficiency. This poses a key design challenge in wireless transmitters for communication standards that utilize high peak-to average power ratio (PAPR) signals. In this work, two PLL-based digitally-intensive wireless transmitter architectures employing RF-Pulse Width Modulation (RF-PWM) are presented, in order to address the efficiency challenge. The first architecture employs envelope and phase information, while the second utilizes quadrature I-Q signal components directly. A key contribution of this work is the use of analog-domain Pulse-Width Modulation (PWM) that can directly generate the output signals at the desired RF band without the need for frequency up-conversion and without degradation caused by quantization. By employing Class-D output stages, the proposed architectures can provide enhanced efficiency and allow for the use of broadband loads. These approaches make the designs suitable for multi-band and multi-mode operation. Furthermore, the digitally-intensive architectures can benefit from technology scaling. A prototype RF-PWM transmitter with a Class-D power amplifier (PA) which utilizes a polar approach is implemented in a 65-nm CMOS technology. For an LTE signal with a 1.4 MHz bandwidth and a 6.4 dB peak-to-average- power ratio (PAPR), the RF-PWM transmitter achieves a power-added efficiency (PAE) of 17.5% and an adjacent channel leakage ratio (ACLR) of -30.9 dBc and -31.1 dBc at an average output power of 16.1 dBm. The proposed transmitter achieves a peak output power of 22.4 dBm with 46.6% PAE and 38.8% efficiency for the full RF-PWM transmitter, including PAs.

Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented. Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to TDCs in the past that concentrate on the arrival time difference between the divider feedback edge and the reference signal edge. Our approach extracts the timing information that is embedded in voltage domain. This approach not only achieves a higher time resolution, lower phase noise, but also consumes less power. A digital background calibration circuit is also presented to reduce the output spurious tones when the digital PLL operates under fractional-N divisions. Ring Oscillators (ROs) have the advantage of small area, wide tuning range, and multiphase output. However, their higher phase noise and higher sensitivity to supply noise may seriously deteriorate the wanted signal in wireless receivers. To circumvent this non-ideality, a low overhead phase noise cancellation technique for ring oscillator-based quadrature receivers is presented. The proposed technique operates in background and extracts ring oscillator phase noise as well as supply-induced phase noise from the digital PLL. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. In recent years, the unsilenced band at 57~64 GHz frequency range has motivated the building of high-data rate radio systems targeting wireless personal area network (WPAN) applications. To address this demand, a low-noise wide-band integer-N PLL is presented which serves as the carrier generator of a 60 GHz heterogeneous transceiver. The PLL employs sub-sampling phase detection technique to achieve low-noise performance, and provides 48 GHz LO and 12 GHz IF carrier signals for the heterogeneous transceiver.

Demands for high data-rate communications and high-precision sensing applications have pushed wireless systems towards higher operating frequencies where wider bandwidth is available. Examples of such applications include 60 GHz indoor communications and vehicular RADAR around 77 GHz. High-speed frequency synthesizers integrated in a CMOS process, with wide operating bandwidth, and low phase noise are key to low-cost transceiver implementations for such applications. The requirement to operate over a wide span of carrier frequencies arises from two key sources. The system itself often requires a wide tuning range, in excess of 5-10% of the carrier frequency. Further, it is necessary to compensate for the uncertainty in operating frequencies, caused by process and temperature variations. This dissertation introduces a dual-mode voltage-controlled oscillator (VCO) topology, embedded in a frequency synthesizer, for wideband operation. The VCO can operate in two oscillation modes by reconfiguring the active negative resistance core around the LC tank that is employed as the resonator element in the oscillator. A key aspect to the design is that the switches used for mode reconfiguration do not contribute to the tank loss. The frequency spacing of the two modes is determined by an accurate inductor ratio. It is demonstrated through analysis that in order to ensure mode-switching, the size of the switches needs be larger than a critical value, which is a function of the electrical properties of the cross-coupled, negative resistance core, as well as the resonator used in the design. The impact of noise injection and mismatch on switching behavior is also analyzed. The VCO topology has been implemented in a 65nm CMOS process. The design demonstrates measured tuning ranges of 56.9 GHz to 65.4 GHz, and 64.6 GHz to 75.3 GHz, in the two respective modes, for a total effective tuning range of 28%. The oscillator consumes 13 mW, with a 1 V-supply, and its Figure of Merit with tuning range (FOMT) is -177.2 dB. An integer-N frequency synthesizer that employs the dual-mode VCO, has also been designed and verified in a 65 nm CMOS process. The synthesizer has a locking range from 56 GHz to 63.9 GHz in its low frequency mode. The total power consumption of the synthesizer, including output buffers, is approximately 50 mW. The in-band phase noise, at a locked frequency of 63.04 GHz, is -88.4 dBc/Hz at 1 MHz offset.

Advances in transistor-integration technology and multi-core technology of the latest microprocessors have driven transient requirements to become more and more stringent. Rather than relying on the bulky output capacitors as energy-storage devices, increasing the control bandwidth (BW) of the multiphase voltage regulator (VR) is a more cost-effective and space-saving approach. However, it is found that the stability margin of current-mode control in high-BW design is very sensitive to operating conditions and component tolerance, depending on the performance of the current-sensing techniques, modulation schemes, and interleaving approaches. The primary objective of this dissertation is to investigate an advanced multiphase current-mode control, which provides accurate current sensing, enhances the stability margin in high-BW design, and adaptively compensates the parameter variations. Firstly, an equivalent circuit model for generic current-mode controls using DCR current sensing is developed to analyze the impact of component tolerance in high-BW design. Then, the existing state-of-the-art auto-tuning method used to improve current-sensing accuracy is reviewed, and the deficiency of using this method in a multiphase VR is identified. After that, enlightened by the proposed model, a novel auto-tuning method is proposed. This novel method features better tuning performance, noise-insensitivity, and simpler implementation than the state-of-the-art method. Secondly, the current state-of-the-art adaptive current-mode control based on constant-frequency PWM is reviewed, and its inability to maintain adequate stability margin in high-BW design is recognized. Therefore, a new external ramp compensation technique is proposed to keep the stability margin insensitive to the operating conditions and component tolerance, so the proposed high-BW constant-frequency control can meet the transient requirement without the presence of bulky output capacitors. The control scheme is generic and can be used in various kinds of constant-frequency controls, such as peak-current-mode, valley-current-mode, and average-current-mode configurations. Thirdly, an interleaving technique incorporating an adaptive PLL loop is presented, which enables the variable-frequency control to push the BW higher than proposed constant-frequency control, and avoids the beat-frequency input ripple. A generic small-signal model of the PLL loop is derived to investigate the stability issue caused by the parameter variations. Then, based on the proposed model, a simple adaptive control is developed to allow the BW of the PLL loop to be anchored at the highest phase margin. The adaptive PLL structure is applicable to different types of variable-frequency control, including constant on-time control and ramp pulse modulation. Fourthly, a hybrid interleaving structure is explored to simplify the implementation of the adaptive PLL structure in an application with more phases. It combines the adaptive PLL loop with a pulse-distribution technique to take the advantage of the high-BW design and fast transient response without adding a burden to the controller implementation. As a conclusion, based on the proposed analytical models, effective control concepts, systematic optimization strategies, viable implementations are fully investigated for high-BW current-mode control using different modulation techniques. Moreover, all the modeling results and the system performance are verified through simulation with a practical output filter model and an advanced mixed-signal experimental platform based on the latest MHz VR design on the laptop motherboard. In consequence, the multiphase VRs in future computation systems can be scalable easier with proposed multiphase configurations, increase the system reliability with proposed adaptive loop compensation, and minimize the total system footprint of the VR with the superior transient performance.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.

High performance computing and high resolution range sensor motivates the intelligent system innovations such as smart car, smart home/community and 3D motion games. Most importantly, 3D graphics technique requires high performance computation to provide high quality and vivid real-time videos. Accurate motion sensing requires high resolution radar sensor. However, in general, data transmission limits the large scale computation while high resolution radar signal processor limits the detection accuracy. Therefore, low power design for high speed data transmission and high resolution radar signal processor are desired.Energy efficient transceivers have been aggressively demanded by high performance computing applications. Recently, data center has reached TB/s in 2015 and it would reach 20 TB/s in a few years. Therefore, low cost short range interconnects becomes one of the major limitations for high speed data transmission especially for processor-to-processor and processor-to-memory. Silicon photonics (SiP) has attracted great attentions for its low energy efficiency and less IO pins. In air interface, 15 cm sensing resolution and Gb/s data communication dual mode system enables a layer of network intelligence.The first portion of the dissertation discusses the energy efficient transceiverdesign for optical interconnects. A monolithic micro-ring modulator based transmitter is presented in 130 nm CMOS SOI. In this process, the data rate limitation of monolithic integration is on the eletrical driver. With optimized micro-ring modulator, the transmitter demonstrates 25 Gb/s data rate without pre-emphasis.Secondly, the scaling trends from FD-SOI CMOS to FinFET process is discussed. Since the monolithic integration can not scale the energy efficiency as hybrid integration due to the limitation of optical devices development, hybrid integration keeps the energy efficiency scaling on behalf of the high fT device in advanced process. An optical and electrical co-design algorithm for the WDM link is proposed which focus on the energy efficiency optimization in hybrid integration. Link budget is analyzed and transceivers with planar 28 nm FD-SOI CMOS and 3D 14 nm FinFET are presented.Thirdly, a high speed pulse compression radar (PCR) signal processor is presented in 90 nm CMOS. High speed analog correlation is proposed to replace the conventional digital correlation. This relaxes the high speed requirement in analog-to-digital converter (ADC) design. An analog correlation signal processor is implemented with a variable gain amplifier (VGA), a correlator, a delay-lock loop (DLL), a 4-bits DAC and a 4-bits ADC. Additionally, a new closed-loop calibration algorithm is proposed for DC offset and time misalignment.Finally, a dual mode bidirectional pulse compression radar is proposed. Theradar signal processor is demonstrated in 90 nm CMOS. The system allows 3 Gb/s data transmission in passthrough mode and 10 cm range resolution in radar mode. This is the first demonstration of pulse compression radar signal processor with the features of wireless data communication and high resolution range sensing.

Next Generation aviation, in short “NextGen,” requires an Alternate Positioning Navigation and Timing (APNT) system to back up the Global Navigation Satellite Systems (GNSS). Distance Measuring Equipment (DME) is a favorable APNT candidate but likely needs to be upgraded to enhanced Distance Measuring Equipment (eDME) to support the stringent NextGen aeronautical navigation requirements. This dissertation proposes, researches, and demonstrates eDME carrier phase, a key enabling technology that can dramatically improve the eDME system performance. eDME carrier phase provides line-of-sight displacement measurements with mm-level accuracy.After introducing the eDME carrier phase concept, this dissertation discusses the required changes for airborne and ground equipment. A novel flight test methodology is presented that allows evaluation of the eDME carrier phase performance without requiring changes to existing equipment. A spectrum-based carrier phase acquisition algorithm is presented next. Combined with several interference-mitigation techniques, this acquisition method demonstrates fault-free acquisition.Furthermore, a phase-locked loop (PLL) is designed for eDME carrier phase. A correction term is first proposed to modify the conventional PLL design to reduce the undesired loop stability and bandwidth changes when the loop noise equivalent bandwidth is close to the Nyquist frequency of the loop. This modified PLL is then further adapted to accommodate eDME’s random pulse timing. The carrier phase tracking results show dm-level errors for 110-km straight and level flights and for various banking maneuvers up to 60 degrees. These errors are further characterized and quantified.eDME carrier phase can be used in combination with the eDME pulse range to significantly improve the accuracy and integrity of the DME system. Several algorithms are introduced and the resulting improvement of the eDME accuracy and integrity performance are illustrated. Finally, DME-Next is proposed as a most feasible eDME architecture that fully utilizes the benefits of eDME carrier phase and demonstrates performance sufficient to meet the most stringent NextGen APNT navigationrequirements.

Terahertz (THz) and sub-millimeter wave band are known to provide unique applications in spectroscopy, imaging and high-data-rate wireless communication. An imaging system operating in this frequency region exhibits non-invasive and high-resolution characteristics due to the non-ionized and short-wavelength radiation waves, which makes it attracting for security surveillance. On the other hand, the THz wireless transceiver operating in the license-free spectrum is capable of achieving tens of gigabits-per-second by utilizing a simple modulation scheme. All the benefits mentioned above make THz a promising research topic. Towards realization of a high-performance THz system, one of the most challenging steps is to design a frequency synthesizer. A voltage-controlled oscillator (VCO) is one of the important building blocks within a synthesizer. Due to the server performance degradation of varactors and transistors at high frequencies, new ways of designing VCOs need to be investigated. Here, two different ideas are proposed. First, an inductive-tuning mechanism with high quality-factor and wide tuning-range is introduced. This tuning technique is based on a variable inductor seen at the emitter terminal of a base-degenerated transistor. By adding a series RL at the base terminal, the variable inductor, exhibiting low loss and high tunability, improves the VCO output power and phase noise while achieving a wide tuning range. The second idea, double-stacked cross-coupled VCO, is to design a strong negative resistance cell to compensate for the server loss of the varactor at THz frequencies. By implementing a source-degenerated negative resistor of a conventional cross-coupled pair, the overall negative resistance is enhanced. It also reduces the parasitic capacitance, making it an attracting approach for THz applications. Finally, a novel THz frequency synthesizer is proposed. A 300GHz phase-locked-based synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a three-phase injection locked divider is introduced. The CAV is used to tune the oscillation frequency, enhance output power, and buffer the VCO's fundamental signal. The divider's locking-range is vastly increased attribute to the three-phase injection. This work demonstrates the highest-frequency synthesizer in silicon.

This research addresses problems in designing analog and mixed-signal (AMS) systems by bridging the gap between system-level and circuit-level simulation by making simulations fast like system-level and accurate like circuit-level. The tools proposed include metamodel integrated Verilog-AMS based design exploration flows. The research involves design centering, metamodel generation flows for creating efficient behavioral models, and Verilog-AMS integration techniques for model realization. The core of the proposed solution is transistor-level and layout-level metamodeling and their incorporation in Verilog-AMS. Metamodeling is used to construct efficient and layout-accurate surrogate models for AMS system building blocks. Verilog-AMS, an AMS hardware description language, is employed to build surrogate model implementations that can be simulated with industrial standard simulators. The case-study circuits and systems include an operational amplifier (OP-AMP), a voltage-controlled oscillator (VCO), a charge-pump phase-locked loop (PLL), and a continuous-time delta-sigma modulator (DSM). The minimum and maximum error rates of the proposed OP-AMP model are 0.11 % and 2.86 %, respectively. The error rates for the PLL lock time and power estimation are 0.7 % and 3.0 %, respectively. The OP-AMP optimization using the proposed approach is ~17000× faster than the transistor-level model based approach. The optimization achieves a ~4× power reduction for the OP-AMP design. The PLL parasitic-aware optimization achieves a 10× speedup and a 147 µW power reduction. Thus the experimental results validate the effectiveness of the proposed solution.

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.

With more advanced technology, complete phased array system can be integrated in CMOS. Integrated CMOS phased array systems offer lower cost, lower power consumption, higher reliability and the possibility of on-chip signal processing using ever cheaper digital circuitry. This opens up possibilities for new applications such as directional point-to-point wireless communication which provides high security and is less prone to jamming by interferers. Integrated phased array systems are for the most part not too different from normal single channel transceivers. The key additional component is the phase shifter. A new phased array architecture that uses digital phase locked loop (PLL) modulator to realize phase shift is developed. To achieve phase shifting capability, PLL is a natural candidate. If we combine PLL’s phase shifting and modulation capabilities then we can realize phased array system using solely PLLs. With recent breakthrough in digital PLL, a digital PLL can generate a precise and well-controlled phase shift that analog PLLs cannot. The same phase shift capabilities can be used for data modulation. With both phase shift and data modulation capabilities, we only need an array of such PLLs to realize a phased array. Compared with conventional phased arrays, PLL based phased array can achieve more precise phase shift thus more precise radiation angle. It is also more flexible, since all channels can generate independent phase shift. A fully-integrated 5.8GHz PLL modulator prototype implemented in 65nm CMOS that achieves digitally-controlled arbitrary phase generation is presented. The PLL is a Type II fractional-N PLL with a 1-bit TDC as its PFD. Digital phase setting, which operates by adding a proportional signal to the PFD output, is incorporated in the PLL. The prototype achieves an average measured phase resolution of 2.25o and phase range of more than 720o. The entire PLL and output buffer consumes 11mW. Four of such PLLs form a prototype phased array as a proof of concept.

As data centers are expected to manage the increasing demands in bandwidth, processing power and storage requirements, connectivity issues between blades/racks present a whole new set of challenges in maintaining a stable infrastructure. While data centers may grow to occupy thousands of square feet, current passive copper interconnects pose a real limitation with a run length of 10 meters at 10Gbps per wire pair. Optical fiber can extend the interconnection length from 10 meters to 100 meters, but the large power requirements and expensive opto-electric modules prove to be too uneconomical for practical application. As a compromise, through the use of the Infiniband standard, a 12Gbps cable link can be achieved that would extend the range of copper interconnects beyond the 100 meter threshold. The proposed link leverages synchronous clock forwarding on one available data channel that improves jitter tracking, while greatly simplifying the design of the receiver and timing recovery circuits. Only a phase de-skewing is required at the receive side to retrieve the clock-data relationship. In the cable link architecture, the 12 Gbps data is repeated in 8 meter sections with clocking forwarding on a dedicated channel. Then the forwarded clock is dropped off every data repeating stage in order to be multiplied to half the data rate and be used to strobe the incoming data. The longer the quality of clock forwarding is maintained, the cleaner the data strobed at each repeater and the longer the cable can be extended. At each repeater, the clock resets the jitter accumulated from the previous repeater, allowing for data transmission with as much jitter as in the strobing clock. Determining a fine balance in forward clock frequency is crucial in defining jitter performance of the cable link. Frequency beyond the cable bandwidth results in large attenuation of clock amplitude creating more noise and jitter accumulation along clock repeater. On the other hand, frequency well below the cable bandwidth will increase jitter accumulation time and will degrade jitter performance inside the clock multiplier. The trade-off between low frequency clock jitter accumulation in the Clock Multiplication Unit (CMU) and the high frequency jitter accumulation along the clock repeaters is one of the defining aspects of optimizing the active copper link.To further reduce the clock jitter accumulation across repeaters, phase interpolation between the input clock and the divided output of the CMU is used to generate the forward clock for the next repeater stage. The addition of the phase interpolator has negligible power/area cost, dramatically reduces jitter accumulation, and adds another degree of flexibility in choosing the forwarded clock to reduce the total accumulated jitter. With the proper choice of forward clock frequency, application of the FIR filtering technique and a high performance CMU, a total run length of 115 meters is achieved at 12Gbps data rate.

This dissertation contains three parts. In the first part, the analysis and circuits of a jittercleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented.For the first part, the design utilizes a dual-loop architecture, which is suitable for integration in an SoC environment. The primary loop is a digital PLL with a second-order noise shaping phase-error ADC. The secondary loop is a fractional-N PLL implementing the digitally controlled oscillator inside the primary loop, and it locks to an external clean reference clock to reduce the phase noise and to improve the frequency stability of the on-chip oscillator. For the second part, a tail-tank coupling technique that combines two complementary differential LC-VCOs to form a quadrature LC-VCO is presented. This technique reduces phase noise by providing additional energy storages for noise redistribution and by canceling out most of the noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum value.For the third part, a 2.8 to 3.2 GHz fractional-N digital PLL is presented. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. An ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size to 20 kHz. With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, this prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. A FOM of -240.4 dB is achieved.

There is a strong need for stable frequency references with large tuning ranges in today's communication systems. While the crystal oscillators assure good frequency stability, it is not possible to achieve a large frequency range by tuning the passive components attached to them. Frequency synthesizers are usually used for this purpose because of their ability to produce a variety of output frequencies. The Phase Locked Loop (PLL) based frequency synthesizer is the most preferred of all types of synthesizers available because of its additional features like programmability, low noise and low cost as well as high accuracy and stability. The main idea of this PLL-based synthesizer is to phase-lock its output signal with an input reference signal and to produce a synchronous output. It does this by generating an error signal to correct the oscillator frequency. This functionality is achieved by integrating a phase detector, charge pump, loop filter and voltage controlled oscillator block in series with a frequency divider in feedback. This thesis presents, in detail, the design of all the individual PLL blocks, the strategies employed in the design, issues faced in testing and the test data from simulation and measurement. All the above mentioned PLL blocks are designed in the 130 nm IBM-CMOS cmrf8sf process and optimized for low power consumption. PLLs are used in almost all kinds of communication systems, transmitters and receivers for applications such as carrier recovery, carrier generation, clock slew correction, frequency modulation and demodulation.

The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed.

Abstract: Interfacing and operating AC power electronic systems requires rapid and accurate estimation of the phase angle of the power source, and specifically of the positive sequence of the three-phase utility grid voltage. This is needed to ensure reliable operation of the power control devices and of the resulting power flow. However, the quality of this information is undermined by various distortions and unbalanced conditions of the three-phase grid voltage. Phase estimation and power control can both be performed in real time by a DSP, but a DSP typically has limited computational resources, especially in regards to speed and memory, which motivates the search for computationally efficient algorithms to accomplish these tasks. In contrast to conventional PLL techniques, recent approaches have used adaptive amplitude estimation to enhance the acquisition of the phase information, resulting in faster response and improved performance. This thesis presents a novel technique to estimate the phase of the positive sequence of a three-phase voltage in the presence of frequency variations and unbalanced conditions, referred to as hybrid negative sequence adaptive synchronous amplitude estimation with PLL, or H-NSASAE-PLL. The key feature consists of a feedback structure which embeds a positive sequence PLL and an adaptive synchronous negative sequence estimator to enhance the performance of the PLL. The resulting benefits include faster estimation of the phase of the positive sequence under unbalanced conditions with zero steady state error, simplified tuning of PLL parameters to address a wide range of application requirements, robust performance with respect to distortions and PLL parameters, a structure of minimal dynamical order (fifth) to estimate the main signal parameters of interest, simplified discretization, and reduced computational costs, making the proposed technique suitable for real time execution on a DSP. The H-NSASAE-PLL is developed in the Matlab/Simulink environment, and a specialized test signal generator is developed to evaluate it’s performance. The overall system is executed, and experimental results are produced, in real time, on a dSPACE DS1104 controller board.

The persistent demand for increased data throughput in computer desktops and servers has been driving the design and development of high-speed I/O links in CMOS technologies. Frequency dependent channel loss and imperfections, such as impedance discontinuities, in I/O transceiver building blocks lead to inter-symbol interference (ISI) which limits the achievable link throughput. Crosstalk noise from neighboring channels results in both timing and amplitude errors with the growing data rate trends in chip-tochip communication. In addition, increasing ISI and crosstalk noise sources complicates the design of critical circuit blocks such as timing recovery. All these factors exacerbate the eye closure at the receiver and adversely affect the performance or bit-error-rate (BER) of the overall link. This thesis extends the design scope of current high-speed I/O systems by applying the joint know-how in advanced digital communication and novel circuit implementations. Several architectures and schemes including equalization, timing recovery and timing generation circuits are proposed which address some of the limiting factors in today’s chip-to-chip I/O links. First, partial response (PR) equalization is presented analyzed and demonstrated as a successful candidate for steep roll-off channel classes. Based on this technique, a transceiver with PR transmit equalizer and a 1-tap decision feedback equalizer (DFE) is proposed which increases the signal to noise (SNR) of the received signal at the receiver decision circuit input. The proposed PR1.1.b equalization in this thesis outperforms duobinary signaling by 28% and 19% when comparing vertical eye opening and by 10% and 7% when comparing horizontal eye opening at 10Gbps and 15Gbps respectively. These improvements become significantly higher when the channel is subjected to severe crosstalk noise sources. Additionally this architecture mitigates the circuit design issue related to tight DFE loop timing and convergence. Second, a novel pilot-based clock and data recovery (CDR) circuit is introduced that eliminates the clock recovery performance dependency on channel ISI components. A 5Gbps CDR prototype was designed and fabricated in a 0.13μm CMOS technology which uses simultaneously data and clock transmission over the same channel. The measured recovered clock rms jitter was 1.6ps while only a 5% voltage overhead was imposed onto the transmitter for the pilot signal when subjected to a channel loss of 10dB. Third, a 5.6GHz transmit phase-locked-loop (PLL), prototyped in a 0.18μm CMOS technology, is also presented which dynamically corrects the charge-pump (CP) current and reduces the side-band spurs by 22dB and therefore improves the jitter quality of the PLL generated clock. Finally a unified configurable I/O transceiver solution is introduced that takes advantages of all the architecture schemes and circuits proposed throughout the thesis for future chip-to-chip communication ICs.

Voltage-controlled oscillators (VCOs) are critical components in the design of phase-locked loops (PLLs) for a variety of applications such as high speed digital communication systems, on-chip clock generators and RF transceivers. VCOs experience large supply noise variations due to digital switching currents. This degradesthe jitter performance of the VCO, thus limiting system performance.Supply noise is a major concern in ring oscillators in particular, since the frequencyof a ring VCO is highly dependent on the supply voltage.This thesis presents a novel power supply insensitive voltage controlled ring oscillator. This thesis also discusses some previously adopted VCO buffer stage designs implemented to achieve high supply noise rejection, and compares their results with those achieved with the proposed architecture.Based on the concepts developed in this thesis, a differential ring oscillator wasdesigned in a 0.13-um CMOS technology, to demonstrate the robustness against supply fluctuation. The VCO operates from 236.66 MHz to 373.33 MHz, and displayscomplete rejection to power supply noise.

In this thesis, we present and discuss two advanced architectures of wireless integrated circuits. In the first part of this thesis we will focus on the design of an inductorless receiver, which include a LNA, mixer and frequency synthesizer. Inductors are used in RF design to extend the bandwidth by resonating out the load and/or parasitic capacitance. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this thesis we describe a new methodology for designing the RF frontends necessary for the wideband 1GHz-10GHz bandwidth in a 0.13um CMOS technology. To validate our design methodology two receiver RF frontends were designed; a traditional inductor based design and an inductorless design. A common-gate LNA transconductor is followed by a capacitive peaking LNA-mixer pair (CPLM). Measurement results indicate that CPLM with the same bandwidth has better linearity, comparable noise figure and uses only 17% more power. The silicon area for the CPLM is only 22% of the IPLM. Both designs can be mated with an inductorless, ring-oscillator based, wide lock range and low power PLL also shown in this thesis. We present theory and prototype results for injection-locked frequency dividers based on differential ring oscillators (D-ILFD) and single-ended ring oscillators (S-ILFD), which can be locked to all harmonics (i.e., even and odd). We have developed a general theory for lock range and phase noise for all harmonics for both topologies. Measurement results for the D-ILFD and the S-ILFD show that the lock range decreases with increasing harmonics at the low harmonics while leveling off for larger division ratios. Measured integrated phase noise for D-ILFD and S-ILFD also show that the integrated phase noise decreases with increasing harmonics. The measurement results corroborate our theory. Ring oscillator based D-ILFDs and S-ILFDs are compact and consume low power making them well suited for wideband low power PLLs. We exploit the ring VCO based on an updated Maneatis delay cell with self- boosted biased techniques, which has a ultra wide tuning range of 1 GHz to 10.3GHz. The injection-locked frequency divider (ILFD), which can lock to all harmonics, has been used. A wide lock range, low power PLL based ring VCO and ILFD has been designed for UWB radio. Experimental results indicate that integrated phase noise is below a 30 and power consumption is only 8.6 mA to 22.35 mA for the entire frequency bands. In the second part of this thesis, we focus on noise isolation for mixed-signal (RF/analog/digital) design in CMOS 3D ICs. Faraday cages have traditionally been used to provide isolation from electromagnetic fields. In this thesis, we describe the use of Faraday cages for reducing crosstalk in 3D ICs. We validate our methodology with a combination of simulation and measurements from fabricated prototype designs. Measurement and simulation results show that the crosstalk between the transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday cage in combination with tier-to-tier isolation, which is one of best performance reported so far. Measurement results indicate that the Faraday cages have no effect on the S-parameters and linearity of inductorless RF circuits. We further develop a lumped equivalent model for crosstalk with and without a Faraday cage. There is good agreement between measurement, 3D electromagnetic simulation and lumped circuit simulation.

Fully integrated Ultra-Wideband (UWB) RFIC transmitters are designed in Si-based technologies for applications such as wireless communications or sensor networks. UWB technology offers many unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks and frequency mixing with single sideband mixers ----- are explored in great detail. To generate the required UWB signals, pulse generators are designed and integrated into the transmitter chips. The first prototype UWB transmitter is designed in Freescale Semiconductor 0.18μm SiGe BiCMOS technology for operation over three 500 MHz bands at center frequencies of 4.6/6.4/8.0 GHz, and generates pulses supporting differential BPSK modulation. The transmitter output frequency is controlled by a two-bit code which sets the state of a switched capacitor tank array for coarse tuning of the VCO. While selecting between the different bands, the transmitter is capable of settling and re-transmitting in less than 0.7μs using an integrated, wide band phase-locked loop (PLL). Various issues such as mismatch/inaccuracy of the pulses and high power consumption of the prescaler were identified during the first design and were addressed in subsequent design revisions. The pulse generator is a critical part of the proposed UWB transmitter. The initial pulse generator design used CMOS delay lines and logic gates to synthesize the required pulse bandwidth; however this approach suffered from inaccurate pulse timing control due to delay time sensitivity to device modelling and process variations. Subsequently, a novel pulse generator design capable of achieving accurate timing control was implemented using digital logic and a fixed oscillator frequency to provide timing information, integrated into a modified transmitter circuit, and subsequently fabricated in Jazz Semiconductor's 0.18μm CA18 RFCMOS process. Experimental results confirm the generation of accurate one-nanosecond pulses. Finally, a new multiband UWB transmitter based on a new single sideband (SSB) resistive mixer with superior linearity and zero static power consumption was also designed and fabricated using Jazz CA13 0.13μm RF CMOS process. This design is based on a fixed frequency phase-locked VCO and generates different bands through frequency mixing. In the prototype design, two additional carrier frequencies are generated from the VCO center frequency (5 GHz) by mixing it with its output divided-by-4 (1.25 GHz). By switching the relative I/Q phases of the LO/IF inputs to this single side band mixer, either the upper side band (6.25 GHz) or lower side band (3.75 GHz) frequency is selected at the mixer output, while the other sideband is rejected. Simulation results show that the transmitter is capable of generating the desired carrier frequencies while suppressing the image component by more than 40 dB. Overall, this work has explored various aspects of UWB transmitter design and implementations in fully integrated silicon chips. The major contributions of this work include: proposed hardware architectures for pulse-based multiband UWB transmitters; implemented a fully integrated multiband UWB transmitter with embedded phase-locked switched-tank VCO capable of wide frequency tuning; demonstrated an all digital pulse generator capable of generating accurate one-nanosecond pulse trains in the presence of various mismatches; and investigated resistive SSB mixer topologies and their implementation in a multiband UWB generation architecture.

A 435-MHz, Digital Low-IF (1-MHz), Double Differential Phase Shift Keying (DDPSK) Transceiver circuit for space application was the motivation for engineering our low power Quadurature Phase Lock Loop (PLL). The PLL was designed to meet specifications set forth by NASA and JPL. In this thesis, you will gain knowledge of the implemented design, transistor sizes, the layout as a whole, and the calculations used for the system design. The design consists of two cross-coupled NMOS and PMOS pair analog Voltage Controlled Oscillators with a digital feed back loop.

PLLs find enormous use in applications such as carrier recovery, signal synchronization, frequency division and multiplication. In addition, they can be modified to synthesize multiple stable frequencies in transceiver circuits for receiver tuning. In wireless applications, they are used to demodulate transmitted signals that are frequency or phase modulated. Communication systems require signals with stable frequencies that are robust to noise and other perturbations in the surrounding environment and use of a carefully designed PLL fulfils the criterion. This thesis is focused on modeling high frequency charge pump PLLs using a mixed-signal hardware description language, Verilog-AMS. The flexibility of Verilog-AMS as a mixed-mode modeling language is explored by using it to design a PLL system in three levels of abstraction and comparing their results for accuracy and consistency. Finally, an improvement is suggested to the current architecture in an attempt to enhance the PLL performance.

For the past years, great efforts have been made to implement a single chip transceiver for a target wireless system. More over, world-wide massivetransportations necessitate global communication methods. However, lots of different standards exist nowadays and a mobile unit for a certain standard can not be used for different standards. In order to cover various wireless systems, unless a new unified global communication standard is adopted, conventional systems need to be merged and evolve into a more complicated communication system called a "multi-standard'' transceiver. In a typical receiver architecture, incoming RF signals are multiplied by a local oscillator(LO) signal to obtain desired signals that might be either intermediate frequency(IF) signals or baseband signals. The local oscillator is practically an output signal of a frequency synthesizer. Conventional synthesizers can provide channel selection over a limited band due to limited division ratios of prescalers and voltage-controlled oscillator(VCO) operating frequency ranges. In this dissertation, a frequency synthesizer for multi-standard applications is presented. Based on a phase-locked loop, the synthesizer can provide various channel selection in order to comply with a designer's own frequency plan to cover multiple wireless standards. A fully programmable dual-modulus frequency divider is proposed with a new frequency division method to avoid division ratios that contain a decimal point. Newly developed PLL sub-blocks are presented. A new method to analyze and suppress effects of VCO pushing is introduced. Due to the difficulty in building a wide-band/multi-band LC-tank oscillator, a 900MHz band and tri-band single-ended voltage controlled oscillator(SE-VCRO) are built for the purpose of multi-band test even though they exhibit inferior phase noise performance to their LC-tank counterparts. A phase noise equation for a voltage-controlled oscillator is derived by modifying a phase noise equation from a linear time-varying(LTV) phase noise theory.The new phase noise equation can provide a designer with insights of phase noise information across the VCO's entire operating frequency range. The new SE-VCRO exhibits improved phase noise performance. A test chip (0.5um technology for 800MHz - 1.2GHz applications) is fabricated and partial experimental results are presented and discussed. Another version of the synthesizer is designed with 0.18um technology to cover 800 MHz - 2.4 GHz range and post layout simulation results are presented. The synthesizer is also compatible with a delta-sigma fractional-N architecture due to the fully programmable dual-modulus prescaler.

The Small Aircraft Transportation System (SATS) is a partnership between the FAA, the NASA, US aviation companies, universities and state and local aviation officials. The purpose of SATS is to develop a system to handle future increase in Air Traffic, reduce time-travel, develop automation in Air Traffic Control (ATC) and make better use of small aircraft and underused airports. The Smart Landing Facility (SLF) is an important part of the program. The SLF is a small airport upgraded with equipment to support SATS aircraft. Among the SLF equipment, SATS needs new detection equipment, and eventually automation. This thesis investigates different techniques to avoid data collision in aircraft radar responses, and to reduce delays between landings and take offs. First, the paper shows how and when the radar receiver can separate two overlapped radar responses. Second, to avoid transponders responses overlapping, requirements in terms of aircraft safety distance are computed, different conflicts in air traffic around the SLF are examined and a solution is proposed for each case. And finally, the thesis investigates how far SATS can go in developing an automatic ATC system and what the role of future human operator will be in ATC.