High Speed Digital Sampling and Its Applications in PLLs

Abstract: Sampling, employed as a special type of mixing, allows using a low local frequency to down-convert the high-frequency RF signal. Existing work of sampling is limited to analog sampling. If a high-speed digital sampler is directly applied to sample the RF signal, the generated output will be the 1-bit digitized alias signal corresponding to the RF input. We show in simulation that a digital sampler, implemented with a sense amplifier such as a StrongARM latch or a current mode logic (CML) latch, can greatly extend the operating frequency when compared to static digital dividers implemented with the same circuit (i.e., through 130 GHz for circuit implemented in TSMC 40nm bulk CMOS process). In a traditional high-frequency PLL implementation, analog frequency dividers that typically use inductors are needed when exceeding the frequency operation range of digital dividers. Unfortunately, these analog dividers not only cost in power consumption and large silicon areas but also suffer from limited frequency ranges. To solve this problem, another circuit architecture, named the alias-locked loop (ALL), which utilizes the advantage of digital sampler and applies it in the feedback path to replace the dividers, was proposed [15]. An ALL has several advantages including wide frequency range of operation, saving silicon area and design cost, but suffers from several drawbacks, including spurs and the need for two reference clocks. One significant drawback of an ALL is that the feedback signal to the PFD (phase frequency detector) may not be single-tone periodic in most cases, which therefore introduces periodic spurs. To solve this problem, another circuit architecture, named coresidual alias-locked loop (C-ALL), which uses a digital circuit and the sampling clock to synthesize the reference signal, is proposed. By predicting the expected pattern of 1's and 0's and providing this signal to the phase detector, a C-ALL can mitigate the periodic PFD pattern that generates frequency spurs in an ALL output (by as much as 27.7 dB in simulation). In addition, a C-ALL does not require a second reference clock. The C-ALL control loop has a “dead zone” in lock when the phases are close, but no net charge pump signal is generated. This dead zone results in only a coarse phase lock and no effective suppression of phase noise. To solve this problem, we propose a new type of locking mechanism and a new type of circuit architecture we call a Phase Shift Coresidual Alias-Locked Loop (PS-CALL), which guarantees feedback at every active edge of the alias signal, thus eliminating the dead zone and achieves fine phase lock. Our simulations show that a PS-CALL can not only achieve phase lock but also reduces the spur level by 16.2 dB compared to a normal C-ALL. We propose another circuit architecture named the differential alias-locked loop (D-ALL) to avoid the second reference clock required by an ALL. In a D-ALL, two feedback signals are generated from two samplers clocked at different sampling frequencies (divided down from a common clock), and the sampled signals fed into the phase frequency detector (PFD). Spectre post-layout extracted circuit simulations have verified the proposed design can achieve lock at programmable frequencies in the range of 21–23.3 GHz. In addition to digital sampling and its applications in high-speed PLLs, other issues in PLLs are also discussed in this thesis. The capacitor in the loop filter is either an off-chip discrete component preventing full integration, or on-chip consuming significant silicon area. Moreover, the voltage ripples on the loop filter output can result in large spurs at the VCO output. To address these two issues, a new circuit architecture is presented with a VCO-based integrator to replace the charge pump and loop filter. Instead of using a charge pump and capacitor as the integrator, a VCO is used to implement the integrator with the phase being the output in the proposed PLL architecture. To ensure loop stability, a voltage-controlled delay line (VCDL) is developed to introduce a zero in the loop transfer function. Spectre simulation has verified the proposed design with a VCO-based integrator can successfully synthesize the targeting frequency at 3 GHz with 39% of total silicon area saving at a cost of 109% increase in total power consumption, without compromising on phase noise performance.