HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS

PLLs find enormous use in applications such as carrier recovery, signal synchronization, frequency division and multiplication. In addition, they can be modified to synthesize multiple stable frequencies in transceiver circuits for receiver tuning. In wireless applications, they are used to demodulate transmitted signals that are frequency or phase modulated. Communication systems require signals with stable frequencies that are robust to noise and other perturbations in the surrounding environment and use of a carefully designed PLL fulfils the criterion. This thesis is focused on modeling high frequency charge pump PLLs using a mixed-signal hardware description language, Verilog-AMS. The flexibility of Verilog-AMS as a mixed-mode modeling language is explored by using it to design a PLL system in three levels of abstraction and comparing their results for accuracy and consistency. Finally, an improvement is suggested to the current architecture in an attempt to enhance the PLL performance.