15 results on '"Miller, James W"'
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2. A new full-chip verification methodology to prevent CDM oxide failures.
3. Study of undoped channel FinFETs in active rail clamp ESD networks
4. A co-optimization methodology on ESD robustness and functionality for pad-ring circuitry.
5. Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies
6. Advanced ESD rail clamp network design for high voltage CMOS applications
7. Investigation of product burn-in failures due to powered NPN bipolar latching of active MOSFET rail clamps.
8. Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe.
9. Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology.
10. A Wireline-Retrievable Wellhead Plug System For Use With Horizontal Trees
11. Investigation into bake-reversible low-level ESD-induced leakage
12. Maximization of nMOSFET hot-carrier injection stability through optimization of device and process design
13. Investigation into bake-reversible low-level ESD-induced leakage.
14. Structure/Performance Relationships For Barium Sulfate And Strontium Sulfate Antiscalants
15. Outstanding contributions award.
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