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The aim of this project is to reduce the gate leakage current and improve the drain characteristics by varying the source/ drain length in the MESFET (Metal Semiconductor Field Effect Transistor) and compared with MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) by using nanotechnology. Materials and Methods: The MOSFET and MESFET are considered as 2 groups having 21 samples respectively, so the total number of samples is 42. The simulation was carried out in the DFT tool and G-power is 80%. Result: MESFET has significantly higher drain current (0.00231mA) than MOSFET (0.00135mA). The optimal drain region length for maximum drain current was 1nm for MESFET and 1nm for MOSFET. Conclusion: The independent t test was done which reveals that the MESFET (p < 0.05) was found to be statistically highly significant compared with MOSFET. [ABSTRACT FROM AUTHOR]

The project aims to improve the drain characteristics of a novel Metal Semiconductor Field Effect Transistor (MESFET) by reducing the size using nanotechnology and compared with MOSFET. The reduction in the size of the MESFET will be done as per Moore's law and will lead to an increase in the density of devices on a single chip. The MOSFET and MESFET was chosen as a group having 21 samples each respectively. The drain characteristics were simulated by varying the channel length of a MESFET and MOSFET. Reducing the channel length of a MESFET will lead to reducing the size of the device and G-power is 80%. The Independent t test was done which reveals that the MESFET (p<=0.05) was found to be statistically significant compared with MOSFET. The analysis found that MESFET (mean 123.165) having the channel length has statistically better drain characteristics compared to MOSFET (mean 14.496). [ABSTRACT FROM AUTHOR]

The aim of the project is to improve the drain characteristics of a novel Metal Semiconductor Field Effect Transistor (MESFET) by reducing the size using nanotechnology and compared with Metal Oxide Semiconductor Field Effect Transistor (MOSFETThe MOSFET and MESFET were chosen as two groups having 21 samples each respectively. The drain characteristics were simulated by varying the substrate thickness in a MESFET. Reducing the source region length of a MESFET will lead to reducing the size of the device. The G power analysis is used for determining the sample size which contains two different groups, alpha (0.05), power (80 %) and enrollment ratio. The independent t-test was done which reveals that the MESFET (p <0.05) was found to be statistically significant compared with MOSFET. The analysis found that MESFET (0.00235 A) has significantly better drain characteristics compared to MOSFET (0.00131 A). [ABSTRACT FROM AUTHOR]

In order to replicate the current and voltage characteristics of MESFET and single-gate MOSFET, several channel materials will be used (Si, Ge, GaAs). The following are the materials and procedures used: In the NANOHUB tool simulation environment, the electrical conductance of 360 MESFET (Si, Ge, and GaAs) and 120 MOSFET samples was assessed. Results: The conductance of Ge-MESFET is much larger than that of MOSFET (P0.05) (4111.602*10-6 mho). Conclusion: Ge-MESFET has a higher conductivity than MOSFET within the scope of this research. [ABSTRACT FROM AUTHOR]

The aim of this project is to reduce the gate leakage current and improve the drain current by varying the source/ drain length in the MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) and novel SOI (Silicon on Insulator) device using nanotechnology. The MOSFET and SOI are considered 2 groups having 23 samples respectively, so the total number of samples are 46. The simulation was carried out in the DFT tool. Within the limits of this study, SOI (Mean -22.62) has better drain current compared with MOSFET (Mean - 15.04). SOI has significantly higher drain current (P=0.190) than MOSFET. The optimal source/drain length for maximum drain current was 15nm for SOI and 15nm for MOSFET. [ABSTRACT FROM AUTHOR]

Fabrication of transition metal dichalcogenides(TMD) including WSe2(tungsten diselenide), PdSe2(Palladium diselenide) which are also a semiconductor itself is a challenge in field effect transistors(FET). Current metal-semiconductor junction in FET faces a non-ohmic contact due to its Schottky barrier (SB). SB is an energy barrier that prevents you from having ohmic contact when metal and semiconductor come into intimate contact. Silicon based electronics used ion-implantation for doping to have ohmic contact [1]. However, a thin layer of TMD materials can render implantation unnecessary. In order to reduce conduct resistance in TMDs, we insert TMDs at the metal/semiconductor interface. [ABSTRACT FROM AUTHOR]

From the past decade to modern era, new technology nodes have overcome many challenges from previous nodes in order to achieve Moore's Law. Modelling Various architectures with different parameters to achieve high channel current and low offset leakage current is crucial. In this work, a new 7nm GAAFET and 7nm TRIGATE FinFET device design were modelled. 2-types of FinFET's, Short Gate FinFET (SGFinFET), Independent Gate FinFET (IGFinFET) and single channel GAAFET, Multi-Channel GAAFET Mode models were designed and compared using Sentaurus TCAD. Using high dielectric materials such as SiO2 and HfO2 as oxide materials, and increasing doping profile of fin reduces short channel effects. Short Channel Effects like Subthreshold slope, Transconductance, drain induced barrier lowering were analyzed and compared with various designs. Simulation results demonstrate the benefit of 7nm GAAFET over 7nm FinFET. [ABSTRACT FROM AUTHOR]

Silicon based semiconductor technology has gained a lot of attention in electronics industries for decades. Nowadays it has almost reached an end, further scaling may cause critical issues such as short channel effects, leakage due to tunneling, high field effects etc., which are not under the control of the designers. Carbon Nanotube is found to be a better alternative to silicon as channel in nano range FETs. In this paper the process parameters affecting the drain current of both planar and coaxial type CNTFETs are identified. The device performance matrices such as transconductance(gm), drain resistance (rd) and gain corresponding to ± 5% variation of the parameters is analyzed and the device which shows better performance on scaling is identified. Coaxial CNTFET offer better performance for further scaling as it offers better gate control due to its gate all around geometry. Finally, modelled the drain current of coaxial CNTFET as a function of individual process parameter. The percentage variation of the modelled and simulated results are calculated, and it is found to be less than±1%. This model can be useful in predicting drain current of the device for different process parameters during the fabrication process. [ABSTRACT FROM AUTHOR]

A theoretical model to study the optical sensitivity of a metal-semiconductor field effect transistor has been proposed for a relatively high drain field. An analytical expression of drain current of the device has been derived for a MESFET under optical illumination considering field dependent mobility of electrons across the channel. The variation of drain current with and without optical illumination has been studied with drain and gate voltages. The optical sensitivity of the drain current has been studied for different biasing conditions and gate lengths. In addition, the shift in threshold voltage of a MESFET under optical illumination is determined and optical sensitivity of the device in terms of its threshold voltage has been studied. [ABSTRACT FROM AUTHOR]

This project presents a new method to fabricate porous Si using two-step Alternating Current Photo-Assisted Electrochemical Etching (ACPEC) technique. The n-type Si (111) was initially etched for a short time to form high density of etch pits and subsequently the sample was anodized in HF solution by using alternating current photo-assisted electrochemical etching (ACPEC) technique. The study aims to investigate the effect of different etching duration on the properties of porous Si. This new method of porous Si fabrication produced higher density, porosity and more uniform distribution of triangular-like pores compared to the sample etched without the initial etching. We observed that the pore size, porosity and average surface roughness were increased with etching duration. Amongst the samples, the 10 minutes of etched sample showed the maximum pore diameter and porosity. Subsequently, metal-semiconductor-metal (MSM) photodetector have been fabricated by depositing Al metal contacts on the non-porous and all porous samples for comparative study. The effectiveness of porous structure on Si towards the electrical characteristic and the performance of the MSM photodetector have been investigated. All the porous Si-based MSM photodetectors showed higher gain compared to the non-porous sample. The finding showed that, the porous based photodetector has better photoresponse compared to the non-porous photodetector.. [ABSTRACT FROM AUTHOR]

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates. [ABSTRACT FROM AUTHOR]

In this paper, a new deep submicron double-gate (DG) GaN-MESFET structure and its 2-D numerical model have been proposed, investigated and expected to suppress the short- channel-effects (SCEs) and improve the subthreshold behavior for deep submicron GaN-MESFET-based applications. The models have been used to predict and compare the performances of downscaled DG and conventional GaN-MESFETs, where the comparison of device architectures shows that the proposed DG GaN-Based MESFET exhibits a superior performance with respect to the conventional MESFET both in terms of threshold voltage and DIBL (Drain Induced Barrier Lowering) effect in deep submicron domain. The obtained results make (DG) GaN-MESFET a promising candidate for future MESFET-based circuits. [ABSTRACT FROM AUTHOR]

We have demonstrated a method to improve the dark current response of monocrystalline N-Si<100>metal-semiconductor-metal (MSM) photodetector. The combination of chemical and cryogenic treatment (77 K) have been proven to successfully reducing dark current response in a silicon based MSM photodetector. The combination of treatment with a different chemical solution (RCA, HF & SPM) was investigated. The surface roughness of the samples obtained using AFM technique showed that treated Si sample has better surface uniformity than untreated sample. The XRD results showed that the treated sample has increased intensity compared to those of untreated samples. [ABSTRACT FROM AUTHOR]

In the paper results of low frequency noise measurements were presented. The investigations were carried out on SiC MESFET transistors type CRF24010. The system for low frequency noise measurements was constructed, equivalent noise circuit for MESFET was elaborated. From the results of noise measurement it was found that the dominant noise is the flicker noise of the drain current. [ABSTRACT FROM AUTHOR]

A family of current-voltage (I-V) characteristics and 1/f voltage (source - drain) noise spectra of prototypes of submicron planar GaAs FETs with Schottky flat gate was investigated in linear region. The model of I-V characteristic was suggested. FET channel was described by Shockley model; the crowding of current in passive regions was taken into account as well. Analysis of measured set of I-V characteristics allowed us to define geometrical and electrical parameters of devices more precisely. Effects of natural ageing were found from the measurements made after manufacturing of prototypes (in 2002), and three years later (in 2005). Suggestion on the presence of excess defects in a structure which, as seemed, are presented by dipoles (donor-acceptor pairs) was made; their concentration was estimated and essential decrease of this concentration with the course of time was detected. In order to analyze the 1/f noise the hypothesis of existence of bistable point defects was used. It was supposed that these defects result in specific resistance fluctuations of conducting regions. It was shown that defects from the channel made the main contribution to the 1/f noise; concentration of these defects also was decreased. Experimental data obtained allow us to suppose that the observed 1/f noise is caused by dipoles revealed from analysis of I-V characteristics of FETs. Our results support the δμ model for 1/f noise in GaAs devices. © 2007 American Institute of Physics [ABSTRACT FROM AUTHOR]

Steady-state characteristics and low-frequency noise spectra of SiC-based metal-semiconductor field-effect transistors (MESFETs) before and after small doses (1×106 rad) of gamma radiation treatment are studied. The structural ordering of non-controllable impurities with radiation leads to an increase in threshold voltage, decrease of the channel’s resistance and reduces the number of G-R components observed in the total noise spectra of the devices. © 2005 American Institute of Physics [ABSTRACT FROM AUTHOR]

We propose that in nanotube field effect transistors (FETs) with small effective dielectric thickness the vertical potential drop across the nanotube diameter at finite gate bias can lower or eliminate the Schottky barrier at the electrode. This effect is demonstrated in single-walled carbon nanotube FETs fabricated on top of ultra-high-κ dielectric constant SrTiO3/Si substrates. These FETs show transconductances normalized by channel width of 8900 S/m, one of the highest values to date. This transconductance cannot be explained within the conventional FET or Schottky-barrier models. © 2004 American Institute of Physics [ABSTRACT FROM AUTHOR]

Three basic tune measurement methods are employed in RHIC; kicked beam, Schottky, and phase-locked loop. The kicked beam and 2GHz Schottky systems have been in operation since the first commissioning of circulating beam in RHIC in 1999. Preliminary PLL measurements utilizing a commercial off-the-shelf lockin amplifier were completed during that run, and the resonant BPM used in that system also delivered 230MHz Schottky spectra. With encouraging preliminary results and the thought of tune feedback in mind, a PLL tune system was implemented in the FPGA/DSP environment of the RHIC BPM system for the RHIC 2001 run. During that run this system functioned at the level of the present state-of-the-art in tune measurement accuracy and resolution, and was successfully incorporated into a tune feedback system for use during acceleration. Each of the tune measurement systems has particular strengths and weaknesses. We present specific and comparative details of systems design and operation. In addition, we present detailed tune measurements and their utilization in the measurement of chromaticity and the implementation of tune feedback. Finally, we discuss planned upgrades for the RHIC 2003 run. [ABSTRACT FROM AUTHOR]

The paper presents the comparative study of MESFET as photodetector for three different channel materials: Si, Ge and GaAs using ATLAS 3D device simulator. Common semi-insulating substrate i.e. sapphire is used for all the three MESFETs. Effect of illumination on the performance of the device has been studied in detail in terms of ratio of dark current to current under illumination, threshold voltage shift and enhanced drain current. [ABSTRACT FROM AUTHOR]

FET linearity is dictated by electric field distribution along the channel. Field profile shaping is known to improve device linearity. We study the effect of field tailoring in 5µm long 4H SiC with two 0.5µm long gates. The gates were biased in a manner that Vg1>Vg2. We demonstrate that proper ratio of voltages Vg1 /Vg2 reduce the strength of electric field along the channel, thus making transconductance more uniform. In field tailored MESFET the gm is about 21mS/mm with sharp pinch-off and good saturation characteristics in comparison to conventional single gate device. Shaping of electrical field increased the breakdown by 100%, with minimal effect on high frequency performance. [ABSTRACT FROM AUTHOR]

Short channel GaAs Metal Semiconductor Field Effect Transistors (MESFETs) have been fabricated with gate length to 20 nm, in order to examine the characteristics of sub-50 nm MESFET scaling. Here the rise in the measured transconductance is mainly attributed to electron velocity overshoot. For gate lengths below 40 nm, however, the transconductance drops suddenly. The behavior of velocity overshoot and its degradation is investigated and simulated by using a transport model based on the retarded Langevin equation (RLE). This indicates the existence of a minimum acceleration length needed for the carriers to reach the overshoot velocity. The argument shows that the source resistance must be included as an internal element, or appropriate boundary condition, of relative importance in any model where the gate length is comparable to the inelastic mean free path of the carriers. [ABSTRACT FROM AUTHOR]

ZnO metal-insulator-semiconductor(MIS) and metal-semiconductor(MES) field effect transistors with very low leakage gate currents in the range of picoampere were fabricated by pulsed-laser deposition to study the influence of interface scattering on the lateral electronic transport. Channel mobilities were increased by successive elimination of electron-scattering mechanisms by means of different ZnO transistor types: heteroepitaxial MISFET, MESFET and high-electron-mobility transistor (HEMT) on a-sapphire substrate as well as homoepitaxial MESFET on ZnO substrate. [ABSTRACT FROM AUTHOR]

Detailed characterization of the electron mobility along the channel reveals that average mobility can be improved and the performance of both MESFET and HEMT could be optimized. A detailed electric field profile of the devices was modeled using commercially available Silvaco™ software. Measurements of I–V characteristics of transistors together with modeled field profile allowed to generate maps of carrier mobility along the channel of studied devices. Manufacturing of two and three-gate transistors provided additional degree of freedom to tailor electrical field in both multi-gate MESFETs and HEMTs. Experimental optimization of transistor performance is presented. © 2005 American Institute of Physics [ABSTRACT FROM AUTHOR]