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The optimized derivative fast Fourier transform (dFFT) simultaneously increases resolution and reduces noise in spectra reconstructed from encoded time signals. The pertinent applications have recently been published for time signals encoded with and without water suppression by in vitro and in vivo magnetic resonance spectroscopy (MRS). Even with the employed lower derivative orders, genuine resonances were narrowed, their intensities enhanced and the background baselines flattened. This unequivocally separated many overlapped peaks that are the thorniest problem in data analysis by signal processing. However, it has been common knowledge that higher-order derivative spectra quickly deteriorate with the increased derivative order. The optimized dFFT can challenge such findings. An unprecedented resilience of this processor to derivative-induced distortions is presently demonstrated for high derivative orders (up to 20). The salient illustrations are given for the water residual, lactate quartet and lactate doublet alongside their close surroundings. These applications of diagnostic relevance for patients with cancer are reported for time signals encoded with water suppression by in vitro proton MRS of human ovary. [ABSTRACT FROM AUTHOR]

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application. [ABSTRACT FROM AUTHOR]

Summary Nanopore ion channels are a promising solution for certain molecular structure analyses. Large arrays of nanopore channels and their associated readout circuits are used in many molecular studies such as DNA sequencing. Readout circuits must meet challenging performance criteria such as low noise operation, low power consumption, in‐channel digitization capability, and high linearity. Previously, sigma–delta modulators have been presented to address these criteria; however, their specifications show drifts with temperature. In this paper, an approach is presented to keep modulator performance constant with temperature variations. For this purpose, the sigma–delta modulator's feedforward and feedback branches are modified so that their gain coefficient remains constant over a certain temperature range. With large sensors arrays, solutions employing high bias currents in the feedback paths are not suitable due to power consumption limitations. Here, the design gives the possibility of switching low current levels in the feedback paths without affecting the ENOB. The proposed temperature compensation solution shows good performance when temperature is swept from 27°C to 100°C. Over the mentioned temperature range, the gain and bandwidth of the modulator show a change of less than 0.4%. It is further shown that for a 10 kHz input current signal with an amplitude of 600 pA, the ENOB and power consumption are 12.9 and 4.6 mW, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design's novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 μ W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/ (H z) at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition. [ABSTRACT FROM AUTHOR]

We study single-voxel in vivo proton magnetic resonance spectroscopy (MRS) of white matter in the brain of a 25 year old healthy male volunteer. The free induction decay (FID) data of short length (0.5KB) are encoded at a long echo time (272 ms) with and without water suppression at a clinical scanner of a weak magnetic field (1.5T). For these FIDs, the fast Fourier transform (FFT) gives sparse, rough and metabolically uninformative spectra. In such spectra, resolution and signal to noise ratio (SNR) are poor. Exponential or Gaussian filters applied to the FIDs can improve SNR in the FFT spectra, but only at the expense of the worsened resolution. This impacts adversely on in vivo MRS for which both resolution and SNR of spectra need to be very good or excellent, without necessarily resorting to stronger magnetic fields. Such a long sought goal is at last within reach by means of the optimized derivative fast Fourier transform (dFFT), which dramatically outperforms the FFT in every facet of signal estimations. The optimized dFFT simultaneously improves resolution and SNR in derivative spectra. They are presently shown to be of comparably high quality irrespective of whether water is suppressed or not in the course of FID encodings. The ensuing benefits of utmost relevance in the clinic include a substantial shortening of the patient examination time. The implied significantly better cost-effectiveness should make in vivo MRS at low-field clinical scanners (1.5T) more affordable to ever larger circles of hospitals worldwide. [ABSTRACT FROM AUTHOR]

The paper presents a wide-bandwidth, low-polarization semiconductor optical amplifier (SOA) based on strained quantum wells. By enhancing the material gain of quantum wells for TM modes, we have extended the gain bandwidth of the SOA while reducing its polarization sensitivity. Through a combination of tilted waveguide design and cavity surface optical thin film design, we have effectively reduced the cavity surface reflectance of the SOA, thus decreasing device transmission losses and noise figure. At a wavelength of 1550 nm and a drive current of 1.4 A, the output power can reach 188 mW, with a small signal gain of 36.4 dB and a 3 dB gain bandwidth of 128 nm. The linewidth broadening is only 1.032 times. The polarization-dependent gain of the SOA is below 1.4 dB, and the noise figure is below 5.5 dB. The device employs only I-line lithography technology, offering simple fabrication processes and low costs yet delivering outstanding and stable performance. The designed SOA achieves wide gain bandwidth, high gain, low polarization sensitivity, low linewidth broadening, and low noise, promising significant applications in the wide-bandwidth optical communication field across the S + C + L bands. [ABSTRACT FROM AUTHOR]

We demonstrate a low-power (Pdc) 25.5–30.7 GHz CMOS variable-gain amplifier (VGA). The VGA constitutes a common-source (CS) input stage (M1), followed by current-reused CS gain (M2) and output stages (M3). Transistors M1-M3 adopt the topology of B-to-D with RB, i.e., body terminal is connected to drain via a large resistance RB, for body self-forward-bias and floating (BSFBF). This leads to gain boosting and NF reduction of the VGA at the same Pdc due to larger transconductance gm (because of larger bias current) and smaller bias voltage, and effective suppression of the substrate leakage and noise. Simultaneous input and noise matching are achieved by suitable selection of the size and bias of M1, and the inductance of Lg1 and L1. Analog switch transistor M4 is in parallel with M3 to tune its overdrive (VOV) and drain-source voltage (VDS) for fine tuning of S21. Digital switch transistor M5 (in conjunction with the series coupling capacitance CC and resonant inductance L10) is in parallel with M2 to control its AC VDS for coarse tuning of S21. In the case of M5 being turned-on, the series of CC-M5-L10 is close to a short-circuit (~ 4.6 Ω) at the output node of M2 over the 3-dB gain bandwidth (f3dB) of 18.4–30.7 GHz. This leads to S21 tuning range boosting. Moreover, M4-M5 adopt DTMOS with RB, i.e., body of M4-M5 is connected to gate via RB, for BSFBF to lower the on-state channel resistance (Rch) and increase the off-state Rch. Further S21 tuning range boosting is attained. The VGA consumes 9 mW, and achieves S21 of 15.4 ± 1.5 dB for 18.4–30.7 GHz, tuning range of 29.8 dB (15.5 ~ − 14.3 dB) at 28 GHz, average NF (NFavg) of 2.79 dB for 18–31 GHz, and figure-of-merit (FOM) of 2.24 GHz. The NFavg and FOM are one of the best results ever reported for wideband VGAs/LNAs with Pdc lower than 10 mW. The eminent results of the VGA indicate it is suitable for 28 GHz 5G systems. [ABSTRACT FROM AUTHOR]

Summary: The present study is devoted to articulating a modified folded‐cascode circuit, to make folded‐cascode structures an attractive configuration as a transimpedance amplifier (TIA) for being employed in Giga‐bit per second optical communication receiver systems. Giga‐bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes folded cascodes comparable to the famous regulated cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5 Gbps up to 8 Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65 nm CMOS validate the suitability of the modified circuit as a TIA. [ABSTRACT FROM AUTHOR]

This article presents a low-noise amplifier based on the use of a composite right-left handed transmission line consisting of a single microstrip line and a split ring resonator at the transistor input and output. This design ensures optimum matching over a wide frequency range while eliminating an unwanted frequency band. The circuit is designed to operate at a center frequency of 2.4 GHz while simultaneously eliminating the frequency band around 4.8 GHz, meeting key performance criteria including improved gain, better stability, and significant noise reduction. To achieve these objectives, the transistor used undergoes precise biasing via a DC power supply. In this process, a specifically selected capacitor is arranged in series with a λ/4 transformer. This transformer, in turn, is connected in series to a radial line section. The dimensions of the proposed amplifier are 70 × 34 mm2.For validation purposes, the proposed method was implemented through design, manufacture, and testing. The results obtained show that the proposed low noise amplifier achieves a high gain of 15.27 dB, an input reflection loss S11 of −16.26 dB, an output reflection loss S22 of −13.94 dB, and an inverse isolation S12 of −22.82 dB at 2.4 GHz, with a resonance peak at 4.8 GHz allowing the surrounding frequency band to be eliminated with an attenuation of 77 dB at 4.8 GHz. What's more, the noise figure is kept below 2 dB, with unconditional stability in the desired frequency band.

Voltage standards are widely used to transfer volts from Josephson voltage standards (JVSs) at national metrology institutes (NMIs) into calibration labs to maintain the volts and to transfer them to test equipment at production lines. Therefore, commercial voltage standards based on Zener diodes are used. Analog Devices Inc. (San Jose, CA, USA), namely, Eric Modica, introduced the ADR1000KHZ, a successor to the legendary LTZ1000, at the Metrology Meeting 2021. The first production samples were already available prior to this event. In this article, this new temperature-stabilized Zener diode is compared to several others as per datasheet specifications. Motivated by the superior parameters, a 10 V transfer standard prototype for laboratory use with commercial off-the-shelf components such as resistor networks and chopper amplifiers was built. How much effort it takes to reach the given parameters was investigated. This paper describes how the reference was set up to operate it at its zero-temperature coefficient (z.t.c.) temperature and to lower the requirements for the oven stability. Furthermore, it is shown how the overall temperature coefficient (t.c.) of the circuit was reduced. For the buffered Zener voltage, a t.c. of almost zero, and with amplification to 10 V, a t.c. of

An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves - 10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 μ m 2 area. [ABSTRACT FROM AUTHOR]

The sensitivity and accuracy of nanopore sensors are severely hindered by the high noise associated with solid-state nanopores. To mitigate this issue, the deposition of organic polymer materials onto silicon nitride ( S i N x ) membranes has been effective in obtaining low-noise measurements. Nonetheless, the fabrication of nanopores sub-10 nm on thin polymer membranes remains a significant challenge. This work proposes a method for fabricating nanopores on polymethyl methacrylate (PMMA) membrane by the local high electrical field controlled breakdown, exploring the impact of voltage and current on the breakdown of PMMA membranes and discussing the mechanism underlying the breakdown voltage and current during the formation of nanopores. By improving the electric field application method, transient high electric fields that are one–seven times higher than the breakdown electric field can be utilized to fabricate nanopores. A comparative analysis was performed on the current noise levels of nanopores in PMMA- S i N x composite membranes and S i N x nanopores with a 5 nm diameter. The results demonstrated that the fast fabrication of nanopores on PMMA- S i N x membranes exhibited reduced current noise compared to S i N x nanopores. This finding provides evidence supporting the feasibility of utilizing this technology for efficiently fabricating low-noise nanopores on polymer composite membranes. [ABSTRACT FROM AUTHOR]

Measurement of lightning current plays a critical role in the field of atmospheric electricity. Traditionally, Rogowski coils or low-resistance shunts were employed for measuring lightning currents in the range from several amperes up to several hundreds of kilo-amperes, and high-value resistors were utilized for measuring corona discharge currents at sub-ampere levels. However, these approaches were not suitable for continuously recording the vast range of lightning currents. For this sake, we have developed a lightning current measurement system equipped with a shock-tolerant low-noise amplifier module. With the system installed on a tall tower, sub-ampere level currents just before the lightning initiation were observed for the first time. To confirm the authenticity of the recorded currents, the background noise of the measurement system and surrounding environment were identified, and a digital multi-frequency notch filter was proposed for de-noising. Results show that the system can achieve a current identification level of 50 mA even in complex electromagnetic environments, while having a measurement capability of 220 kA. [ABSTRACT FROM AUTHOR]

Copyright of Transportation Science & Technolgy is the property of Transportation Science & Technology Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm. [ABSTRACT FROM AUTHOR]

Voltage standards are widely used to transfer volts from Josephson voltage standards (JVSs) at national metrology institutes (NMIs) into calibration labs to maintain the volts and to transfer them to test equipment at production lines. Therefore, commercial voltage standards based on Zener diodes are used. Analog Devices Inc. (San Jose, CA, USA), namely, Eric Modica, introduced the ADR1000KHZ, a successor to the legendary LTZ1000, at the Metrology Meeting 2021. The first production samples were already available prior to this event. In this article, this new temperature-stabilized Zener diode is compared to several others as per datasheet specifications. Motivated by the superior parameters, a 10 V transfer standard prototype for laboratory use with commercial off-the-shelf components such as resistor networks and chopper amplifiers was built. How much effort it takes to reach the given parameters was investigated. This paper describes how the reference was set up to operate it at its zero-temperature coefficient (z.t.c.) temperature and to lower the requirements for the oven stability. Furthermore, it is shown how the overall temperature coefficient (t.c.) of the circuit was reduced. For the buffered Zener voltage, a t.c. of almost zero, and with amplification to 10 V, a t.c. of <0.01 µV/V/K was achieved in a temperature span of 15 to 31 °C. For the buffered Zener voltage, a noise of ~584 nVp-p and for the 10 V output, ~805 nVp-p were obtained. Finally, 850 days of drift data were taken by comparing the transfer standard prototype to two Fluke 7000 voltage standards according to the method described in NBS Technical Note 430. The drift specification was, however, not met. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 n V / H z @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 (( µ V / H z )·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications. [ABSTRACT FROM AUTHOR]

A low-noise Low Dropout Regulator (LDO) is designed in a Semiconductor Manufacturing International Corporation (SMIC) $0.18~\mu $ m process, aiming at supply of a clean and constant clamping voltage in the operation of Correlated Double Sampling (CDS) for elimination of switching and reset noise in CMOS Pixel Sensors (CPS) applied to high energy physics experiments. In order to decrease noise of the LDO, a noise model of the LDO consisting of blocks, such as a pass transistor, a resistor network, and an error amplifier, is constructed and noise contributions made by these blocks are analyzed in detail. According to results of the noise analysis, the error amplifier is identified as the major noise source. For the purpose of reduction in noise, especially 1/f noise, an error amplifier exploiting a chopper stabilization technique is proposed. Simulation results demonstrate the effectiveness of the proposed method. The Power Spectral Density (PSD) of the LDO’s output noise is only 60 nV/ $\surd $ Hz at 10 Hz and total integrated noise within the bandwidth is $40~\mu $ V.

This paper presents a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in a low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain-driven input stage topology in conjunction with a low-voltage attenuator to permit operation at a low voltage, and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, this four-stage amplifier can achieve 84.59 dB in gain, 161.00 kHz in unity-gain bandwidth, 96 deg in phase margin, and 5.7 dB in gain margin whilst offering an input-referred noise of 213.63 nV/Hz @1 kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth-based FoMnpb of 1.15 × 10−6 ((µV/Hz)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metrics in terms of noise, power, and bandwidth at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.

A split-voltage amplifier architecture is proposed which improves the power efficiency compared to a conventional implementation. The approach is verified with a prototype fabricated in 0.35 µm CMOS technology using lateral bipolar input transistors. It achieves a measured DC gain of 105 V/V, a differential AC gain of 40.3 dB with a bandwidth of 55 kHz, a CMRR of approximately 75 dB, and a PSRR of 55 dB. The input-referred noise is 7 nV/√Hz and 923 nVrms integrated from 100 Hz to 10 kHz, resulting in a Noise Efficiency Factor (NEF) of 2.84 and a Power Efficiency Factor (PEF) of 18.3. The split-voltage configuration improves power efficiency by nearly 25% compared to a full voltage supply and maintains a small area design. Action potentials of the medial and lateral giant fiber of an earthworm are recorded as an example application.

A high conversion gain, low noise up-conversion mixer for 5G New Radio band (850 MHz) Internet of Thing (IoT) applications implemented in UMC 0.18 μm standard CMOS technology is presented. The proposed mixer is based on the Flipped voltage follower current mirror with a passive switching circuit. The proposed up-conversion mixer achieves a noise figure (NF) of 4.4 dB, maximum Conversion Gain (CG) of 33.85 dB, maximum input third-order intercept point (IIP3) of 33.16 dBm, and output third-order intercept point (OIP3) of 11.89 dBm. It has a total power consumption of 23.58 mW with a 1.2 V supply voltage. The overall chip area of the design is 26.5 µm × 54.9 µm. [ABSTRACT FROM AUTHOR]

Abstarct: In this work, a new Charge Pump (CP) design including a Phase and Frequency Detector (PFD) is presented. The PFD is designed using the common topology of two D Flip Flops, AND gates and a controllable reset delay for the DFFs to compensate for process and tem-perature variations. The Charge Pump is using a bias cell which generates the necessary bias voltages, the clock driving cells which convert the single-ended UP and DOWN signals to differential and the core cell which comprises of six slices, each one contributing the same amount of current to the low pass filter. The output current is programmable with minimum and maximum values of 25 uA and 150 uA respectively. An extra option to double the output current is also added. A new technique has been adopted in terms of layout floorplan of the charge pump slices to eliminate the clock feedthrough mismatch between the differential UP and DOWN sig-nals. The technology used in this work is TSMC 65nm, while the supply voltage is 1 V. The main characteristics of the proposed design are modularity, low power, low noise, great linearity, small area, simplicity and performance. [ABSTRACT FROM AUTHOR]

A capacitance-to-voltage converter (CVC) is proposed in this paper and applied to a readout circuit for a micro-electro-mechanical system (MEMS) accelerometer to improve the power efficiency. In a traditional readout circuit, the front-end CVC has to operate at a high sampling frequency to resist thermal noise deterioration due to the large parasitic capacitance introduced by the mechanical sensing element. Thus, the back-end analog-to-digital converter (ADC) also has to operate at a high sampling frequency to avoid noise aliasing when sampling the output signal of the CVC, which leads to high power consumption. The average CVC technique is proposed in this paper to reduce the sampling frequency requirement of the back-end ADC and thus reduce the power consumption. Both the traditional readout circuit and the proposed readout circuit are simulated with a commercial 0.18 μm BCD process. The simulation results show that noise aliasing occurs, and the noise power spectral density (PSD) of the traditional readout circuit increases by 12 dB when the sampling frequency of back-end ADC is reduced by 24 dB. However, in the proposed readout circuit, a noise aliasing effect does not occur. Moreover, the proposed readout circuit reduces the power consumption by 53% without thermal noise deterioration. In addition, the proposed CVC circuits are fabricated in an 0.18 μm BCD process, and the test results show that the presented readout circuit based on the average CVC technique can obtain better performance than the traditional CVC-based readout circuit. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The 1550 nm band semiconductor optical amplifier (SOA) has great potential for applications such as optical communication. Its wide-gain bandwidth is helpful in expanding the bandwidth resources of optical communication, thereby increasing total capacity transmitted over the fiber. Its relatively low cost and ease of integration also make it a high-performance amplifier of choice for LiDAR applications. In recent years, with the rapid development of quantum-well (QW) material systems, SOAs have gradually overcome the shortcomings of polarization sensitivity and high noise. The research on quantum-dot (QD) materials has further improved the noise characteristics and transmission loss of SOAs. The design of special waveguide structures—such as plate-coupled optical waveguide amplifiers and tapered amplifiers—has also increased the saturation output power of SOAs. The maximum gain of the SOA has been reported to be more than 21 dB. The maximum saturation output power has been reported to be more than 34.7 dBm. The maximum 3 dB gain bandwidth has been reported to be more than 120 nm, the lowest noise figure has been reported to be less than 4 dB, and the lowest polarization-dependent gain has been reported to be 0.1 dB. This study focuses on the improvement and enhancement of the main performance parameters of high-power SOAs in the 1550 nm band and introduces the performance parameters, the research progress of high-power SOAs in the 1550 nm band, and the development and application status of SOAs. Finally, the development trends and prospects of high-power SOAs in the 1550 nm band are summarized. [ABSTRACT FROM AUTHOR]

An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a two-stage operation for reduced kickback noise. It also incorporates the adaptive current reuse (ACR) technique for reduced latency and high-speed operation. The proposed comparator is designed and simulated in a 65-nm UMC CMOS process using a 1.2-V power supply. The performance of the design is verified using post-layout simulation and also through Monte Carlo simulations. The resultant offset standard deviation of 8 mV is observed, which is 3 times less compared to the conventional design. The maximum operating frequency of the comparator is 1 GHz. The worst-case energy consumption is 67 fJ with an average latency of 70 ps. The kickback noise of 5.5 mV is observed for the entire working range, which is almost 10 times less compared to the conventional dynamic comparator at 500 MHz clock frequency. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The monitoring of microvolt‐level biosignals such as electroencephalograms requires the application of low‐noise signal amplifier circuits, which, for single‐use cases, must be fabricated for disposability using low‐cost manufacturing techniques. One promising solution for the production of low‐cost amplifier circuits for digital biosensing is the emerging technology of low‐noise printed circuits. Here, a low‐noise‐electrode printing process for organic transistors that can carry out precision measurement of brain activity using a low‐noise organic amplifier is proposed. In the transistor fabrication process, Ag electrodes are processed via flat stamp parallel printing, and fine‐process optimization to minimize the charge‐trapping effect enables a three‐order reduction in transistor noise. The low‐noise transistors are used to produce an organic pseudo‐complementary metal‐oxide‐semiconductor amplifier with a small noise level of 2.2 µVp‐p at 10 Hz, which enables precision brain wave monitoring in a close correlation with signals obtained using a commercialized measurement system. [ABSTRACT FROM AUTHOR]

The paper presents a wide-bandwidth, low-polarization semiconductor optical amplifier (SOA) based on strained quantum wells. By enhancing the material gain of quantum wells for TM modes, we have extended the gain bandwidth of the SOA while reducing its polarization sensitivity. Through a combination of tilted waveguide design and cavity surface optical thin film design, we have effectively reduced the cavity surface reflectance of the SOA, thus decreasing device transmission losses and noise figure. At a wavelength of 1550 nm and a drive current of 1.4 A, the output power can reach 188 mW, with a small signal gain of 36.4 dB and a 3 dB gain bandwidth of 128 nm. The linewidth broadening is only 1.032 times. The polarization-dependent gain of the SOA is below 1.4 dB, and the noise figure is below 5.5 dB. The device employs only I-line lithography technology, offering simple fabrication processes and low costs yet delivering outstanding and stable performance. The designed SOA achieves wide gain bandwidth, high gain, low polarization sensitivity, low linewidth broadening, and low noise, promising significant applications in the wide-bandwidth optical communication field across the S + C + L bands.

Measurement of lightning current plays a critical role in the field of atmospheric electricity. Traditionally, Rogowski coils or low-resistance shunts were employed for measuring lightning currents in the range from several amperes up to several hundreds of kilo-amperes, and high-value resistors were utilized for measuring corona discharge currents at sub-ampere levels. However, these approaches were not suitable for continuously recording the vast range of lightning currents. For this sake, we have developed a lightning current measurement system equipped with a shock-tolerant low-noise amplifier module. With the system installed on a tall tower, sub-ampere level currents just before the lightning initiation were observed for the first time. To confirm the authenticity of the recorded currents, the background noise of the measurement system and surrounding environment were identified, and a digital multi-frequency notch filter was proposed for de-noising. Results show that the system can achieve a current identification level of 50 mA even in complex electromagnetic environments, while having a measurement capability of 220 kA.

The sensitivity and accuracy of nanopore sensors are severely hindered by the high noise associated with solid-state nanopores. To mitigate this issue, the deposition of organic polymer materials onto silicon nitride (SiNx) membranes has been effective in obtaining low-noise measurements. Nonetheless, the fabrication of nanopores sub-10 nm on thin polymer membranes remains a significant challenge. This work proposes a method for fabricating nanopores on polymethyl methacrylate (PMMA) membrane by the local high electrical field controlled breakdown, exploring the impact of voltage and current on the breakdown of PMMA membranes and discussing the mechanism underlying the breakdown voltage and current during the formation of nanopores. By improving the electric field application method, transient high electric fields that are one–seven times higher than the breakdown electric field can be utilized to fabricate nanopores. A comparative analysis was performed on the current noise levels of nanopores in PMMA-SiNx composite membranes and SiNx nanopores with a 5 nm diameter. The results demonstrated that the fast fabrication of nanopores on PMMA-SiNx membranes exhibited reduced current noise compared to SiNx nanopores. This finding provides evidence supporting the feasibility of utilizing this technology for efficiently fabricating low-noise nanopores on polymer composite membranes.

The seafloor E-field signal is extremely weak and difficult to measured, even with a high signal-to-noise ratio. The preamplifier for electrodes is a key technology for ocean-bottom electromagnetic receivers. In this study, a chopper amplifier was proposed and developed to measure the seafloor E-field signal in the nanovolt to millivolt range at significantly low frequencies. It included a modulator, transformer, AC amplifier, high-impedance (hi-Z) module, demodulator, low-pass filter, and chopper clock generator. The injected charge in complementary metal-oxide semiconductor (CMOS) switches that form the modulator is the main source of 1/f noise. Combined with the principles of peak filtering and dead bands, a hi-Z module was designed to effectively reduce low-frequency noise. The chopper amplifier achieved an ultralow voltage noise of 0.6 nV/rt (Hz) at 1 Hz and 1.2 nV/rt (Hz) at 0.001 Hz. The corner frequency was less than 100 mHz, and there were few 1/f noises in the effective observation frequency band used for detecting electric fields. Each component is described with relevant tradeoffs that realize low noise in the low-frequency range. The amplifier was compact, measuring Ø 68 mm × H 12 mm, and had a low power consumption of approximately 23 mW (two channels). The fixed gain was 1500 with an input voltage range of 2.7 mVPP. The chopper amplifiers demonstrated stable performance in offshore geophysical prospecting applications.

Resonant Inelastic X-ray Scattering (RIXS) is a powerful spectroscopic technique to study quantum properties of materials in the bulk. A novel variant of RIXS, called 2D RIXS, enables concurrent measurement of the scattered X-ray spectrum for a wide range of input energies, improving on the typically low throughput of 1D RIXS. In the soft X-ray domain, 2D RIXS demands an X-ray camera system with small pixels, large area, high quantum efficiency and low noise to limit the false detection rate in long duration exposures. We designed and implemented a 7.5 Megapixel back-illuminated CMOS detector with 5 μm pixels and high quantum efficiency in the 200–1,000 eV X-ray energy range for the QERLIN 2D RIXS spectrometer at the Advanced Light Source. The QERLIN beamline and detector are currently in commissioning. The camera noise from in-situ 3 s long dark exposures is 7e− or less and the leakage current is 6.5 × 10−3 e−/(pixel ∙ s). For individual 500 eV X-rays, the expected efficiency is greater than 75% and the false detection rate is ∼1 × 10−5 per pixel.

Abstract The monitoring of microvolt‐level biosignals such as electroencephalograms requires the application of low‐noise signal amplifier circuits, which, for single‐use cases, must be fabricated for disposability using low‐cost manufacturing techniques. One promising solution for the production of low‐cost amplifier circuits for digital biosensing is the emerging technology of low‐noise printed circuits. Here, a low‐noise‐electrode printing process for organic transistors that can carry out precision measurement of brain activity using a low‐noise organic amplifier is proposed. In the transistor fabrication process, Ag electrodes are processed via flat stamp parallel printing, and fine‐process optimization to minimize the charge‐trapping effect enables a three‐order reduction in transistor noise. The low‐noise transistors are used to produce an organic pseudo‐complementary metal‐oxide‐semiconductor amplifier with a small noise level of 2.2 µVp‐p at 10 Hz, which enables precision brain wave monitoring in a close correlation with signals obtained using a commercialized measurement system.

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This paper presents a novel ultra-high speed, high conversion-gain, low noise CMOS image sensor (CIS) based on charge-sweep transfer gates implemented in a standard 180 nm CIS process. Through the optimization of the photodiode geometry and the utilization of charge-sweep transfer gates, the proposed pixels achieve a charge transfer time of less than 10 ns without requiring any process modifications. Moreover, the gate structure significantly reduces the floating diffusion capacitance, resulting in an increased conversion gain of 183 µV/e−. This advancement enables the image sensor to achieve the lowest reported noise of 5.1 e− rms. To demonstrate the effectiveness of both optimizations, a proof-of-concept CMOS image sensor is designed, taped-out and characterized. [ABSTRACT FROM AUTHOR]

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results. [ABSTRACT FROM AUTHOR]

As an effective capacitance signal produced by a micro-hemisphere gyro is usually below the pF level, and the capacitance reading process is susceptible to parasitic capacitance and environmental noise, it is highly difficult to acquire an effective capacitance signal. Reducing and suppressing noise in the gyro capacitance detection circuit is a key means to improve the performance of detecting the weak capacitance generated by MEMS gyros. In this paper, we propose a novel capacitance detection circuit, where three different means are utilized to achieve noise reduction. Firstly, the input common-mode feedback is applied to the circuit to solve the input common-mode voltage drift caused by both parasitic capacitance and gain capacitance. Secondly, a low-noise, high-gain amplifier is used to reduce the equivalent input noise. Thirdly, the modulator–demodulator and filter are introduced to the proposed circuit to effectively mitigate the side effects of noise; thus, the accuracy of capacitance detection can be further improved. The experimental results show that with the input voltage of 6 V, the newly designed circuit produces an output dynamic range of 102 dB and the output voltage noise of 5.69 nV/√Hz, achieving a sensitivity of 12.53 V/pF. [ABSTRACT FROM AUTHOR]

The seafloor vector magnetometer is an effective tool for marine geomagnetic surveys and seafloor magnetotelluric (MT) detection. However, the noise, power consumption, cost, and volume characteristics of existing seafloor vector magnetometers are insufficient for practical use. Therefore, a low-noise, low-power-consumption seafloor vector magnetometer that can be used for data acquisition of deep-ocean geomagnetic vector components is developed and presented. A seafloor vector magnetometer mainly consists of a fluxgate sensor, data acquisition module, acoustic release module, glass sphere, frame, burn-wire release, and anchor. A new low-noise data acquisition module and a fluxgate sensor greatly reduce power consumption. Furthermore, compact size is achieved by integrating an acoustic telemetry module and replacing the acoustic release with an external burn-wire release. The new design and magnetometer characteristics reduce the volume of the instrument and the cost of hardware considerably, thereby improving the integrity and deployment efficiency of the equipment. Theoretically, it can operate for 90 days underwater at a maximum depth of 6 000 m. The seafloor vector magnetometer was tested in the South China Sea and the Philippine Sea and obtained high-quality geomagnetic data. The deep-water environment facilitates magnetic field data measurements, and the magnetometer has an approximate noise level of 10 pT/rt (Hz)@1 Hz, a peak-to-peak value error of 0.2 nT, and approximate power consumption of 200 mW. The fluxgate sensor can measure the magnetic field in the lower frequency band and realize geomagnetic field measurements over prolonged periods. [ABSTRACT FROM AUTHOR]

Owing to its suitable electronic bandgap, excellent air stability, and high carrier mobility at room temperature, low‐dimensional bismuth oxyselenide (Bi2O2Se) has become attractive in the context of visible–near‐infrared (VIS–NIR) detection. However, the high carrier concentration and bolometric effect of Bi2O2Se nanosheets are not conducive to reducing the dark current and improving the response speed, which hinders Bi2O2Se nanosheet‐based photodetectors from achieving an optimal performance. In this study, a Bi2O2Se nanoribbon is controllably synthesized on a fluorophlogopite substrate by means of the chemical vapor deposition approach. Through the use of a Bi2O2Se nanoribbon structure and the application of a Schottky barrier between the Bi2O2Se and Au electrodes, a fast response and low noise photodetector is achieved. More specifically, the response times are 2.1 and 313 µs at 650 and 1550 nm, respectively, and the corresponding optimal detectivities are 3.28 × 1013 and 8.07 × 109 Jones. Furthermore, the device reaches a −3 dB bandwidth of 81 kHz and exhibits a responsivity of 3.2 × 105 A W−1 at 650 nm under a bias of 5 V. This study provides new opportunities for the application of high‐performance VIS–NIR photodetectors. [ABSTRACT FROM AUTHOR]

This article presents a microelectromechanical system (MEMS) Coriolis-based mass-flow-to-digital converter ($\Phi $ DC) that can be used with both liquids and gases. It consists of a micromachined Coriolis mass flow sensor and a CMOS interface circuit that drives it into oscillation and digitizes the resulting mass flow information. A phase-locked loop (PLL) drives the sensor at its resonance frequency ($f_{D}$), while a low 1/ $f$ noise switched-capacitor (SC) proportional–integral (PI) controller maintains a constant drive amplitude. Mass flow through the sensor causes Coriolis-force-induced displacements, which are detected by co-integrated sense capacitors. In-phase (${I}$) and quadrature (${Q}$) components of these displacements are then digitized by two continuous-time delta–sigma modulators (CT- $\Delta \Sigma $ Ms) with finite impulse response (FIR)-DACs and passive mixers. Their outputs are used to accurately estimate and cancel sense path delay, thus improving sensor stability. To ensure constant sensitivity over a wide range of fluid densities, a background sensitivity tuning (BST) scheme adjusts the sense capacitors’ bias voltage as a function of $f_{D}$ , which is a good proxy for fluid density. Implemented in a standard 0.18- $\mu \text{m}$ CMOS technology, the interface circuit consumes 13 mW from a 1.8-V supply. The proposed MEMS Coriolis $\Phi $ DC achieves a state-of-the-art noise floor of 80 $\mu \text{g}$ /h/ $\sqrt {\text {Hz}}$ and a zero stability (ZS) of ±0.31 mg/h, which is at par with MEMS thermal flow sensors. [ABSTRACT FROM AUTHOR]

The observed data of transient electromagnetic (TEM) systems is often contaminated by various noises. Even after stacking averages or applying various denoising algorithms, the interference of the system noise floor cannot be eliminated fundamentally, which limits the survey capability and detection efficiency of TEM. To improve the noise performance of the TEM receiver, we have designed a low-noise amplifier using the current source long-tail differential structure and JFET IF3602 through analyzing the power spectrum characteristics of the TEM forward response. By the designed circuit structure, the JFET operating point is easy to set up. The adverse effect on the JFET differential structure by JFET performance differences is also weakened. After establishing the noise model and optimizing the parameters, the designed low-noise differential amplifier has a noise level of 0.60 nV / Hz , which increases the number of effective data 2.6 times compared with the LT1028 amplifier. [ABSTRACT FROM AUTHOR]

Abstract With the rapid growth of electric vehicles (EVs) in the past decade, many new traffic safety challenges are also emerging. With the crash data of Norway from 2011 to 2018, this study gives an overview of the status quo of EV crashes. In the survey period, the proportion of EV crashes in total traffic crashes had risen from zero to 3.11% in Norway. However, in terms of severity, EV crashes do not show statistically significant differences from the Internal Combustion Engine Vehicle (ICEV) crashes. Compared to ICEV crashes, the occurrence of EV crashes features on weekday peak hours, urban areas, roadway junctions, low-speed roadways, and good visibility scenarios, which can be attributed to the fact that EVs are mainly used for urban local commuting travels in Norway. Besides, EVs are confirmed to be much more likely to collide with cyclists and pedestrians, probably due to their low-noise engines. Then, the separate logistic regression models are built to identify important factors influencing the severity of ICEV and EV crashes, respectively. Many factors show very different effects on ICEV and EV crashes, which implies the necessity of re-evaluating many current traffic safety strategies in the face of the EV era. Although the Norway data is analyzed here, the findings are expected to provide new insights to other countries also in the process of the complete automotive electrification.

A high power supply rejection ratio (PSRR), low noise and low-power self-biased bandgap voltage reference (BGR) is presented in this paper. In response to the trade-off between power consumption and output noise, a feedback depth enhancement technique is proposed for mitigating the effect of the resistor on output noise and offset voltage. The PSRR is enhanced by a novel self regulating technology based on an improved flipped voltage follower (FVF). The designed BGR was verified under post-simulation for various process corners, voltages and temperatures (PVT). It was using 0. 18 μ m BiCMOS process, occupying an active area of 0.016 mm 2. The BGR operates normally at 3.0 V – 3.6 V with a quiescent current of 3.6 μ A. The best untrimmed TC is 22.04 ppm / ∘ C and the rms noise is only 2.47 μ V r m s from 0.1 Hz to 10 Hz. The PSRR is −184 dB@1 Hz and −50 dB@1 MHz when V I N = 3.0 V. [ABSTRACT FROM AUTHOR]

The next generation of Ring Imaging CHerenkov detectors in high energy physics experiments may use SiPMs as photon sensing elements. This upgrade is necessary to achieve greater detector granularity and speed, however SiPMs need to be cooled down to cryogenic temperatures to detect single photons in high-radiation environments and avoid being overwhelmed by the presence of "dark signals". It is therefore necessary to study and characterize SiPM models in dedicated campaigns, using a custom-built amplifying chain that can also operate in an extended temperature range, between 80 K and 300 K, for detector characterization purposes. The proposed amplifier configuration consists of two amplifying stages and achieves low jitter values (< 10 − 20 ps RMS ) thanks to the low electronic noise and the high amplifier bandwidth. The circuit achieves a signal bandwidth of 500 MHz < BW < 1 GHz , a phase margin of approximately 45° and a power consumption of about 65 − 135 mW. The amplifier prototype unit can be adjusted to cover the considered temperature range and still achieve low jitter values. [ABSTRACT FROM AUTHOR]

A capacitance-to-voltage converter (CVC) is proposed in this paper and applied to a readout circuit for a micro-electro-mechanical system (MEMS) accelerometer to improve the power efficiency. In a traditional readout circuit, the front-end CVC has to operate at a high sampling frequency to resist thermal noise deterioration due to the large parasitic capacitance introduced by the mechanical sensing element. Thus, the back-end analog-to-digital converter (ADC) also has to operate at a high sampling frequency to avoid noise aliasing when sampling the output signal of the CVC, which leads to high power consumption. The average CVC technique is proposed in this paper to reduce the sampling frequency requirement of the back-end ADC and thus reduce the power consumption. Both the traditional readout circuit and the proposed readout circuit are simulated with a commercial 0.18 μm BCD process. The simulation results show that noise aliasing occurs, and the noise power spectral density (PSD) of the traditional readout circuit increases by 12 dB when the sampling frequency of back-end ADC is reduced by 24 dB. However, in the proposed readout circuit, a noise aliasing effect does not occur. Moreover, the proposed readout circuit reduces the power consumption by 53% without thermal noise deterioration. In addition, the proposed CVC circuits are fabricated in an 0.18 μm BCD process, and the test results show that the presented readout circuit based on the average CVC technique can obtain better performance than the traditional CVC-based readout circuit.

The research of quantum noise in the interaction of laser and atoms plays a critical role in quantum optical experiments. The measurement of quantum noise is mainly based on the balanced homodyne detection method. Here, we reported a balanced homodyne detector with low noise, high gain, and high common-mode rejection ratio (CMRR) at the wavelength of 795 nm. By optimizing the selection of components and printed circuit board (PCB) layout, a minimum electronic noise of −96.7 dBm is obtained. Over the range of 1 MHz to 5 MHz, we get a flat CMRR above 59 dB and a linear gain regime, which can enable a shot noise measurement with the laser power of $100~\mu \text{w}$ . The developed detector can be used in quantum coherent experiments with a weak probe laser of power down to tens of microwatts.

The power consumption and the opto-electric noise of organic photo-detectors are the challenges for large-scale detecting and imaging applications to surpass. This article presents a new device concept of organic heterojunction PIN channel for photo-transistor. The presence of the channel's heterostructure enables rectifying capability and effective control of defect density, which leads to low power consumption (0.12 to 7.5 nW) and low dynamic noise (4.5 × 1013 Jones detectivity). Significantly, through adopting the highly efficient Perovskite Quantum Dots as intrinsic sensing core, the device exhibits high responsivity up to 7190 A/W. As we demonstrate a large-scale 10 × 20 imaging array with integrated photo-transistor, the output signals are read-out and rebuilt by I-V converting amplifier with analog-to-digital circuit and numerical computation method to visualize the functionality of the system.

Abstract This work introduces a new low‐noise current‐reused CMOS active inductor (AI) based on Gyrator‐C configuration. In the proposed AI, a simple common‐source amplifier is utilised for boosting effective Gm and improving noise performance of the AI. While the Gm‐boosting technique improves the noise performance as well as the quality factor of the inductor, a resistor is also added to the feedback path for more quality factor improvement. Rigorous analysis of the proposed circuit shows a significant noise performance and quality factor enhancement. In order to verify the concept and confirm the mathematical analysis, the AI is designed and simulated in a commercial 0.18 μm RF‐CMOS technology. The simulation results show that the proposed inductor operates in 1 to 7.2 GHz frequency range, has a 9 nH inductance at 2.864 GHz frequency and 650 μW total power dissipation at 1.8‐V supply voltage. Maximum quality factor of 90 is achieved at 2.864 GHz frequency and a quality factor greater than 40 is obtained from 2.4 to 3.3 GHz. The input‐referred current noise of the proposed inductor is as low as 22 pA/√Hz showing 30.5% improvement compared to the conventional AI. The proposed AI is also tunable and sweeping the tuning voltage results in changing extracted inductance from 4.35 to 15.2 nH with only a chip area of 0.003 mm2. Post‐layout and different Monte Carlo simulation results also confirm the robust operation of the proposed AI against different process non‐idealities.