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A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients.

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients. [ABSTRACT FROM AUTHOR]

Experimental studies help compare and assess the efficiency of lifetime prediction methods for buried-channel p-MOSFETs under charge-pumping and standard lifetime conditions, with respect to time-dependent degradation. Transconductance degradation restricts the p-MOSFET lifetime in comparison to drain-current and Vth-shift degradation. A charge-pumping technique helps differentiate the time-dependencies of the trapped oxide charge and interface trap generation, while comparison of the prediction methods with respect to trapping process indicates the correlation between oxide charge and transconductance degradation.

A discussion on the fabrication and role of oxide traps above the drain near the spacer oxide of LDD n-channel metal oxide semiconductor field-effect transistors is presented. The floating-gate and charge-pumping approaches are used as the main characterization tools. Results show that the acceptor-like oxide traps are produced by hot-electron and hot-hole injections with generation rates on the order of 10-to-the-negative ninth power and 10-to-the-negative second power.

The charging and discharging characteristics of electron traps produced by hot-carrier injections in the thin gate oxide of n-channel metal oxide semiconductor transistors were investigated. The results showed that the thermal and optical ionization energies of the traps were around 1.7 + or - 0.2 and 3.0 + or - 5 eV, respectively. Theoretical comparisons indicate that Si dangling bonds or oxygen vacancies in the oxide should be the defects created by the injections.

This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si/SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows one to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage. [ABSTRACT FROM AUTHOR]

A theoretical framework about interface state creation rate from Si-H bonds at the Si/Si[O.sub.2] interface which includes three main ways of bond breaking is described. The concept of the framework facilitated to physically model the reliability of metal oxide semiconductor field effect transistors, and particularly negative bias temperature instability permanent part, and channel hot carrier to cold carrier damage.

Endurance is investigated on one transistor floating body RAM cells processed on a silicon-on-insulator substrate with ultrathin buried oxide, and programmed using the bipolar junction transistor current inherent in MOSFETs. During the hole generation step, defects are generated close to the drain. These defects not only reduce the retention time but also result in a lower hole generation rate as a function of the number of cycles, which leads to a write 1 failure. We have shown that standard junction devices with a lightly doped drain (LDD) region are more enduring than extensionless devices with the LDD left undoped. This is owing to the poor spacer oxide on top of the extensionless region where holes are generated. [ABSTRACT FROM PUBLISHER]

A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes. [ABSTRACT FROM PUBLISHER]

Abstract: The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation. [Copyright &y& Elsevier]

In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the recovery characteristics associated with negative bias temperature instability and channel hot carrier degradation in p-channel metal-oxide-semiconductor using a novel method of on-the-fly patterns of biases. We demonstrate experimentally that we can identify two types of mechanisms associated with degradation. One of them is associated with recovery dynamics, and the other relates to nonrecoverable degradation. [ABSTRACT FROM PUBLISHER]

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components. [ABSTRACT FROM PUBLISHER]

In this study, we have characterized the degradation of metal–oxide–semiconductor structures having a 2.2 nm-thick gate oxide, after uniform tunnelling injections in large metal–oxide–semiconductor field-effect-transistors or localized channel hot-carrier injections resulting from either first impact ionization or substrate enhanced secondary impact ionization in 50/0.1 μm or 50/0.15 μm N channel devices. The degradation of the oxide is investigated by following the changes of the electrical parameters of the transistor, the gate leakage current, and the interface state density measured by charge pumping measurements. Uniform tunnelling injections are found not to degrade the oxide and the structure up to 300 C/cm2 of injected charge. The induced damage is found to result from acceptor-type defects located at the Si/SiO2 interface and extends below the channel, without any recorded-trapped charge in the interior of the oxide. Substrate enhanced electron injection induce a reduction of carrier mobility and a larger increase in gate leakage current than the one recorded after first impact ionization injection and uniform stresses. [Copyright &y& Elsevier]