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Titanium-based contacts are envisioned for the integration of III–V device contacts on a 300-mm platform, such as photodetectors, semiconductor optical amplifiers (SOAs), and III–V silicon hybrid lasers. For the first time, the impact of the thermal budgets of process integration, back-end of line (BEOL), and long-term thermal stress on the electrical characteristics of the Ti/p-In0.53Ga0.47As and Ti/n-InP contacts has been investigated. Additional physical characterizations have been used to supplement the electrical properties on both systems. Results have indicated that, given a thermal budget between 350 °C and 450 °C during 60 s right after metal deposition, 1) Ti as a contact metal has led to contact resistivity in low $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for p-contacts and in mid $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for n-contacts, which is in accordance with the device requirements; and 2) process integration, BEOL, and long-term thermal stress will not induce any change of the electrical properties. In the scope of III–V silicon hybrid laser contact integration, Ti has hence been evidenced as a suitable candidate for both p- and n-contacts.

In this paper, we present the hybrid III–V/Si photonic platform developed in CEA-LETI. The overall integration is done in a fully CMOS compatible 200-mm technology, scalable to 300-mm wafers, leveraging the large-scale integration capabilities of silicon photonics. III–V material is integrated on top of a mature silicon photonic front-end wafer through direct molecular bonding enabling the monolithic integration of light sources. DFB and distributed Bragg reflector (DBR) laser reference designs are used as test vehicles for the process validation. A modular approach is used in order to minimize the impact on the already qualified silicon-based devices. Collective III–V die bonding is proposed in this platform. CMOS compatible metallizations are used to form ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². A planarized two-metal-level BEOL is used to connect the device, leading to a drastic reduction of series resistance. Finally, the functionality of both types of lasers is demonstrated with SMSR up to 50 dB and maximum output power of 5 mW.

International audience; Although silicide oxidation was studied 20years ago, the interest in obtaining a robust process for new applications remains significant today. Indeed, the new architectural development process requires dense and narrow spaces. In this study, attempts were made to bury a silicide layer under a protective silica layer in order to keep the physical and electrical properties of the silicide constant after oxidation. Thus, we first tried to reproduce and study these conditions and, once acquired, aimed to decrease the oxidation temperature in order to meet industrial requirements. Titanium (Ti) and nickel (Ni) were chosen for their metallurgical interest and their integration capability in devices. Four different groups of silicide (TiSi, TiSi2, Ni2Si, NiSi) were targeted by adjusting the temperature. Then, all of the silicides, including one pure Si wafer, were oxidized using dry, wet and plasma techniques. In situ scanning electron microscopy, spectroscopic ellipsometry and X-ray reflectivity measurements were carried out simultaneously before and after oxidation of the silicide to characterize the SiO2 and silicide morphology, thickness and density. We found that after 800 degrees C dry oxidation, Ti silicide was totally oxidized, which was an unexpected result. But, Ni silicide showed an agglomeration phenomenon after 500 degrees C and 800 degrees C dry oxidation. Although, after wet oxidation, it was confirmed that the highest SiO2 thickness formed, the NiSi surface roughness was higher. In the case of plasma oxidation, we obtained a thin layer (approximate to 1nm) of SiO2 on NiSi with an extremely smooth surface.

Nickel-based metallization are envisioned for the p-contact integration of III-V / silicon hybrid lasers on a 300 mm platform. The electrical and physical characteristics of Ni 0.9 Pt 0.1 and Ni thin films on In 0.53 Ga 0.47 As layers have been studied. For the first time, the impact of the thermal budget of the process integration and laser operations on the contact integrity have been investigated. Results have shown that in the case of the Ni 0.9 Pt 0.1 / p-In 0.53 Ga 0.47 As system, with a rapid thermal annealing between 350 and 450 °C for 60 s applied after metal deposition, promising contact resistivities have been extracted (low 10–5 - high 10–6 Ω.cm2) along with a good electrical stability after process integration and laser operations. The Ni / p-In 0.53 Ga 0.47 As system have exhibited lower contact resistivities (low 10–6 - high 10–7 Ω.cm2) granted a rapid thermal annealing between 400 and 500 °C after metal deposition. A strong electrical stability after integration steps and laser operations has also been evidenced. Results suggest that the Ni / p-In 0.53 Ga 0.47 As system constitutes the most promising option for p-contact integration.

We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

International audience; Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.

In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni2P metallization combined with an in situ Ar+ preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as $4.3 \times 10^{-6}~\Omega ^{2}$ on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.

3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self-aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre-treatments have been carried out. Indeed, a novel Ni-based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si-Cap) and Si0.7Ge0.3:B S&D pre-amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si-Cap. Moreover, the presence of Si-Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.

In this progress review, an overview of the CMOS-compatible contact technology developed at the CEA-Leti for Si photonics applications is proposed. The elaboration of III–V/Si hybrid lasers implies the development of ohmic contacts on n-InP and p-InGaAs III–V materials. In this way, a contact technology fully compatible with a Si-Fab line was developed. The results presented in this manuscript cover a wide scope: from surface preparation and solid-state reaction to electrical results and integration guidelines. The metallurgy of several systems including Ni/InGaAs, Ni/InP, Ti/InGaAs and Ti/InP was studied. The direct metallization of III–V materials using Ni2P was also introduced. Most of the studied metallizations provided efficient solutions for achieving ohmic contacts on n-InP and p-InGaAs. Finally, the contact technology developed in the framework of this study was successfully integrated on 200 mm CMOS-compatible III–V/Si hybrid lasers.

From surface preparation and solid-state reaction to laser integration, a short overview of the CMOS-compatible contacts developed in our group on n-InP and p-InGaAs for Si photonic applications is proposed.

Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid. In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for this integration will be deeply described. These modules are localized silicon thickening using damascene process, Bragg reflector patterning with DUV lithography, III-V patterning and ohmic contact formation with no lift-off and without noble metal. This integration is compatible with a multi metal levels planar BEOL, mandatory for photonic circuit design. The first DFB lasers fabricated with this new platform are operating at 1310nm with a threshold current around 60mA, a SMSR larger than 45dB and more than 1.5mW optical power in the output waveguide. New laser designs, specifically adapted for this new process, will be introduced and fabricated.

In this paper, we present a short overview of the CMOS-compatible contact technology developed in our group on n-InP and p-InGaAs for Si photonic applications. Obtained results cover a wide spectrum: from surface preparation and solid-state reaction to electrical results and laser integration. The metallurgy of several systems including Ni / InGaAs, Ni / InP, Ti / InGaAs and Ti / InP has been studied. Most of the metallizations studied provide efficient solutions for contacting n-InP and p-InGaAs. Finally, guidelines for integrating low resistivity contacts are proposed.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

In this paper we demonstrate the first integration of a hybrid III-V/Si laser in a fully CMOS compatible 200mm technology. Device with SMSR up to 50 dB and a maximum output power of 4mW coupled in the waveguide have been measured. The fabrication flow is fully planar and compatible with large scale integration silicon photonics circuit.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one hand, Ni/n-InP Ar-precleaned contacts exhibit nonohmic behavior for each investigated thermal budget. On the other hand, He-precleaned contacts features ohmic behavior for the as-deposited state and thermal anneals up to 350 ° C for 60 s. They, however, become nonohmic after anneals of 400 and 450 ° C for 60 s. These results, hence, suggest that the difference of electrical behavior obtained between Ar and He-precleaned Ni/n-InP contacts is due to differences in the state surface and morphology.The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one han...

Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully benefit from the desired effects of strain engineering techniques. This paper deal with the impact of the silicidation process conditions on the strain of Si1-xGex:B layers (x=0.3 and 0.45) and SiC:P with [C]≤1,5%. We show that the strain of epitaxial layers is not affected by the silicidation in the case of Si0.7Ge0.3 and SiC, while a strong degradation of strain occurs with Si0.55Ge0.45. The strain evolution in the channel of a device at various stages of the silicidation process has been followed using dark field electron holography. We show that process parameters can be tuned in order to minimize the reduction of strain induced by the silicidation

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

To improve 20nm FD-SOI pMOS transistor performances, salicide process must be optimized on SiGe source&drain. In this paper, we propose an investigation on Ni and Pt/Si1-xGex (x=0.15, 0.3) systems. In a first part, process window is studied to determine thermal budget domain where the less resistive phase is stable morphologically and thermically. Solid state reactions in terms of phase sequence, thermal stability and morphology have been examined. At high temperature, two kinds of degradations have been observed. In Ni case, Ge out diffusion leads to the film agglomeration. In Pt case, grain coalescence degrades germanosilicide film. In a second part, contact resistivity has been extracted on lateral germanosilicides thanks to new designed structures. After a validation on Pt/Si system, RC extraction has been carried out on Si1-xGex substrate up to 30% of Ge. RC seems to be better with Pt compared to Ni with the same conditions of process optimizations.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has been integrated on pMOS FDSOI transistors with state of the art process leading to performance improvements compared to the standard Ni0.85Pt0.15 salicide. In this study, the cobalt incorporation into the salicide has been investigated to enhance its thermal stability.

International audience; Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650^oC). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.

Ni-GeSn based materials are promising in order to obtain contacts in complementary metal oxide semiconductor and Si photonic devices. In this work, a systematic and comprehensive study of the solid-state reaction between NiPt thin films and Ge0.9Sn0.1 layers is carried out. A particular focus is given on the impact of the addition of 10 at. % of Pt in Ni thin films. In situ X-ray diffraction and in-plane reciprocal space map measurements reveal a sequential growth in which the first phase appearing corresponds to a Ni-rich phase: (Ni0.9Pt0.1)5(Ge0.9Sn0.1)3. Then, at 245 °C, the Ni-rich phase vanishes to the benefit of the mono-stanogermanide phase (Ni0.9Pt0.1)(Ge0.9Sn0.1), which is unstable. At 360 °C, a more stable (Ni1– yPty)(Ge1– xSnx) phase is obtained concomitantly to the formation of PtSnx compounds. Finally, Sn segregation occurs at even higher temperatures. Even if Pt addition in Ni thin films complicates the phase formation sequence, it positively impacts the surface morphology and roughness, delays film agglomeration and Sn segregation, and stabilizes the electrical properties of the stanogermanide in a wide range of temperatures.

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

The metallurgical properties of the Ni/n-InP system have been investigated. We report the formation of a compositionally nonuniform Ni-In-P amorphous layer during the DC sputtering metal deposition process which includes an Ar+ cleaning. During various heat treatments the simultaneous appearance of the Ni2P and Ni3P binary phases and the Ni2InP ternary phase were observed. For temperature equal to or greater than 350°C we highlighted the partition and precipitation of In. Thanks to RTP and longtime annealings we pointed out the predominance of diffusion on the formation of the Ni2P, Ni3P and Ni2InP phases and that of nucleation on the partition and precipitation of In.

In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (V GS =V dd =0.7V) increase versus a Titanium liner-based silicidation-free approach.

We have investigated the impact of various plasma treatments on InGaAs layers. Argon- and helium-based direct plasmas are more efficient than remote plasmas for the removal of InGaAs native oxides. We have demonstrated that the nature of direct plasma influences the InGaAs oxides removal efficiency. Indeed, both types of plasma seem to be efficient for removing arsenic oxides whereas the elimination of In oxides is more effective with Ar plasma. Hydrogen addition in He plasma impacts the removal of InGaAs oxides and appears to have a reducing effect on indium atoms. Whatever the nature of the pretreatment, the surface morphology and roughness of InGaAs layers were not significantly impacted.

The metallurgical properties of the Ni/n-InP system have been investigated. We report the formation of a compositionally nonuniform Ni-In-P amorphous layer during the DC sputtering metal deposition process which includes an Ar+ cleaning. After RTP and long in situ annealing treatments the simultaneous appearance of the Ni 2 P and Ni 3 P binary phases and the Ni 2 InP ternary phase were observed. Kinetics and nucleation phenomena were highlighted by the precipitation of In during the RTP.

We introduce a full 3D reciprocal space map (RSM) measurement technique developed at the BM02 beamline (ESRF) in the framework of ultrathin polycrystalline films for microelectronic applications. This technique gives a complete overview of the reciprocal space in a large range of Bragg angles to detect and characterize the nature and texture of all phases present in a polycrystalline film. As a demonstration for this technique we have performed 3D RSM measurement on several kinds of samples: Ni-based germano-silicide on silicon for source/drain contacts in the framework of sub-20 nm FD-SOI transistors; Ni-based alloyed with III-V materials for power electronics application; and PZT thin films on silicon substrate for MEMS applications. New software (DEVA) is developed in pure Python language in order to quickly automatically and on line treat these multidimensional data, taking into account the specific geometry of our area detector XPAD.

We studied the solid-state reaction of Ni thin films with InGaAs layers grown on InP or Si substrates. The inter-metallics obtained carried an hexagonal structure, but yielded a difference in orientation regarding either the substrates or the annealing temperature.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

Linear scaling CMOS has encountered many hurdles which request new process modules, driven mainly by the maximization of energy efficiency. Fabrication at the sub 10nm node level will request Intrinsic Variability approaching to zero. The rapid growth of mobile, multifunctional and autonomous systems is hardly demanding to reach Zero Power consumption. The solutions to integrate Thin Film based devices, architectures and systems in order to face these challenges are described.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

We review in this paper some key enabling process integration modules, the development of which will allow pursuing the trend of energy efficiency improvement in sub-28nm FDSOI technologies.

This paper deals with the thermal and morphological stabilization of nickel-based silicides and germanides using tungsten and fluorine implantation for 3D monolithic CMOS applications. The incorporation of few % of W and/or F at various steps of the salicide process can successfully address two major issues: the morphological degradation (agglomeration) of NiSi and NiGe layers on one side and the Ge diffusion outside the active regions on the other side. The paper highlights cumulative effects of Pt alloying together with the incorporation of F and W for delaying at higher temperatures the agglomeration phenomenon. It also deals with the strong reduction of Ge diffusion using W and F implantation. Implantation conditions (dose, energy) and schemes (implantations prior metal deposition, after metal deposition, into the silicide) are discussed.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm 2 /V/s resp.).

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; I OFF =60nA/µm @ V DS =-1.2V; L g =30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.

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The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance (R co ) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of 0.32 eV for electrons and 0.15 eV for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.

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Thin films of Ni(Si1−xGex) are of interest for their applications in metal-oxide semiconductor transistors as contacts and interconnections. In this work, the lattice parameters and the coefficients of linear thermal expansion (γa, γb, and γc) of the orthorhombic Ni(Si1−xGex) alloys, with 0⩽x⩽1, were determined from high-temperature x-ray diffraction data (298–1073K). A negative thermal expansion along the b axis of Ni(Si1−xGex) is observed for all x values of the Ge concentration: the magnitude of the thermal expansion coefficient decreases with increasing Ge concentration. The anisotropy of the thermal expansion is potentially important for the integration of Ni(Si1−xGex) in microelectronic devices.

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The reaction between nanometric Ni films and Ge is analyzed using isothermal x-ray diffraction measurements and transmission electron microscopy. It is found that NiGe is formed during deposition at room temperature. The metal rich phase that grows during heat treatment has been clearly identified to be Ni5Ge3. The simultaneous growths of Ni5Ge3 and NiGe have been observed on amorphous and polycrystalline germanium. This is in contrast with the usual sequential growth reported in thin films.