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We report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH4 as an etchant, we rely for this work on Cl2-based etching and the use of a higher order Si precursor which allows to maintain a high wafer throughput at low temperatures. We demonstrate that selective Si:P layers can be obtained with a resistivity below 0.3 mOhm.cm which can be grown selectively on fins and stacks with Si nanosheets.

This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS–SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost of ownership are estimated.

Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high- $\kappa $ metal gate (HKMG) FinFET transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. In addition, activation energies for the capture process in tall fins during NBTI stress show lower values while charge trapping in standard height fins is highly temperature dependent. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high- $\kappa $ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin. On the other hand, PBTI shows limited temperature dependence, independent of fin height.

With the introduction of novel stacked CMOS transistor integration schemes such as sequential 3D and CFETs [1,2], there is an increasing need for highly active source/drain layers with a low overall thermal budget. For some integration schemes, processing temperatures below ~ 525°C are desired [3] and in most cases, the contacts need to be formed on the {110} surfaces of exposed Si nanosheets. In this paper, we report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH4 as an etchant [4,5], we rely for this work on Cl2-based etching in combination with Si3H8 as a high-order Si precursor [6]. The Si:P layers were grown in a 300 mm ASM Intrepid® ES reduced pressure chemical vapor deposition reactor on Si (001) substrates. Figure 1 shows some typical characteristics for the Si:P layers without etching (“Dep-only”) and CDE Si:P layers below 500°C. As the temperature is lowered, the growth rate and P incorporation for a given PH3 flow decreases substantially, while the active concentration increases. For both the “Dep-only” and CDE layers, a minimum develops in the resistivity which corresponds to a maximum in active concentration as derived from micro-Hall measurements. Due to the etching during CDE, a P-enrichment takes place and the P concentration in the layers is enhanced compared to the “Dep-only” case. A minimum resistivity of 0.28 mOhm.cm (Pact ~ 6e20/cm3) is obtained for CDE at 480°C which is slightly larger than the minimum resistivity of 0.24 mOhm.cm (Pact ~ 1e21/cm3) for the “Dep-only” case at the corresponding temperature. Figure 2 shows the application of the CDE process on wafers with fins. By lowering the deposition time at a constant etching time per cycle, a (wafer-scale) selective regime can be reached. For the “Dep-only” case, quite some defects and nuclei are present on the sidewalls of the Si-fins and the oxide dielectric, respectively, which are finally removed by sufficient Cl2 etching. Figure 3 compares the corresponding X-TEMs of the above fins after “Dep-only” and selective CDE conditions. For the “Dep-only” case we can only observe a mono-crystalline growth in the direction. For other growth directions like , epitaxial breakdown-down occurs resulting in a substantially reduced crystalline thickness. With the use of Cl2 based CDE, a selective growth can be reached as well as a clear structural improvement in the growth direction, which is very important for the application in nanosheet devices. Finally, once a (111) facet is formed, twin defects occur as expected for low temperature Si:P and Si:C:P [7]. The growth behavior of the CDE processes in relevant nanosheet geometries is currently under investigation. References [1] W. Rachmady et al. in Proc. IEDM 2019. [2] C.-Y. Huang et al. in Proc. IEDM 2020. [3] A. Vandooren et al. in Proc. VLSI 2018. [4] N. Loubet et al., Thin Solid Films 520, pp.3149-3154 (2012). [5] J.M. Hartmann et al., Semicond. Sci. Technol. 28, p.025018 (2013). [6] M. Bauer, ECS Trans. 50(9), pp. 499–506 (2012). [7] J. Tolle et al., ECS Trans. 50(9), pp. 491-497 (2012). [8] E. Rosseel et al., ECS Trans. 75(8), pp.347-359 (2016). Figure 1

We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO 2 , LK3.0, SiCO and Si 3 N 4 films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO 2 , LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si 3 N 4 films.

Due to the slowdown in gate pitch scaling linked to fundamental physical limitations, standard cell (SDC) height reduction becomes a key to achieve the scaling targets. In this work, a two-level (2L) middle of line (MOL) scheme based on a forksheet (FSH) device architecture and Vertical-Horizontal-Vertical (VHV) routing style is proposed to achieve 4-Track (4T) SDC template. The proposed architecture achieves 21% higher Power-Performance-Area (PPA) compared to the traditional 5T-HVH FSH architecture with limited additional process complexity and Cost (C).

The focus of this paper is on automatic methodology to detect the sidewall voids in narrow trenches filled by Ru. For this purpose, we applied image processing techniques for image recognition and labeling of images obtained by high-angle-annular-dark-field scanning TEM (HAADF-STEM). Roughly 3300 STEM images of narrow trenches with BCD of 10nm and AR>8 were labeled. This paper demonstrates the versatility and potential of image processing to address the automated void detection in advance MOL applications.

In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {V OV ,V D } stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.

It is shown that replacing a TiN effective work function metal by TaN results in a pronounced reduction of the low-frequency noise power spectral density (PSD) of thick-SiO2 input/output (I/O) DRAM peripheral pMOSFETs. The 1/ $f$ noise is originating from carrier number fluctuations, suggesting that the observed reduction results from a decrease of the oxide trap density in the SiO2. On the other hand, I/O pMOSFETs with a TiN gate deposited by different methods or used as a sacrificial gate in a gate replacement integration scheme yield a similar high 1/ $f$ noise PSD and corresponding oxide trap density.

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.

Fin height dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-κ metal gate (HKMG) FinFETs transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related to a reduced role of the defective fin corners and/or top surface. PBTI results reveal a similar, albeit less severe, impact of fin height, suggesting an impact of fin height on the high-κ layer, with again an increased defectivity at the fin corners and/or top surface, whose effective role is reduced in the case of taller fin.

Automotive, Artificial Intelligence/Machine Learning and blockchain generation are imposing increasing demanding specs for Dynamic Random Access Memory (DRAM) memories. Wider memory bandwidth can be achieved by using conventional planar SiO2 MOSFET and different interfaces but at the expense of required energy per bit. Advantages of High-K/Metal Gate versus SiO2/SiON planar DRAM periphery devices compatible with DRAM memory fabrication have been demonstrated in literature. More recently, the power performance benefit of FinFET for DRAM peri devices have been discussed. In this paper we provide a detailed analysis and additional insights in the first experimental validation of a thermally stable, reliable and cost effective tall fins platform (65 and 80 nm fin height). Power performance benefit versus fin height and expected area advantages on Sense Amp area are presented.

Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3-nm equivalent-oxide-thickness (EOT) interfacial layer (TmSiO) and two different bulk high- $k$ dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate-stack EOT was 1.2 and 0.65 nm for the Tm2O3 and HfO2 samples, respectively. In general, both gate-stacks resulted in 1/ $f$ type of noise spectra and noise levels comparable with the conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was $2.5\times 10^{17}$ and $1.5\times 10^{17}$ cm $^{\mathrm {-3}}$ eV $^{\mathrm {-1}}$ for TmSiO/HfO2 and TmSiO/Tm2O3, respectively. Therefore, the best noise performance was observed for the gate-stack with Tm2O3 bulk high- $k$ layer and we suggest that the interface free single-layer atomic layer deposition (ALD) fabrication scheme could explain this.

We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We demonstrate that oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed by a SiN liner. This SiN fin protection improves the controllability of nanowire formation. In addition, highly-selective Si nano-wire release and inner spacer cavity formation without Si re-flow are demonstrated. Finally, for the first time we report functional ring oscillators based on stacked Si NW-FETs.

Integration of a high- $k$ interfacial layer (IL) is a promising technological solution to improve the scalability of high- $k$ /metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiO x /HfO2 nFETs (0.7 A/cm $^{2}$ at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and −0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO2 stack, i.e., improved channel mobility over SiO x /HfO2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm $^{2}$ /Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO2/TiN gate stack is investigated, demonstrating 10-year expected lifetimes for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

An alternative route to continue the trend of scaling of CMOS technology is to implement novel channel materials with superior transport properties. Germanium has high intrinsic mobilities for both electrons (3900 cm2/Vs) and holes (1900 cm2/Vs), and is compatible with Si process technology, making it a suitable channel material for low power, high performance devices. The smaller band gap of Ge (0.67 eV) potentially allows for lower contact resistances compared to Si due to a reduced barrier height, and hence is more suitable for voltage scaling. A challenging task is the formation of a high-quality gate stack with low interface trap density and sub-nm equivalent oxide thickness (EOT) to maintain the intrinsically high performance of Ge. The peak electron mobility has been dramatically improved for Ge MOSFETs in recent years [1,2], largely achieved by improving the quality of GeO2/Ge interface. Although thermally grown GeO2 is the most natural choice, its inherent shortcomings still remain, such as: high water solubility, low desorption temperature (~400°C), low dielectric constant (~6); unconventional growth methods. Since the dielectric constant of GeO2 is low it cannot be used as the gate dielectric for aggressively scaled devices. The focus is on high-k dielectric (k>20) for sub-nm EOT scaling. The Liverpool group has been interested in two possible routes for Ge interface engineering: (i) using high-k materials that are intimate with Ge, such as La2O3 and Y2O3, and (ii) introducing a robust ultra-thin high-k interfacial layer (IL) barrier, such as Al2O3 and Tm2O3. Concerning the first route, high reactivity of Ge with high-k allows for germanate IL formation, which role is two-fold: to reduce the interface states, and to suppress the GeO desorption at the interface. The second route involves the use of ultra-thin barrier layers, Al2O3 and Tm2O3, as oxides highly resistant to oxygen diffusion and to reaction with Ge. The rare-earth metals (La, Y, Tm) tend to possess multiple valency, such as +2 and +3 oxidation states, that can provide effective passivation of electrically active defects. Both routes lead to achieving a GeOx-free gate stack with effective Ge surface passivation. We will present an overview study of physical and electrical properties of La2O3/Ge, Y2O3/Ge, Tm2O3/Ge, Al2O3/Ge and HfO2/Al2O3/GeO2/Ge gate stacks. The interfacial composition, valence band offset, uniformity, thickness, band gap, crystallinity, dielectric function and absorption features will be shown, as ascertained using X-ray photoelectron spectroscopy, X-ray diffraction, high resolution transmission electron microscopy, medium energy ion scattering and ultra violet variable angle spectroscopic ellipsometry. The correlation of these results with electrical characterization data, will make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS. Acknowledgement: the authors thank the EPSRC (UK) and the EU (OSIRIS and ESTEEM2 projects) for funding. [1] S. Takagi et al., Microelectron. Eng. 109, 389 (2013); [2] A. Toriumi et al. IEEE IEDM Tech. Dig., 646 (2011).

A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic ...

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

State-of-the-art CMOS technology relies on the integration of multi-layer high-k/metal gate stacks in order to achieve high capacitance density while fulfilling the requirements in terms of gate leakage current density, interface state density, channel mobility, threshold voltage and reliability. Conventional SiO x /HfO 2 gate dielectric stacks are capable of meeting the performance targets of current technology nodes and have been shown to possess sufficient short-term scalability, but solutions providing enhanced long-term scalability are actively researched, mostly via integration of higher-k oxides or high-k interfacial layers. This paper provides an overview of recent research efforts in this area, focusing on integration of high-k interfacial layers. We then analyze the potential scalability improvement which can be obtained through integration of thulium silicate as interfacial layer and summarize the main results supporting its applicability to future technology nodes.

In this work, the negative bias temperature instability (NBTI) performance for HKMG and diffusion and gate replacement (D&GR) input/output (I/O) devices is investigated. Even though NBTI performances of D&GR transistors are aligned with conventional HKMG (high-k/metal gate) integration with thin oxide devices, it is not the case for thick oxide I/O devices. In particular, it is shown that strong lifetime degradation is observed as soon as high-k layers are deposited on top of the thick interfacial layer. The NBTI degradation is correlated to a diffusion of Ti/Hf (potentially Al) elements from the HKMG gate stack down to the interfacial layer. Directions for reliability improvement treatments are then defined. It is shown that decoupled plasma nitridation (DPN) and fluorine implant could greatly improve NBTI performance, through an improvement of interface and bulk (inside SiO2 interfacial layer) defect density. Device trade-offs are also investigated for the DPN treatments and fluorine implants cases.

High-k/metal gate stacks have been a core enabler of CMOS technology for almost a decade, allowing sub-nm equivalent oxide thickness (EOT) while keeping the gate leakage current density at acceptable levels [1]. State-of-the-art high-k/metal gate stacks employ a Hf-based high-k dielectric (typically HfO2) deposited on top of a thin interfacial layer (IL), which usually consists of chemical oxide (SiOx) and whose presence is crucial in order to guarantee the overall electrical quality of the gate stack [2]. It has indeed been shown that a thinner IL, while desirable from the point of view of EOT scaling, leads to problematic degradations in channel mobility [3], threshold voltage control [4], and device reliability [5]. Further scaling of high-k/metal gate stacks has been a central subject in recent research, and is usually addressed by replacing HfO2 with a higher-k material and/or by replacing SiOx with a high-k IL. The latter strategy is especially interesting, since the IL contributes ~1/2 of the total EOT of a scaled gate stack and since there are viable options to replace SiOx with a dielectric exhibiting significantly higher dielectric constant (~3x), whereas the same is not true for higher-k dielectrics. Lanthanide silicates have especially been shown to provide controllable thickness of the IL in the sub-nm regime and device-grade interface state density, rendering them extremely interesting as a potential replacement for SiOx IL [6]. Careful consideration of the material properties from the point of view of achieving controllable and reproducible formation of a sub-nm interfacial layer has led to the identification of thulium silicate (TmSiO) as a promising candidate IL for sub-10nm CMOS nodes. A straightforward process flow, compatible with industry-standard gate-first and gate-last integration schemes, has been demonstrated for integration of TmSiO in a high-k/metal gate stack, achieving EOT of the IL of 0.25±0.15 nm and interface state density ~1·1011 cm-2eV-1 [7]. Integration of TmSiO in Hf-based gate stacks has also been shown to be compatible with threshold voltage control techniques commonly used in gate-first and gate-last integration schemes [8], and gate-last MOSFETs achieving sub-nm EOT, 10 year device reliability and higher mobility than state-of-the-art SiOx/HfO2 devices have been demonstrated [9-10]. Replacing the SiOx IL with TmSiO can be especially advantageous in terms of channel mobility and device reliability, since both device properties have been shown to degrade strongly with decreasing IL thickness. Reliability in TmSiO/HfO2 MOSFETs has been investigated from the point of view of time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI), achieving expected lifetimes of 10 years for both nFETs and pFETs at EOT~0.8 nm and gate voltage ~1V (compatible with supply voltage in sub-10nm CMOS nodes). The effect of TmSiO on channel mobility has been analyzed by measuring electron mobility at high temperature and after constant voltage stress and comparing the observed trends with published data on SiOx/HfO2 devices, with the conclusion that replacing the SiOx IL with TmSiO can improve mobility by 20% at high effective field due to reduced remote phonon scattering. In this talk, the main advantages and challenges in the adoption of TmSiO as interfacial layer in scaled CMOS technology nodes will be addressed. [1] K. Mistry et al., IEDM Tech. Dig., pp. 247–250, 2007. [2] T. Ando, Materials, vol. 5, no. 3, pp. 478–500, 2012. [3] L.-Å. Ragnarsson et al., Int. Symp. VLSI Technol. Syst. Appl., 2011. [4] T. Ando et al., IEEE Electron Device Lett., vol. 34, no. 6, pp. 729–731, 2013. [5] E. Cartier et al., IEDM Tech. Dig., pp. 441–444, 2011. [6] T. Kawanago et al., IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 269–276, 2012. [7] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3271–3276, 2013. [8] E. Dentoni Litta et al., Solid-State Electron., vol. 108, pp. 24-29, 2015. [9] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 934–939, 2015. [10] E. Dentoni Litta et al., IEEE J. Electron Devices Soc., vol. 3, no. 5, pp. 397–404, 2015.

The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap densities appeared at the high-k interface or in the bulk, mobility degradation and enhancement in the level of low-frequency noise [1]. Previously low-frequency noise in devices with PtSi Schottky-barrier source/drain contacts were studied [2]. In this work the low-frequency noise characterization of MOSFETs with high-k LaLuO 3 dielectric and TiN gate is presented. The devices were fabricated on an SOI substrate thinned down to 30 nm by sacrificial dry oxidation and HF wet etching. Active areas were patterned through MESA etching. The process was continued with an optional growth of a 5 nm layer of thermal oxide on the wafers. The high-k LaLuO 3 dielectric was deposited by MBE (t LaLuO3 =6 nm) and the metal TiN gate by sputtering (t TiN =20 nm). This was followed by in-situ deposition of phosphorus doped poly-Si with t poly =150 nm. For the reference wafer, the high-k deposition was skipped. PtSi Schottky-barrier source/drain with Boron and Arsenic implantation was carried out for pMOSFETs and nMOSFETs respectively. In the next step, RTA at 700°C was performed for dopant segregation at the PtSi/Si interface. The fabrication process was finalized by metallization and FGA (10% H 2 in N 2 at 400° C for 30 min).