Search

In the wide bandgap (WBG) arena, it is generally considered that GaN and SiC are competitors for the 600 V voltage class. However, in reality, they possess partly highly complementary functional characteristics, which, when duly combined, can yield advanced performance in power conversion applications. Here, the focus is specifically on the development of a hybrid GaN-SiC power switch to demonstrate superiority over either a GaN-only or SiC-only transistor. It is an original undertaking, whose outcomes will be directly applicable to several application domains., IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD 2022), 22-25 May 2022, Vancouver, Canada

This paper presents the modeling of the electrothermal and electromagnetic behavior in SiC-based multi-chip power modules. The proposed approach is based on a macromodeling technique and is applied to a realistic case-study. Preliminarily, the assembly under analysis was experimentally characterized to estimate its parasitics due to electromagnetic interactions. Extremely fast and efficient electrothermal simulations were then performed in a SPICE-like environment. Parasitics and nonlinear thermal effects were accounted for in simulations at high switching frequencies. Results demonstrate that such an approach can be successfully adopted in the design flow of power modules in any device technology.

This article focuses on the thermal analysis of direct bonded copper (DBC) substrates embedded in SiC-based multi-chip power modules. Due to the development of the innovative double-sided cooled technology, such substrates turn out to play a relevant and growing role in defining the PMs thermal, electrical, and mechanical performances. The study is aimed to compare typical ceramic materials adopted for the DBC manufacturing process; the comparison is carried out by means of exceptionally accurate nonlinear FEM 3-D simulations performed in the COMSOL Multiphysics environment. The influence of dissipated power and boundary conditions is thoroughly investigated by accounting for the temperature dependence of the thermal conductivities.

In this paper, an enriched version of a VHDL-AMS tool devoted to electro-thermo-mechanical simulations is presented. The major improvement consists in the evaluation of the vertical displacements of the layers in the domain. As a case study, the mechanical deformations and stress in a principle structure emulating a state-of-the-art multi-chip SiC-based power module are thoroughly examined. By means of the proposed approach, the vertical displacements were quickly investigated and quantified in a typical electro-thermo-mechanical stress test scenario.

This paper is aimed to investigate the electrical ruggedness of double-sided cooled power modules in SiC technology. In particular, an approach based on 3-D FEM simulations performed in the COMSOL Multiphysics environment is presented. In order to improve the module reliability and reduce the number of failure occurrences, most of the designers commonly adopt higher spacing among the interfacing DBC substrates that compose the assembly. The simulation results are devoted to meticulously quantify the beneficial effects of such spacing, thus providing useful guidelines for the design of power modules. An unexpected numerical outcome is then presented and a thorough explanation of the underlying physics is provided.

The relevant cooling action ensured by the thermal vias in PCB-based power circuits allows extending the operating conditions of the semiconductor devices. However, to properly drain off the power dissipated in the active regions, efficient thermal designs must be developed. To further reduce the devices operating temperature, a strategy to take advantage of the unexploited PCB areas surrounding the device footprint is proposed and discussed in this paper. The analysis is carried out by means of 3-D FEM thermal simulations performed in the COMSOL Multiphysics environment. This investigation is devoted to providing guidelines for an optimum design of thermal vias by accounting for their main geometrical features.

This work proposes analytical thermal models for through-PCB thermal vias and passive heat-sinks, two key components of the overall junction-to-ambient thermal resistance in modern integrated power electronics circuits based on advanced wide-band-gap semiconductor technology. The proposed models aim to support the thermal design of PCB and cooling system by the quick estimation of their thermal resistances. The models are scalable in that they fully include the geometry, material properties and boundary conditions. As a case-study, reference is made to the cooling of last generation gallium nitride HEMTs in SMD type package. Here, only the static behavior is considered. The models accuracy is evaluated by comparison with accurate FEM simulations performed exploiting the commercial software COMSOL Multiphysics aided by a MATLAB routine developed by the authors.

This paper presents a comparative study of different approaches and solutions to the cooling of new type highly compact flat packages for gallium nitride (GaN) transistors. The focus here is on an inverter intended for hybrid and full-electric transport applications, where optimization of the gravimetric power density is paramount. As a case-study, a 3-level active neutral point clamped (aNPC) bi-directional inverter-rectifier topology is considered. The outcomes of the investigation are manifold: optimum design of thermal vias is considered; it is highlighted that the use of a graphene layer just underneath the chip can help reduce the temperature gradient between chip and PCB and can also improve heat-conduction in subsequent layers of the assembly, by enabling a better exploitation of lateral heat-flow possibilities, too; the benefit of using a soldered DCB substrate to assist heat removal from the vias towards the heat-sink is quantified for different materials of the insulating layer (ceramic).

In this paper, an experimental and numerical study of the electrical ruggedness in double-sided cooled power modules is presented. In particular, the analysis focuses on the role of the spacing between substrates, which are commonly kept distant to avoid electrical failures like partial discharge and dielectric breakdown. To this aim, many double-sided cooled assemblies were manufactured and then tested by monitoring the leakage current due to high voltages applied to the terminals. Two failure mechanisms are recognized and characterized. To provide an explanation of the counterintuitive measurement outcomes, 3-D FEM electrostatic simulations were performed on the power module samples in the COMSOL Multiphysics environment.

This paper investigates the effect of negative gate bias voltage (V gs ) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

Failure mechanisms during short-circuit conditions of Silicon Carbide Power MOSFETs are analysed in this work, and a possible theoretical explanation is provided. Insight into the physics involved in such processes was inferred through experimental and numerical analyses. The TCAD structure used for electro-thermal simulations was calibrated to fit the I D -V GS characteristics of a commercial device. Adequate physical effects were considered, such as the presence of charges and traps at the oxide-SiC interface and their effect on threshold voltage and carrier mobility. Experimental evidences were explained by analyzing the numerical results. The high temperature reached during these operating conditions was addressed as the main cause of the device failure. The effect on the leakage current and the activation of a parasitic bipolar transistor are also shown.