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The radio frequency (RF) experimental and simulation study of a 3-dimensional (3-D) multichannel silicon-on-insulator (SOI) MOSFET (MCFET) is presented. The studies have shown that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications.

Numerical simulations, characterization methods and integration processes are developed to examine and optimize three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance. The impact of a high-[kappa] metal TiN/Hf[O.sub.2] gate stack introduction on the MCFET electrical properties is studied, and the methods to reduce the increase in series resistance by optimizing the source/drain (S/D) shape and the S/D silicide position are discussed.

An optimized multi-channel field-effect transistor (MCFET) structure fabricated on a silicon-on-insulator (SOI) substrate with a silicon-on-nothing (SON) process is presented and its performance is analyzed. The current gain of the MCFET structure, its transport properties and specific electrostatic properties are examined, and it is observed that the bottom channel in narrow devices increases the drain current of the MCFET structure without degrading its electrostatic characteristics.

We reported on statistical behavioral models of silicon ring resonators at a commercial CMOS foundry. The ring resonators were fabricated on 300 mm silicon-on-insulator wafers using the DAPHNE technology at STMicroelectronics. Process variability, including lot-to-lot, wafer-to-wafer, and field-to-field variation, is inferred from optical test results, and cross validated by inline metrology data. Significant amount of reflection is observed in many ring designs, and the impacts of reflection on system integration are discussed. [ABSTRACT FROM AUTHOR]

Wideband polarization beam splitters (PBS) are a key building block in polarization management circuits for wavelength division multiplexing applications. A broadband PBS on a 300-mm silicon nitride (SiN) photonic platform is reported based on phase-controlled directional coupler (DC). Unlike classical DC-based PBS made on silicon, the proposed configuration leverages the comparatively lower birefringence in SiN to yield wideband and efficient splitting. A semi-analytical approach, based on transfer matrix modeling and 3-D finite difference time domain, has been used to design and optimize the structure for O-band operation. The proposed PBS has been experimentally demonstrated showing insertion loss (IL) lower than 0.6 dB and extinction ratio (ER) as high as 10 dB over 95-nm bandwidth for both polarizations. Furthermore, this simplified architecture eases cascading, allowing the demonstration of IL below 1.1 dB and ER larger than 24 dB over 85-nm wavelength range in a dual-stage configuration. [ABSTRACT FROM AUTHOR]

Keeping up with bandwidth requirements in next generation short- and long-reach optical communication systems will require migrating from simple modulation formats such as on-off keying to more advanced formats such as quaternary phase-shift keying (QPSK). In this paper, we report the first demonstration of QPSK signal generation in the O-band using a silicon dual-drive Mach–Zehnder modulator (DD-MZM). The performance of the silicon DD-MZM is assessed at 20 Gb/s and compared against a similar DD-MZM based on LiNbO3, showing a limited implementation power penalty of only 1.5 dB. [ABSTRACT FROM AUTHOR]

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated. [ABSTRACT FROM PUBLISHER]

This paper presents a 50 Gb/s per lane hybrid BiCMOS and silicon photonic integrated circuit for use in fiber optic communications. Fine pitch copper pillars are used to integrate electronics and silicon photonics. The resulting device demonstrates the generation and detection of up to 56 Gb/s NRZ optical signals over 2-km standard single-mode fiber at 1310-nm wavelength. At 40 Gb/s, the link operates error free, and at 56 Gb/s well below KR4 RS-FEC operating BER. The power dissipation of TX including CW laser is 600 mW (450-mW driver, 150-mW CW laser), RX is 150 mW, resulting in total per channel of less than 750 mW. [ABSTRACT FROM PUBLISHER]

In this paper, for the first time, we present a detailed RF experimental and simulation study of a 3-D multichannel SOI MOSFET (MCFET). Being different from the conventional planar technology, the MCFET features a total of three self-aligned TiN/HfO2 gate stacks fabricated on top of each other, allowing current to flow through the three undoped ultrathinned bodies (UTBs). In other words, the operation of the MCFET theoretically based on two UTB double-gate SOIs and a single-gate UTB fully depleted SOI (FDSOI) at the bottom. Using on-wafer S-parameters, the RF/analog figures-of-merit of an MCFET a gate length of 50 nm are extracted and discussed. Thanks enormous transconductance (gm) and very low output conductance, the RF/analog performances of MCFET-voltage gain (AVI) and early voltage (VEA) are superior compared with that single-gate UTB-FDSOI. However, these advantages diminish in terms of transition frequency (fT), due to the large total input gate capacitances (CGG). This inspires the introduction of spacer engineering in MCFET, aiming at improving both CGG and fT. The sensitivity of the spacer length to the RF/analog performances is experimentally analyzed, and the performance optimization is validated using ac simulation. This paper concludes that optimized MCFETs are a serious contender to the mainstream MOSFETs including FinFETs for realizing future low-power analog applications. [ABSTRACT FROM AUTHOR]

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent ION/IOFF characteristics (NMOS: 2.33 mA/μm at 27 pA/μm and PMOS: 1.52 mA/μm at 38 pA/μm). A gate capacitance Cgg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain AVI (= gm /gds) is improved by 92%. [ABSTRACT FROM AUTHOR]

Integrated microspectrometers implemented in silicon photonic chips have gathered a great interest for diverse applications such as biological analysis, environmental monitoring, and remote sensing. These applications often demand high spectral resolution, broad operational bandwidth, and large optical throughput. Spatial heterodyne Fourier-transform (SHFT) spectrometers have been proposed to overcome the limited optical throughput of dispersive and speckle-based on-chip spectrometers. However, state-of-the-art SHFT spectrometers in near-infrared achieve large optical throughput only within a narrow operational bandwidth. Here we demonstrate for the first time, to the best of our knowledge, a broadband silicon nitride SHFT spectrometer with the largest light collecting multiaperture input (320×410µ m 2 ) ever implemented in an SHFT on-chip spectrometer. The device was fabricated using 248 nm deep-ultraviolet lithography, exhibiting over 13 dB of optical throughput improvement compared to a single-aperture device. The measured resolution varies between 29 and 49 pm within the 1260-1600 nm wavelength range.

Surface grating couplers are fundamental building blocks for coupling the light between optical fibers and integrated photonic devices. However, the operational bandwidth of conventional grating couplers is intrinsically limited by their wavelength-dependent radiation angle. The few dual-band grating couplers that have been experimentally demonstrated exhibit low coupling efficiencies and rely on complex fabrication processes. Here we demonstrate for the first time, to the best of our knowledge, the realization of an efficient dual-band grating coupler fabricated using 193 nm deep-ultraviolet lithography for 10 Gbit symmetric passive optical networks. The footprint of the device is 17×10µ m 2 . We measured coupling efficiencies of -4.9 and -5.2 d B with a 3-dB bandwidth of 27 and 56 nm at the wavelengths of 1270 and 1577 nm, corresponding to the upstream and downstream channels, respectively.

A polarization tolerant optical receiver is a key building block for the development of wavelength division multiplexing based high-speed optical data links. However, the design of a polarization independent demultiplexer is not trivial. In this Letter, we report on the realization of a polarization tolerant arrayed waveguide grating (AWG) on a 300-mm silicon nitride (SiN) photonic platform. By introducing a series of individual polarization rotators in the middle of the waveguide array, the polarization dependence of the AWG has been substantially reduced. Insertion losses below 2.2 dB and a crosstalk level better than -29 d B has been obtained for transverse electric and transverse magnetic polarizations on a four-channel coarse AWG. The AWG temperature sensitivity has also been evaluated. Thanks to the low thermo-optical coefficient of SiN, a thermal shift below 12 pm/°C has been demonstrated.

Recently, erbium-doped integrated waveguide devices have been extensively studied as a CMOS-compatible and stable solution for optical amplification and lasing on the silicon photonic platform. However, erbium-doped waveguide technology still remains relatively immature when it comes to the production of competitive building blocks for the silicon photonics industry. Therefore, further progress is critical in this field to answer the industry's demand for infrared active materials that are not only CMOS-compatible and efficient, but also inexpensive and scalable in terms of large volume production. In this work, we present a novel and simple fabrication method to form cost-effective erbium-doped waveguide amplifiers on silicon. With a single and straightforward active layer deposition, we convert passive silicon nitride strip waveguide channels on a fully industrial 300 mm photonic platform into active waveguide amplifiers. We show net optical gain over sub-cm long waveguide channels that also include grating couplers and mode transition tapers, ultimately demonstrating tremendous progress in developing cost-effective active building blocks on the silicon photonic platform.

Wideband and polarization-independent wavelength filters with low sensitivity to temperature variations have great potential for wavelength division multiplexing applications. However, simultaneously achieving these metrics is challenging for silicon-on-insulator photonics technology. Here, we harness the reduced index contrast and the low thermo-optic coefficient of silicon nitride to demonstrate waveguide Bragg grating filters with wideband apolar rejection and low thermal sensitivity. Filter birefringence is reduced by judicious design of a triangularly shaped lateral corrugation. Based on this approach, we demonstrate silicon nitride Bragg filters with a measured polarization-independent 40 dB optical rejection with negligible off-band excess loss, and a sensitivity to thermal variations below 20 pm/°C.

The successful integration of capacitive phase shifters featuring a p-type strained SiGe layer in a 300 mm silicon photonics platform is presented. The phase shift is evaluated with a voltage swing of only 0.9 V pp , compatible with CMOS technology. A good correlation is shown between the phase shift efficiency from 10 to 60°/mm and the capacitive oxide thickness varying from 15 to 4 nm. Corresponding insertion losses are as low as 3 dB/mm thanks to the development of low loss poly-silicon and to a careful design of the doped layers within the waveguide. The thin SiGe layer brings an additional 20% gain in efficiency due to higher hole efficiency in strained SiGe.

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

In this work, a 25 Gb ps silicon push-pull Mach-Zehnder modulator operating in the O-Band (1260 nm - 1360 nm) of optical communications and fabricated on a 300 mm platform is presented. The measured modulation efficiency (VπLπ) was comprised between 0.95 V cm and 1.15 V cm, which is comparable to the state-of-the-art modulators in the C-Band, that enabled its use with a driving voltage of 3.3 V pp , compatible with BiCMOS technology. An extinction ratio of 5 dB and an on-chip insertion losses of 3.6 dB were then demonstrated at 25 Gb ps.