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A radio frequency (RF) reflectometry technique is presented to measure device capacitances using a probe station. This technique is used to characterize micro-electromechanical system (MEMS) variable capacitor devices that can be connected to create pull-up and pull-down networks used in digital gates for reversible computing. Adiabatic reversible computing is a promising approach to energy-efficient computing that can dramatically reduce heat dissipation by switching circuits at speeds below their RC time constants, introducing a trade-off between energy and speed. The variable capacitors in this study will be measured using single port RF reflectometry achieved with a custom-made RF probe. The RF probe consists of a micromanipulator with an on-board matching network and is calibrated by measuring a capacitive bank that shows a clearly visible frequency shift with the increase in capacitance. The RF probe worked well when measuring static capacitors with no parasitic resistance; however, the frequency shift is masked when measuring the MEMS variable capacitors due to their high in-series parasitic resistance (around 80 kΩ). Therefore, RF reflectometry has the potential to measure MEMS variable capacitors in the range of 0–30 fF when not masked by a high in-series parasitic resistance, creating a fast and versatile method for characterizing variable capacitors that can be used in energy-efficient computing. [ABSTRACT FROM AUTHOR]

Comparison of the switching signals from the Fe(super III)-Ru(super II) cell [C][X] to that of the Ru(super III)-Ru(super II) cell with larger d1/d(sub m)[PF6](sub 3) shows that increasing the length of the conjugated linker between the metal sites can increase the dipolar switching field. A simple electrostatic model suggests that the smaller is the counterion, the greater is the perturbation of the metal sites and the larger is the barrier for switching.

A quantum-dot cellular automata(QCA) latch is an elementary building block, which can be used to build shift registers and logic devices for clocked QCA architectures. The operation of a QCA latch and a shift register, are discussed, and the analysis and presentation of the types and properties of errors encountered in their operation are presented.

Single-electron tunneling transistors (SETs) and boxes (SEBs) exploit the phenomenon of Coulomb blockade to achieve unprecedented charge sensitivities. Single-electron boxes, however, despite their simplicity compared to SETs, have rarely been used for practical applications. The main reason for that is that unlike a SET where the gate voltage controls conductance between the source and the drain, an SEB is a two terminal device that requires either an integrated SET amplifier or high-frequency probing of its complex admittance by means of radio frequency reflectometry (RFR). The signal to noise ratio (SNR) for a SEB is small, due to its much lower admittance compared to a SET and thus matching networks are required for efficient coupling ofSEBs to an RFR setup. To boost the signal strength by a factor of N (due to a random offset charge) SEBs can be connected in parallel to form arrays sharing common gates and sources. The smaller the size of the SEB, the larger the charging energy of a SEB enabling higher operation temperature, and using devices with a small footprint (<0.01 µm2), a large number of devices (>1000) can be assembled into an array occupying just a few square microns. We show that it is possible to design SEB arrays that may compete with an SET in terms of sensitivity. In this, we tested SETs using RF reflectometry in a configuration with no DC through path ("DC-decoupled SET" or DCD SET) along with SEBs connected to the same matching network. The experiment shows that the lack of a path for a DC current makes SEBs and DCD SETs highly electrostatic discharge (ESD) tolerant, a very desirable feature for applications. We perform a detailed analysis of experimental data on SEB arrays of various sizes and compare it with simulations to devise several ways for practical applications of SEB arrays and DCD SETs. [ABSTRACT FROM AUTHOR]

Single-electron tunneling transistors (SETs) and boxes (SEBs) belong to the family of charge-sensitive electronic devices based on the phenomenon of Coulomb blockade. An SEB is a two-terminal device composed of "leaky," C j , and "non-leaky," C g , nanoscaled capacitors in series. At low temperatures, the charge at the common node is quantized and can only be changed near energy-population degeneracy points, resulting in periodic oscillations of the SEB admittance as a function of voltage applied to C g . In comparison to the SETs, SEBs have higher operating temperature, are electrostatic discharge tolerant, and have a much smaller footprint. To monitor the SEB admittance, Radio Frequency reflectometry can be used. To improve the signal-to-noise ratio, limited by the small change in admittance in an SEB, multiple devices sharing the same source and gate electrodes are connected in parallel to form arrays of SEBs. Due to unavoidable random offset charges, the signal boost for an array of N SEBs is expected to be ∼ N. We experimentally demonstrate that by carefully choosing the operating point, the response to the voltage on the sensing gate can be enhanced, for small arrays scales, by a factor approaching N and, thus, provides a method by which these devices can be used in practical sensing applications, such as a scanning probe. [ABSTRACT FROM AUTHOR]

The electron exchange between Fe and Ru sites of the array of dinuclear mixed-valence complexes at energy equalization generates a fluctuating dipole that produces a maximum capacitance versus voltage curve for each complex-counterion combination present. Passage through the capacitance maximum corresponds to switching of the molecular quantum cellular automata cell array by the electric field from the Fe(super III)-Ru(super II) configuration to the Fe(super II)-Ru(super III) configuration.

Recent work on fabricating metal-insulator-metal (MIM) single electron transistors (SETs) using deposited dielectrics shows promise for becoming a manufacturable process due to compatibility with modern CMOS processes. This process, the "rib-SET" process [V. Joshi, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 26, 2587 (2008); G. Karbasian, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 33 (2015)], features a self-aligned island and should allow for scaling SETs below 10 nm. However, one of the biggest roadblocks in realizing a high-quality SET with this process has been difficulties in developing high-quality, low-noise, MIM tunnel junctions. In this work, the authors report Pt-SiO2-Pt MIM SETs with tunnel barriers deposited by e-beam evaporation as an alternative to atomic layer deposition. There are some challenges in the formation of tunnel barriers via e-beam evaporation that are addressed. It is expected that platinum has a negligible native oxide; however, there is a substantial resistance in as-deposited Pt-SiO2-Pt structures that can be reduced by over 5 orders of magnitude by subjecting the finished devices to an anneal in a hydrogen plasma, suggesting the presence of an interfacial platinum oxide. It is shown that this treatment not only increases the conductance through the SET, but that it is necessary for forming high conductance tunnel barriers that are desired for making low-noise SETs. [ABSTRACT FROM AUTHOR]

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics. [ABSTRACT FROM AUTHOR]

Tunable capacitors based on electrostriction in piezoelectric barriers are presented. Electrostriction leads to a modulation of the piezoelectric barrier layer thickness caused by electrostatic attractive forces between the plates of a capacitor under applied voltage. Using this mechanism, a high range of capacitance values with a high capacitance tuning ratio, and wide tunability are obtained. Furthermore, using this electrostrictive piezoelectric capacitor in the gate stack of a two-dimensional (2D) crystal transistor, such as MoS2 transistor, a higher gate capacitance and an ON-current boost are obtained. This allows the transistor switch to operate at a smaller bias voltage in energy-efficient applications. [ABSTRACT FROM PUBLISHER]

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (~4K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain voltage bias). Transmission electron microscopy cross-sectional images showed that annealing did not significantly change device geometry, but energy dispersive x-ray spectroscopy showed an unusually large amount of oxygen in the bottom platinum layer. This suggests that the atomic layer deposition process results in the formation of a thin platinumsurface oxide, which either decomposes or is reduced during the anneal step, resulting in a tunnel barrier without the in-series native oxide contribution. Furthermore, the difference between ozone- and water-based devices suggests that ozone promotes atomic layer depositionnucleation by oxidizing the surface but that water relies on physisorption of the precursors. To test this theory, devices were exposed to forming gas at room temperature, which also reduces platinum oxide, and a decrease in resistance was observed, as expected. [ABSTRACT FROM AUTHOR]

The authors report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultrathin (≈1 nm) tunnel-transparent SiO2 in Ni-SiO2- Ni tunnel junctions. They show that, as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni- SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultrathin barriers. Using this technique, the authors successfully fabricated MIM SETs with minimal trace of parasitic NiO component. They demonstrate that the properties of the tunnel barrier in nanoscale tunnel junctions (with <10-15 m2 in area) can be evaluated by electrical characterization of SETs. [ABSTRACT FROM AUTHOR]

The fabrication is reported of nanodamascene metallic single electron transistors that take advantage of unique properties of chemical mechanical polishing and atomic layer deposition. Chemical mechanical polishing provides a path for tuning the dimensions of tunnel junctions by adjusting the polish time, surpassing the limits imposed by electron beam lithography and lift-off, while atomic layer deposition provides precise control over the thickness of the tunnel barrier and significantly increases the choices for barrier materials. Single-electron transistor operation of a prototype device was successfully demonstrated at T<1K. [ABSTRACT FROM AUTHOR]

Radio-frequency reflectometry (RFR) is a technique that was developed to characterize the properties of transmission lines by observing reflected waveforms. Today, it is widely used in a variety of applications, ranging from the detection of faulty wires in cables and objects buried in the ground to soil moisture detectors and the measurement of dielectric properties of blood. Recently, one important application of this technique, which requires a very small amount of applied power, was developed for the characterization of electronic nanostructures. In this implementation, a microwave radio-frequency (RF) signal is sent to a resonator coupled to the specimen to be studied. If in a specimen the change of some external parameter (e.g., gate voltage) leads to a change of an active [Figure 1(a)] or a reactive (typically, capacitive) load to the resonator, the self-resonance is affected, resulting in a change of magnitude [Figure 2(a)] and phase of the reflected signal. If an impedance matching condition is achieved, the modification of the specimen parameter (e.g., the increase of its resistance) will lead to a very significant change in the reflection coefficient. Here, we discuss two important applications of the RFR technique on nanoscale devices. [ABSTRACT FROM PUBLISHER]

Heat generation limits the performance of state-of-the-art integrated circuits, originating from the wasteful static CMOS operating principle. Near-term solutions like adiabatic charging for energy recovery and limiting friction-type heat sources provide considerable improvement. However, these methods do not address the ultimate thermodynamic necessity to expel energy related to information loss in the computing process. In emerging beyond-CMOS technologies, this bit erasure heat alone can overwhelm the cooling capacity and set the limits of the computing performance. Therefore, logical information loss is becoming an important factor for digital circuit design, and tools have to be developed for analysis and optimization. This article presents a framework for estimating the amount of information loss in complex logic circuits, demonstrating the method by modeling the irreversible bit erasures in a standard binary adder structure. Binary addition is one of the most often used and highly optimized digital designs, and we estimate the erasure bounds for components on various levels of design abstraction, showing that the actual logic gate implementations have orders of magnitude higher loss than the addition operation itself would require. The method and the results can be used to optimize circuits for a higher degree of logical reversibility and energy conservation. [ABSTRACT FROM AUTHOR]

In this article, the authors investigate chemical mechanical planarization (CMP) of gold. Our experiments show that the oxidizer concentration, hardness of the adhesion layer, and surfactants added to stabilize the slurry are the main factors determining the outcome of the process. A combination of 30% H2O2 solution and an alumina based slurry in 1:3 volumetric ratio along with added sodium dodecyl sulfate and poly(vinyl pyrrolidone) was successfully used to pattern gold in a CMP Damascene process. After fabricating inlaid gold structures with CMP, the authors observed that pattern density, as opposed to feature size, is the major factor in determining the amount of metal thinning in inlaid features. 10 lm lines at 5% density were thinned down by 40 nm, while 150 μm pads at 75% density were recessed by 20 nm. The authors believe that in this process, metal recess, that is a chemical effect, outweighs dishing, a feature-size dependent factor, in controlling the severity of metal thinning. [ABSTRACT FROM AUTHOR]

A novel method for the reduction of subthreshold slope below the room-temperature Boltzmann limit of 60 mV/dec for a field-effect transistor based on negative differential capacitance is proposed. This effect uses electric field induced electrostriction of a piezoelectric gate barrier of the transistor. The mechanism amplifies the internal surface potential over the applied gate voltage. This internal voltage gain mechanism provides an opportunity for steep subthreshold slope switching below 60 mV/decade of the transistor current. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The properties of poly(methylglutarimide) (PMGI) when used as an electron beam resist are investigated. The results show that PMGI, when developed with a weak developer, xylenes, shows contrast higher than 12, which is comparable to the contrast achieved in cold developed poly(methylmethacrylate), and approximately twice as high as the recently achieved PMGI contrast using other developers. Using this high contrast polymer, sub 20 nm features with aspect ratios greater than 30:1 can be readily achieved. In addition to the superior positive tone behavior, this polymer behaves as a negative tone resist at higher exposure doses. Negative resist features as small as 20 nm can be fabricated when methyl isobutyl ketone is used to develop negative tone PMGI. [ABSTRACT FROM AUTHOR]

A novel method for fabricating metal-based single-electron transistors (SETs) is reported that combines a nanoscale island produced via electron beam induced deposition (EBID) of Pt metal with a tunnel barrier dielectric produced via atomic layer deposition (ALD) of alumina (Al2O3). A characteristic nonlinearity in Ids-Vds and Coulomb blockade oscillations of the SET are observed at 300 mK. The versatility of the EBID method provides a way to fabricate 3D structures that could be particularly useful in a number of charge sensing applications and which, combined with the accuracy and precise control that ALD provides for the SET's tunnel barriers, greatly expands the choice of techniques suitable for SET fabrication. [ABSTRACT FROM AUTHOR]

A novel process for silicon single electron transistors (Si-SET) is presented, combining chemical mechanical polishing (CMP) with the advantages of silicon processing. To eliminate effects caused by random distribution of dopants in the island, The Si-SET's doped-Si island is replaced with an aluminum or tantalum island by integrating a metal CMP technique with our nano-encapsulation process. The fabricated hybrid Al-island Si-SET has ∼10 nm silicon on insulator lines as the source and drain leads. It shows characteristic Coulomb blockade oscillations with a charging energy of ∼4 meV. The fabrication results demonstrate the scalability of the SET island and the tunnel junction size in a manufacturable top-down approach. [ABSTRACT FROM AUTHOR]

This article presents a proof-of-concept integration of single electron transistors (SETs) and CMOS devices on a single substrate. Two different complementary metal-oxide-semiconductor (CMOS) voltage amplifiers were designed and fabricated for SET readout: a p-type metal-oxide-semiconductor (PMOS) linear amplifier with off-chip source and drain resistors, and a CMOS inverter, which provides gain with no external components. In both cases, the amplifier was coupled to a SET situated on the same substrate and tested at 1.1 K. The amplifiers must have minimal power dissipation to avoid overheating of the SET. Testing of both the linear and CMOS amplifiers demonstrated amplification of the voltage output of an SET/resistor voltage divider. Coulomb blockade of current in the I-V characteristic of SET and Coulomb blockade oscillations were observed with these amplifiers, demonstrating proof-of-concept of the use of CMOS and SETs together. This may enable future integration of CMOS technology with quantum-dot cellular automata or other novel device and logic types that use SETs for readout. [ABSTRACT FROM AUTHOR]

This report presents a study of the effects of light illumination, from near infrared to blue, on the characteristics of Al/AlOx single-electron transistors (SETs) at low temperatures (0.3–4.2 K). Several effects on the SET conductance are observed when the devices are subjected to light illumination, including changes in the Coulomb blockade oscillation period and amplitude. To determine the origin of the observed effects, SETs with different device geometries were fabricated on semiconducting and insulating substrates. The results show that illumination of semiconducting (Si) substrates leads to the excitation of mobile carriers at the insulator-semiconductor interface that strongly influence the SETs, while the use of wide bandgap insulating substrates (quartz) enables SET operation that is immune to visible light illumination from incident powers of 3 μW/mm2 (flux of about 10 photons/nm2 s for whole visible light spectrum). [ABSTRACT FROM AUTHOR]

This article describes the fabrication process for a silicon single-electron transistor (Si-SET) with tunnel barriers made of thermal silicon dioxide. The fabrication method uses electron-beam lithography, dry etching, and chemical mechanical polishing to make devices with well-defined geometry and good yield. The method introduces chemical mechanical polishing as a key processing technique in the production of nanometer scale features required for the device. The fabricated SETs show charging energies in excess of 20 meV and operating temperatures above liquid nitrogen. All the process steps are fully compatible with the current complementary metal oxide semiconductor (CMOS) technology and combined with the higher operating temperature of the SETs, the fabrication method paves the way for designing of hybrid CMOS-SET architectures. Si-SET can also be a key enabling device for the manufacturable implementation of quantum-dot cellular automata. [ABSTRACT FROM AUTHOR]

In this article, the authors report experimental results of the chemical mechanical polishing (CMP) of silicon dioxide (SiO2) and polysilicon to produce nanoscale features with very smooth surfaces. The sizes of the features polished ranged from 30 to 500 nm. For polysilicon polishing, the nanostructures were defined in positive tone e-beam resist and the pattern was transferred to the oxide substrate using reactive ion etching. These etched nanostructures (70 nm deep trenches) were conformally filled with low pressure chemical vapor deposited polysilicon and polished using a CMP system. Polishing planarized the sample and removed the polysilicon overburden to expose the filled trenches in the SiO2. The polished structures were studied using scanning electron microscopy (cross sections) and atomic force microscopy (surface). The authors report controllable CMP to realize ∼20 nm thick layers after polishing, with rms roughness of ∼0.3 nm. Better control of the CMP process (few nm/min removal rate) was demonstrated by using diluted slurry or pure de-ionized water as the CMP slurry. [ABSTRACT FROM AUTHOR]

We discuss novel nanoelectronic architecture paradigms based on cells composed of coupled quantum-dots. Boolean logic functions may be implemented in specific arrays of cells representing binary information, the so-called quantum-dot cellular automata (QCA). Cells may also be viewed as carrying analogue information and we outline a network-theoretic description of such quantum-dot nonlinear networks (Q-CNN). In addition, we discuss possible realizations of these structures in a variety of semiconductor systems (including GaAs/AlGaAs, Si/SiGe, and Si/SiO2), rings of metallic tunnel junctions, and candidates for molecular implementations. We report the experimental demonstration of all the necessary elements of a QCA cell, including direct measurement of the charge polarization of a double-dot system, and direct control of the polarization of those dots via single electron transitions in driver dots. Our experiments are the first demonstration of a single electron controlled by single electrons. [ABSTRACT FROM AUTHOR]