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The design of single- and double-stage carbon nanotube field-effect transistor (CNTFET) based power gain amplifiers using an experimentally-calibrated compact model of an advanced CNTFET technology is presented. Operating at a frequency of 5.2 GHz, the designed single- and double-stage amplifiers achieve competitive gain and linear performance whereas maintining low-power consumption in comparison to incumbent Si-based amplifier circuits. The employed inductorless amplifier topology eases the implementation in a monolithic process. Furthermore, the single-stage amplifier achieves an outstanding input(output)-third-order intercept point ${IIP}_{3} = {\rm {4.7(6.6)dBm}} $. Moreover, the double-stage CNTFET-based amplifier circuit reaches a competitive gain of $S_{21}\sim {\rm {12.5 dB}} $ among results reported in literature. Finally, the obtained results demonstrate that CNTFET technology is a credible contender for implementing RF amplifier circuits suitable for developing RF systems. [ABSTRACT FROM AUTHOR]

The noise behavior resulting from impact ionization (II) is assessed at room temperature for silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) with box Ge profile, featuring a maximum transit frequency of [f.sub.T] = 80 GHz. The noise parameters (NPs) measured over a wide range of collector-emitter voltages revealed that the weak avalanche model is accurate to capture II noise in examined SiGe HBTs.

Many different methods have been proposed in the literature for the extraction of the thermal resistance of heterojunction bipolar transistors (HBTs). This review presents a detailed evaluation and discussion of several widely used methods. Special emphasis is put on a generalized analysis of the underlying assumptions, suitable operating point range, and necessary measurement effort of each method. The accuracy of each method is determined by applying it to data based on circuit simulations of advanced SiGe and III-V HBT technologies. Experimental data from those technologies are used to highlight practical issues. A guideline for the selection of the most suitable method in practice is also given. [ABSTRACT FROM AUTHOR]

A set of compact physics-based equations are proposed for describing the base-resistance component of silicon-germanium (SiGe) HBTs as a function of geometry. Findings reveal the applicability of the proposed equations to all practically useful emitter aspect ratios.

The threshold voltage variation in Schottky-barrier (SB) MOSFETs with different geometric parameters as well as devices with dopant segregation is examined. A multigate structure has suppressed the threshold voltage variation by improving carrier injection by reducing its sensitivity to the SB height inhomogeneity.

A compact bipolar transistor model called HICUM/L(evel)0 is described, that combines the simplicity of the SPICE Gummel-Poon model (SPGM) equivalent circuits with various improvements from HICUM/L(evel)2. The fundamental model formulation is presented along with a derivation of the most important equations.

The Millionshchikov hypothesis of quasi-normal distribution of fourth-order moments fails for convective conditions where the probability density functions of temperature and vertical velocity fluctuations are skewed. This is shown for aircraft and large-eddy simulation (LES) data, and new closures for fourth-order moments that take the skewness into account are suggested. These new closures are in very good agreement with the data.

Microwave noise performance of p and n-type metal-oxide field effect transistor (MOSFETs) fabricated on the same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters

A 190-GHz mixer-based down-conversion receiver realized in a 130-nm SiGe BiCMOS technology featuring high-speed heterojunction bipolar transistors (HBTs) with ($f_{\text {T}}$ , $f_{\text {max}}$) = (300, 500) GHz is presented. The core part of the receiver consists of a low-noise amplifier (LNA), an active tunable fundamental mixer, an intermediate frequency (IF) buffer amplifier (BA), and an active inverse balun. A wideband, high conversion gain (CG) local oscillator (LO) chain is integrated to make the receiver suitable for applications requiring tunable LO, which contains a multiplier with a multiplication factor of 12 ($\times 12$) and a driver amplifier. To exploit the best possible performance with ultralow dc power consumption ($P_{\text {dc}}$), the mixer and LNA transistors operate at forward-biased base–collector junction voltage ($V_{\text {BC}}$). With a fixed IF frequency at 1 GHz, this receiver exhibits a peak CG of 49 dB with a 14-dB tuning range and a minimum single-sideband noise figure (NF) of 16.5 dB, consuming only 29-mW static dc power for the core part and 171 mW overall, including the LO chain. Within the CG tuning range, this receiver achieves a 6-dB RF bandwidth (BW) from 25 to 32 GHz. Compared with previously reported receivers at similar frequencies, the highest CG and the lowest $P_{\text {dc}}$ with highly competitive performance in terms of BW, CG tuning range, 1-dB output compression point, and NF have been achieved. [ABSTRACT FROM AUTHOR]

A two-valley formulation of 1-D drift-diffusion transport is presented that takes the coupling between the valleys into account via a new approximation for the nonlocal electric field. The proposed formulation is suitable for the simulation of III–V heterojunction bipolar transistors as opposed to formulations that employ the single electron gas approximation with a modified velocity-field model, which also causes convergence problems. Based on Boltzmann transport equation simulations, model parameters of the proposed two-valley formulation are given for GaAs, InP, InAs, and GaSb at room temperature. Applications of the new formulation are also demonstrated. [ABSTRACT FROM AUTHOR]

This article presents an ultra-low-power silicon germanium heterojunction bipolar transistor (SiGe HBT) amplifier operating at 200 GHz. The amplifier consists of three cascaded gain-cell stages and was implemented in an experimental 130-nm SiGe HBT technology with peak $f_{{\textrm {T}}}/f_{\text {max}}$ of 460/600 GHz. In order to achieve the demonstrated extremely low dc power dissipation, the circuit was designed with transistors operating at forward-biased base–collector junction voltage ($V_{\text {BC}}$). With 1.3-V supply voltage ($V_{\text {BC}}\approx 0.2$ V), this amplifier exhibits a peak gain of 23.5 dB at 180 and 205 GHz with 34-GHz 3-dB bandwidth (BW) from 173 to 207 GHz, consuming 3.2-mW static dc power. Even with a supply voltage of 0.7 V ($V_{\text {BC}} \approx 0.5$ V), this amplifier still operates with a peak gain of 18.3 dB at 175 GHz, dissipating an extremely low dc power of 1.73 mW. Compared with the previously reported low-power amplifiers operating around 200 GHz, this article achieves the highest linear gain relative to the dc power consumption with an improvement factor of ten, as well as highly competitive performances in terms of noise figure and 3-dB BW. [ABSTRACT FROM AUTHOR]

The thermal resistance, thermal capacitance, and thermal time constant have been experimentally extracted for the first time for a multi-tube multi-finger carbon nanotube FET (CNTFET) from trap-free high-frequency characteristics by following a methodology based on temperature-dependent two-port network analysis. The extracted short thermal time constant confirms the thermal stability for this emerging technology. A lumped-element electro-thermal model for multi-tube CNTFETs has been developed and proven with experimental data. [ABSTRACT FROM AUTHOR]

This paper focuses on the modeling of the avalanche multiplication coefficient in state-of-the-art SiGe:C HBTs suffering from radical self-heating and impact-ionization effects. Experimental data are measured in a wide current range on devices fabricated during the DOTFIVE project and used as a reference. A comparative analysis of the available empirical descriptions for the avalanche coefficient is made at low current density; the best model is then extended to account for medium/high-current effects by resorting to a suitable parameter optimization methodology. The same procedure is adopted to examine the accuracy of physics-based formulations implemented in advanced transistor models for circuit design. [ABSTRACT FROM AUTHOR]

This paper presents a unified physical formulation for the avalanche effect in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) at different injection levels. Based on an analytical description of the resulting electric-field distribution, a closed-form analytical expression for the multiplication factor is derived and has been implemented in the HICUM compact model. The model accuracy close to and beyond the common-emitter breakdown voltage BVCEO has been assessed over a wide temperature range in comparison to measurements of SiGe HBTs with different collector doping profiles and emitter geometries. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) field-effect transistor (FET) based applications require multiple CNTs with small tube pitches for competing with existing silicon technologies. The associated dense packing of CNTs leads to electrostatic interactions between the tubes also known as screening effects. In this paper, the impact of the latter on the CNT current and charge density has been investigated by means of three-dimensional (3D) device simulation (TCAD), in which the CNT is represented by its actual 3D structure rather than by a one-dimensional (1D) line, allowing to include the effects of an inhomogeneous charge and current density distribution along the CNT circumference. Different analytical models describing the impact of the oxide thickness, CNT diameter and CNT pitch on the oxide capacitance are compared. Using the most accurate model, the dependence of drain current, transconductance, subthreshold slope and transit frequency on the above mentioned parameters has been determined using TCAD simulations. [ABSTRACT FROM AUTHOR]

Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM AUTHOR]

In this paper, we present a thru-reflect-line (TRL) calibration/de-embedding kit integrated in the back-end-of-line of a SiGe technology, which allows direct calibration at the first metallization layer, thus moving the reference planes as close as possible to the intrinsic device. The proposed calibration/ de-embedding kit features capacitively loaded inverted CPW lines, allowing to reduce the losses arising from the conducting (i.e., silicon) substrate, by confining the propagating field in the low-loss dielectric layers. The structures have been designed specifically for (sub) mm-wave measurements, as complementary to conventional de-embedding kits used at lower frequencies. A simplified analytical model is presented to support the design of the capacitively loaded CPW lines. Results of a calibration/de-embedding kit, realized using a 130-nm BiCMOS technology are experimentally obtained in the WR-03 waveguide band. Worst case error bounds providing error below 5% in the entire WR3 band are demonstrated. Comparison between direct calibration and de-embedding using calibration transfer from fused silica are provided to highlight the improvements of the proposed approach in the mm-wave bands. Finally, the TRL calibration kit is employed for S-parameter measurements of a heterojunction bipolar transistor and the results are compared to the HiCUM model of the same transistor for verification. [ABSTRACT FROM AUTHOR]

A new analytical model based on the Wentzel–Kramers–Brillouin approximation for MOSFET-like 1-D ballistic transistors with Schottky-Barrier contacts has been developed for the drain current. By using a proper approximation of both the Fermi–Dirac distribution function and transmission probability, an analytical solution for the Landauer integral was obtained, which overcomes the limitations of existing models and extends their applicability toward high bias voltages needed for analog applications. The simulations of transfer and output characteristics are found to be in agreement with the experimental data for sub-10-nm carbon-nanotube FETs. [ABSTRACT FROM PUBLISHER]

In certain types of heterojunction bipolar transistors (HBTs), the carrier transit time associated with the base-collector (BC) space-charge region constitutes a significant contribution to the total transit time. In many compact models, the low-current BC transit time is lumped in with the total low-current transit time and often assumed to be constant—dependent only on the collector width and material saturation velocity. This assumption, however, is insufficient for modeling high-voltage Si-based HBTs as well as for III-V HBTs, where the negative differential mobility (NDM) effect can become relevant in high-speed low-power circuits. This paper presents a closed-form solution for the low-current collector transit time based on a novel accurate analytical velocity-field formulation, covering both group IV and group III-V semiconductor materials. The new solution includes the NDM effect and is suitable for implementation in compact models, and its relevance and accuracy are demonstrated for both TCAD simulated and measured data. [ABSTRACT FROM PUBLISHER]

This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed. [ABSTRACT FROM PUBLISHER]

This letter presents a 97-GHz downconversion mixer in a 130-nm SiGe HBT technology. For achieving the demonstrated ultralow dc power consumption, the mixer was designed with transistors operating in saturation using an accurate compact model. With 0.7-V supply voltage and −5-dBm local oscillator pumping power, this mixer achieves a double-sideband conversion gain (CG) of 6.6 ± 3 dB over the RF frequency range from 91 to 100 GHz, consuming 12-mW static dc power. With the supply voltage further reduced to 0.5 V, this mixer still works with a maximum upper-sideband CG of 5.2 dB from 94 to 100 GHz, with only 8-mW static power consumption. [ABSTRACT FROM AUTHOR]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

Two-section models for capturing the lateral ac emitter-current crowding effect, which is also known as the lateral nonquasi-static (NQS) effect, are presented following a consistent approach based on a model formulation for ac operating condition. Following the theoretical results, model formulations suitable for implementation in the large-signal domain are developed. The proposed two-section model performs better than the state-of-the-art model in both the large-signal and small-signal domains and appears to be suitable for accurately capturing the lateral NQS effect. [ABSTRACT FROM AUTHOR]

Using a dedicated combination of the non-equilibrium Green function formalism and large-scale density functional theory calculations, we investigated how incomplete metal coverage influences two of the most important electrical properties of carbon nanotube (CNT)-based transistors: contact resistance and its scaling with contact length, and maximum current. These quantities have been derived from parameter-free simulations of atomic systems that are as close as possible to experimental geometries. Physical mechanisms that govern these dependences have been identified for various metals, representing different CNT-metal interaction strengths from chemisorption to physisorption. Our results pave the way for an application-oriented design of CNT-metal contacts. [ABSTRACT FROM AUTHOR]

The junction capacitance of heterojunction bipolar transistors (HBTs) is commonly modeled based on the theory of the p-n-homojunction with constant doping levels, made more flexible by the introduction of adjustable model parameters. In III–V HBTs, however, the low-doped collector is often not uniform, but contains both material and doping steps used to suppress the collector current blocking and to improve the linearity. Under these circumstances, the classical formulation is not sufficient to model the capacitance. Similarly, the exponential spatial doping dependence in the collector of modern high-speed HBTs may require a more in-depth approach. In this brief, a smooth expression for modeling the junction capacitance of a multiregion layer stack is presented. The accuracy of the new model is demonstrated based on both simulated and measured data. [ABSTRACT FROM AUTHOR]

Experimental results gained by various electrical characterization techniques are discussed and compared for a CNTFET technology, which suffers as almost all emerging technologies from traps in the gate oxide. Based on these results, it is highlighted that, contrary to common practice, a fast data acquisition technique is required to ensure a proper electrical device characterization in terms of 1) trap-free device characteristics, 2) reproducible experimental results, and 3) a consistent set of dc and small-signal (ac) characteristics. It is argued that a reasonable technology comparison among emerging technologies must be based on data fulfilling these criteria since trap-affected measurements distort the device behavior which can lead to wrong conclusions about the performance of a device such as the apparent linearity. A trap model capturing the aforementioned issues is briefly introduced. Moreover, the challenges of the electrical characterization of high-impedance devices are explored. [ABSTRACT FROM PUBLISHER]

Reconfigurable field-effect transistors (RFETs) are of interest as devices for dynamically switching between n- and p-type polarity which enables different logic computations using the same hardware. So far, RFETs have been realized with one or even two additional program gates for accomplishing reconfigurability. This paper presents an RFET design with just one single-gate on a silicon nanowire channel. Based on measured and device simulation data of a double-gate (DG) RFET, it is shown that the proposed simplified single-gate (SG) RFET achieves the same functionality and dc characteristics as the more complex DG-RFET. Besides reducing the wiring for the program gate(s), the SG-RFET has the additional advantage of being scalable to smaller channel length and thus achieving higher operating speed. [ABSTRACT FROM PUBLISHER]

For the experimental determination of the emitter resistance of bipolar junction transistors and HBTs, many methods exist in the literature, which yield quite different results though. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations, including different device types (i.e., high-speed and high-voltage transistors). First, the accuracy of the methods is evaluated based on simulated data using a compact model. Explanations for causes of observed inaccuracy or failure are given and discussed. Second, suitable methods are applied to experimental data. In both cases, the results are compared for a large variety of device sizes. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, device size, and operating range; as well as its requirements in terms of equipment and extraction effort. A guideline for extracting the emitter resistance is also given. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors are expected to be beneficial for analog high-frequency applications due to, among others, their inherent linearity and, thus, very low signal distortion. Achieving this linearity has so far been assumed to depend on meeting the following conditions: Ballistic single-subband transport, ohmic contacts, and quantum capacitance limited operation1. However, these conditions are very difficult to meet in realistic devices and circuit applications. It is shown in this paper that high linearity is also possible under significantly relaxed and, in particular, more practical conditions. This paves the way toward the exploration of linearity in realistic devices suffering from carrier scattering in the channel and with Schottky-like contacts, as well as thicker and lower-$\kappa$ gate oxides, which do not allow operation in the quantum capacitance limit. This study is based on results obtained with a Boltzmann transport equation solver that includes tunneling through potential barriers. [ABSTRACT FROM PUBLISHER]

A compact large-signal model, called Compact Carbon Nanotube Model (CCAM), is presented that accurately describes the shape of DC and small-signal characteristics of fabricated carbon nano-tube FETs (CNTFETs). The new model consists of computationally efficient and smooth current and charge formulations. The model allows, for a given gate length, geometry scaling from single-finger single-tube to multifinger multitube transistors. Ambipolar transport, temperature dependence with self-heating, noise, and a simple trap model have also been included. The new model shows excellent agreement with the data from both the Boltzmann transport equation and measurements of Schottky-barrier CNTFETs and has been implemented in Verilog-A, making it widely available across circuit simulators. [ABSTRACT FROM PUBLISHER]