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1. Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and its Effect on Analog Figures of Merit

Author

Lucas Nyssens, Arka Halder, Babak Kazemi Esfeh, Nicolas Planes, Michel Haond, Denis Flandre, Jean-Pierre Raskin, and Valeriya Kilchytska

Subjects
UTBB, FDSOI, MOSFET, self-heating, S-parameters, analog figures of merit, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

Published
2020
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2. 28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Author

Lucas Nyssens, Arka Halder, Babak Kazemi Esfeh, Nicolas Planes, Denis Flandre, Valeriya Kilchytska, and Jean-Pierre Raskin

Subjects
28-nm FD-SOI, UTBB MOSFET, cryogenic CMOS, RF figures of merit, small-signal modeling, liquid helium temperature, Electrical engineering. Electronics. Nuclear engineering, TK1-9971
Abstract

This work presents a detailed RF characterization of 28-nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (ft) and maximum oscillation frequency (fmax), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ~130 GHz in ft and ~75 GHz in fmax is observed for the shortest device (25 nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28-nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

Published
2020
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3. 28-nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements Extraction at Cryogenic Temperature Down to 77 K

Author

Michel Haond, Valeriya Kilchytska, Jean-Pierre Raskin, Babak Kazemi Esfeh, Denis Flandre, Nicolas Planes, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
UTBB MOSFETs, 02 engineering and technology, Cryogenics, 01 natural sciences, RF figures of merit (FoM), Parasitic elements, 0103 physical sciences, MOSFET, Figure of merit, Parasitic extraction, Electrical and Electronic Engineering, RF Figures of Merit (FoM), 010302 applied physics, Physics, Oscillation, business.industry, cryogenic temperature, Cryogenic temperature, parasitic elements, 021001 nanoscience & nanotechnology, Cutoff frequency, FDSOI, Electronic, Optical and Magnetic Materials, Equivalent circuit, Optoelectronics, Radio frequency, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Biotechnology
Abstract

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency ( $f_{T}$ ) and maximum oscillation frequency ( $f_{\max }$ ), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of $f_{\textit T}$ and $f_{\max }$ by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

Published
2019

4. Self-Heating in FDSOI UTBB MOSFETs at Cryogenic Temperatures and Its Effect on Analog Figures of Merit

Author

Jean-Pierre Raskin, Michel Haond, Arka Halder, Lucas Nyssens, Babak Kazemi Esfeh, Valeriya Kilchytska, Nicolas Planes, Denis Flandre, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
analog figures of merit, Materials science, Thermal resistance, Silicon on insulator, 02 engineering and technology, Cryogenics, 01 natural sciences, UTBB, MOSFET, 0103 physical sciences, Figure of merit, S-parameters, Electrical and Electronic Engineering, 010302 applied physics, FDSOI, Self-heating, Analog figures of merit, business.industry, self-heating, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Optoelectronics, lcsh:Electrical engineering. Electronics. Nuclear engineering, Radio frequency, 0210 nano-technology, business, Self heating, lcsh:TK1-9971, Order of magnitude, Biotechnology
Abstract

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

Published
2020

5. 28 FDSOI RF Figures of Merit down to 4.2 K

Author

Valeriya Kilchytska, J-P Raskin, B. Kazemi Esfeh, Lucas Nyssens, Nicolas Planes, Denis Flandre, Arka Halder, and UCL - SST/ICTM/ELEN - Pôle en ingénierie électrique

Subjects
010302 applied physics, Physics, business.industry, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Cutoff frequency, Logic gate, 0103 physical sciences, MOSFET, Optoelectronics, Figure of merit, Equivalent circuit, Parasitic extraction, Radio frequency, 0210 nano-technology, business
Abstract

This work presents a detailed RF characterization of 28 FDSOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current gain cutoff frequency (f T ) and maximum oscillation frequency (f max ), as well as parasitic elements of the small-signal equivalent circuit are extracted from the measured S-parameters. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28 FDSOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

Published
2019

6. Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

Author

Gerard Ghibaudo, X. Mescot, Nicolas Planes, T.A. Karatsori, Charalabos A. Dimitriadis, Sebastien Haendler, Christoforos G. Theodorou, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Materials science, Infrasound, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, MOSFET, Electrical and Electronic Engineering, Lorentzian noise, hot carriers (HCs), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Noise measurement, business.industry, Subthreshold conduction, Flicker noise, Electrical engineering, Time constant, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Amplitude, random telegraph noise (RTN), Optoelectronics, 0210 nano-technology, business, Noise (radio), fully depleted silicon-on-insulator (FD-SOI) MOSFETs
Abstract

International audience; The hot carrier (HC)-induced traps in nanoscale fully depleted ultrathin body and buried oxide nMOSFETs are investigated by low-frequency noise (LFN) measurements in the frequency and time domains. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due to either generation-recombination noise or random telegraph noise (RTN). Based on the LFN results, the effect of the HC stress on fully depleted silicon-on-insulator MOSFETs is investigated after short- and long-time stress. The capture and emission time constants responsible for the RTN noise were calculated as the average duration time of the high/low drain current state, respectively. Analysis of RTN traps detected in fresh and HC-stressed devices indicates that the RTN amplitude is uncorrelated to the trap time constants, i.e., the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above-threshold region.

Published
2016
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7. Characterization and modeling of drain current local variability in 28 and 14 nm FDSOI nMOSFETs

Author

Nicolas Planes, Emmanuel Josse, Sebastien Haendler, Gerard Ghibaudo, E.G. Ioannidis, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015)

Subjects
Materials science, Monte Carlo method, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, law, 0103 physical sciences, MOSFET, Materials Chemistry, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Drain current, 010302 applied physics, Characterization Modeling, Mismatch Variability, Transistor, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Characterization (materials science), 0210 nano-technology, Hardware_LOGICDESIGN
Abstract

In this paper, we present, for the first time, a detailed investigation of the drain current local variability in advanced n-MOS devices from 28 and 14 nm FDSOI technology nodes. A simple MOSFET compact model is built to reproduce the local variability I d – V g characteristics of paired transistors using a Monte Carlo simulation with normally distributed MOSFET parameters ( V th , β and R sd ).

Published
2016
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8. Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Author

Nicolas Planes, Christoforos G. Theodorou, T.A. Karatsori, Charalabos A. Dimitriadis, A. Tsormpatzoglou, Sebastien Haendler, Gerard Ghibaudo, E. G. Ioannidis, Aristotle University of Thessaloniki, Department of Physics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), ARISTEIA II project, and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Materials science, fully depleted silicon-on-insulator (FD-SOI) ultrathin-body and box (UTBB) MOSFETs, Channel length modulation, business.industry, Semiconductor device modeling, Silicon on insulator, Saturation velocity, Electronic, Optical and Magnetic Materials, Threshold voltage, Velocity overshoot, Logic gate, compact model, MOSFET, Electronic engineering, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Back-gate control
Abstract

International audience; An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from -3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

Published
2015
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9. Hot carrier degradation mechanisms of short-channel FDSOI n-MOSFETs

Author

T.A. Karatsori, Sebastien Haendler, Christoforos G. Theodorou, C.A. Dimitriadis, Gerard Ghibaudo, Nicolas Planes, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, Department of Physics, STMicroelectronics [Crolles] (ST-CROLLES), and ARISTEIA II(Project 4154 of the GreekGeneral Secretariat for Research and Technology, co-funded by theEuropean Social Fund and national funds)

Subjects
Materials science, business.industry, 020208 electrical & electronic engineering, Gate dielectric, Electrical engineering, 020206 networking & telecommunications, 02 engineering and technology, Dielectric, [SPI.TRON]Engineering Sciences [physics]/Electronics, Stress (mechanics), Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Degradation (geology), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, AND gate, Communication channel, Voltage
Abstract

session poster; International audience; The HC degradation of nanoscale FD-SOI n-MOSFETs has been investigated under the worst bias stress conditions (Vds,stress = Vgs,stress). At high stress voltages the hot carriers injected into the gate dielectric are the main degradation mechanism, superseding the interface degradation. The proposed degradation mechanisms are supported with the interface and gate dielectric trap properties extracted from LFN measurements.

Published
2015
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10. New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Author

E. G. Ioannidis, Sebastien Haendler, Gerard Ghibaudo, Charalabos A. Dimitriadis, Christoforos G. Theodorou, Emmanuel Josse, Nicolas Planes, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, Department of Physics, NANO2017, and European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012)

Subjects
010302 applied physics, Engineering, business.industry, Transistor, Electrical engineering, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), Threshold voltage, law.invention, [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, law, Logic gate, 0103 physical sciences, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Node (circuits), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Cadence
Abstract

session poster; International audience; A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

Published
2015
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11. Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs

Author

Nicolas Planes, E. G. Ioannidis, Charalabos A. Dimitriadis, Christoforos G. Theodorou, Sebastien Haendler, Gerard Ghibaudo, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, STMicroelectronics [Crolles] (ST-CROLLES), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Physics, Infrasound, 020208 electrical & electronic engineering, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Low frequency, 01 natural sciences, Computational physics, [SPI.TRON]Engineering Sciences [physics]/Electronics, Square root, Rise time, 0103 physical sciences, MOSFET, Dispersion (optics), 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Statistical analysis, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

session B8L-E: Variability and Reliability in advanced MOSFETs; International audience; The impact of the dynamic variability due to low frequency and RTS fluctuations on single MOSFET operation from 28nm FD-SOI technology is investigated for the first time. It is shown that, for small rise time of ramp gate voltage, the drain current characteristics I d (V g ) exhibit a huge sweep-to-sweep dispersion due to the low frequency noise. Such a single device dynamic variability, which scales as the reciprocal square root of device area, is added to the static mismatch contribution and could amount up to ≈30% of static variability sources.

Published
2014
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12. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Author

Nicolas Planes, J. Pradelle, Pierre Perreau, P. Brun, Olivier Weber, Konstantin Bourdelle, Thierry Poiroux, Bich-Yen Nguyen, J. Ducote, Claire Fenouillet-Beranger, Remi Beneyton, R. Bianchini, B. Orlando, Francois Andrieu, A. Margain, L. Tosti, F. Abbate, C. Borowiak, C. Richard, D. Pellissier-Tanon, O. Faynot, C. Richier, T. Benoist, Magali Gregoire, Pascal Gouraud, Frederic Boeuf, Thomas Skotnicki, J. Bustos, Sebastien Haendler, E. Gourvest, Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Recherches sur les lois Fondamentales de l'Univers (IRFU), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay, Unité Commune d'Expérimentation Animale, Institut National de la Recherche Agronomique (INRA), Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA)

Subjects
Power management, Engineering, Materials science, Silicon on insulator, 02 engineering and technology, 01 natural sciences, law.invention, law, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, ComputingMilieux_MISCELLANEOUS, Ground plane, High-κ dielectric, 010302 applied physics, business.industry, Transistor, Electrical engineering, Biasing, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Threshold voltage, Modulation, Logic gate, Optoelectronics, 0210 nano-technology, business
Abstract

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.

Published
2013
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13. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs

Author

Francois Andrieu, Gerard Ghibaudo, Nicolas Planes, Olivier Faynot, Christoforos G. Theodorou, J. Jomaah, Charalabos A. Dimitriadis, Sebastien Haendler, E. G. Ioannidis, Franck Arnaud, Thierry Poiroux, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Aristotle University of Thessaloniki, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Semiconductor device modeling, Silicon on insulator, Charge density, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, CMOS, 0103 physical sciences, MOSFET, Optoelectronics, Flicker noise, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

Published
2012
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14. Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Author

Charalabos A. Dimitriadis, Christoforos G. Theodorou, Sebastien Haendler, Nicolas Planes, Gerard Ghibaudo, E. G. Ioannidis, Franck Arnaud, J. Jomaah, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Aristotle University of Thessaloniki, HERACLEITUS IIco-financed by the European Union (European Social Fund – ESF) and Greeknational funds through the Operational Program ‘‘Education andLifelong Learning’’ of the National Strategic Reference Framework(NSRF), European Project: CT208,Catrene, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, business.industry, Infrasound, Oxide, Electrical engineering, Charge density, Silicon on insulator, Biasing, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), [SPI.TRON]Engineering Sciences [physics]/Electronics, chemistry.chemical_compound, chemistry, Gate oxide, 0103 physical sciences, MOSFET, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract

International audience; Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

Published
2012
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15. Back-gate bias effect on UTBB-FDSOI non-linearity performance

Author

Bertrand Parvais, Michel Haond, Nicolas Planes, Denis Flandre, Jean-Pierre Raskin, Valeria Kilchytska, and B. Kazemi Esfeh

Subjects
010302 applied physics, Total harmonic distortion, Materials science, business.industry, Electrical engineering, Silicon on insulator, Linearity, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Logic gate, 0103 physical sciences, MOSFET, Harmonic, Optoelectronics, Radio frequency, 0210 nano-technology, business, Degradation (telecommunications)
Abstract

This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of “effective body factor” and lesser mobility degradation with increase of the positive back-gate bias.

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16. 28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis

Author

X. Garros, S. Moreau, Olivier Weber, C. Guerin, V. Barral, Magali Gregoire, Xavier Federspiel, N. Rambal, O. Rozeau, J-P. Colinag, Joris Lacord, Francois Andrieu, C. Fenouillet-Beranzer, R. Kies, P. Acosta-Alba, A-S. Royet, E. Ghegin, M. Vinet, Sebastien Kerdiles, P-O. Sassoulas, Franck Arnaud, Gerard Ghibaudo, G. Romano, Remi Beneyton, Nicolas Planes, Perrine Batude, C. Cavalcante, A. Magalhaes, and L. Arnaud

Subjects
010302 applied physics, Random access memory, Materials science, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 021001 nanoscience & nanotechnology, FLOPS, 01 natural sciences, CMOS, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Thermal stability, Static random-access memory, 0210 nano-technology
Abstract

For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It is shown that 500°C 2h thermal budget can be applied on a digital 28nm circuit including State-Of- The-Art Cu/ULK BEOL without yield nor reliability degradation. These results pave the way to the introduction of BEOL between tiers in 3D sequential integration while the thermal budget allowed for the top tier is sufficient to lead to high performance device.

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