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19 results on '"Bourennane , Abdelhakim"'

2. Full-SiC Single-Chip Buck and Boost MOSFET-JBS Converters for Ultimate Efficient Power Vertical Integration

Author

Makhoul, Ralph, Bourennane, Abdelhakim, Phung, Luong Viêt, Richardeau, Frédéric, Lazar, Mihai, Beydoun, Nour, Kostcheev, Sergueï, Godignon, Philippe, Planson, Dominique, Morel, Hervé, Bourrier, David, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Lumière, nanomatériaux et nanotechnologies (L2n), Université de Technologie de Troyes (UTT)-Centre National de la Recherche Scientifique (CNRS), Centro Nacional de Microelectronica [Spain] (CNM), Service Techniques et Équipements Appliqués à la Microélectronique (LAAS-TEAM), This national inter-lab research work received financialsupport from the French National Research Agency (ANR).The project name is 'MUS²-IC' for Monolithic Ultimate powerSwitching cell in SIlicon Carbide (n° ANR-21-CE05-0005),over the period 2022 – 2025. This work was supported byLAAS-CNRS and NanoMat micro and nanotechnologiesplatforms, members of the Renatech french national network., Institute of Computer Science of AGH University of Science and Technology, and ANR-21-CE05-0005,MUSIC,Cellule de commutation de puissance ultime en carbure de silicium(2021)

Subjects
VDMOS, JBS diode, metallic via, [SPI.NRJ]Engineering Sciences [physics]/Electric power, electroplating process, Power switching cells, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, monolithic, 2D simulations, TCAD Modeling
Abstract

International audience; This paper aims at demonstrating the relevance of a new design perimeter for power switching cells through a monolithic vertical integration approach on a multi-terminal power chip with Wide-Band Gap material such as 4H silicon carbide (SiC). Multi-terminal monolithic architectures making use quasi-only of vertical unipolar switch (VDMOS) and JBS diode architecture within the context of a 600V/10A full integration of switching cells on 4H-SiC chips are proposed and validated through Sentaurus 2D numerical simulations. The key method to etch and to fill the metallic via needed to connect the VDMOS and the JBS from top to back side of the SiC wafer is presented. The first optimization of the electroplating process resulted in a Ni metal layer of about 5µm thick.

Published
2023

3. Fuse on PiN silicon diode monolithic integration for new fail-safe power converters topologies

Author

Oumaziz, Amirouche, Richardeau, Frédéric, Bourennane, Abdelhakim, Sarraute, Emmanuel, Imbernon, Éric, Ghannam, Ayad, Richardeau, Frédéric, Convertisseurs Statiques (LAPLACE-CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Service Techniques et Équipements Appliqués à la Microélectronique (LAAS-TEAM), 3DiS Technologies, and Serge Pierfederici and Jean-Philippe Martin - Editors

Subjects
monolithic integration, TCAD, Short-Circuit, [SPI.NRJ]Engineering Sciences [physics]/Electric power, fuse, Safety Design, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, fail-safe converter, short-circuit protection, safe inverter leg, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; In this paper, a first concept of monolithic integration of a fuse on a silicon PiN diode is realized and experimentally characterized. An integrated fuse on PiN diode allows fast cutoff , with low I²T (less than 2 A².s) and short pre-arcing times (4 to 6 µs). These fuse-on-diode components are intended for failsafe topologies power converter, aiming for more compact and reliable applications. The fuses were electrothermally designed using Comsol Multiphysics™ and TCAD Sentaurus™ simulations were carried out to study their integration on PiN diodes. Characterization and experimental tests were carried out after components realization.

Published
2022
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4. Switching Cells and Power Devices - An Introduction

Author

Richardeau, Frédéric, Bourennane, Abdelhakim, Université de Toulouse (Université de Toulouse), Centre National de la Recherche Scientifique (CNRS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Laboratoire d'analyse et d'architecture des systèmes (LAAS), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J), Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), and Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole)

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018

5. Realization of a Monolithic Multi-Terminal Si-Power Chip Integrating a 2-Phase Rectifier Composed of Vertical PIN Diodes Insulated by Vertical P+Walls

Author

Lale, Adem, Bourennane, Abdelhakim, RICHARDEAU, Frédéric, Tahir, Hakim, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Convertisseurs Statiques (LAPLACE-CS), Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
[SPI.NRJ]Engineering Sciences [physics]/Electric power, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; This paper is within the context of mixed monolithic/hybrid integrationof a generic multi-phase power converter (DC/AC or AC/DC). The technological results provided in this paper deal with the realization of a 300m deep P+wallas well as with the realization ofthe monolithic 2-phase rectifier that consistsof four verticalPiN diodes that are separatedby P+walls.These technological results are currently in use for the realization of a three terminal common cathode chip consisting of two RC-IGBTs as well as a monolithic H-bridge converter that consists of four RC-IGBTs.

Published
2018

6. Bipolar AC (Bipac) Switch With Buried Layer for Specific AC Mains Applications.

Author

Rizk, Hiba, Bourennane, Abdelhakim, Breil, Marie, and Laur, Jean-Pierre

Subjects
*POWER semiconductor switches, *BIPOLAR transistors, *TRANSISTORS, *COMPUTER architecture, *AC DC transformers, *LOGIC circuits
Abstract

A new vertical bipolar bidirectional switch (Bipac) with a buried layer is proposed for specific ac mains applications (230 V–50 Hz). It is mainly dedicated for the low load current ones (0.5 Arms) and must support a voltage of 750 V in the blocking state. Moreover, the Si-chip area must not exceed 10 mm2. The study of the new proposed Bipac structure is carried out using 2-D Sentaurus physical simulation. The operating principles are first validated, and then the physical and geometrical parameters of the buried layer are determined to meet the specifications. As compared to the classical Bipac, the Bipac with a buried layer exhibits a much higher current gain that makes it more attractive in replacing the triac in the targeted applications. [ABSTRACT FROM AUTHOR]

Published
2020
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7. Realisation and characterisation of compact generic IGBT-based multiphase power converters using the two-chip multi-pole integration approach

Author

Lale, Adem, Videau, Nicolas, El Khadiry, Abdelilah, Bourennane, Abdelhakim, Richardeau, Frédéric, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse 1 Capitole (UT1)-Université Toulouse - Jean Jaurès (UT2J), Convertisseurs Statiques (CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, ANR, LAAS-CNRS / LAPLACE-CNRS, ANR-13-JS09-0008,ConvPlUS,Intégration ultime d'un système multicellulaire de commutation de puissance sur puce multi-pôles silicium.(2013), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Convertisseurs Statiques (LAPLACE-CS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Université de Toulouse (UT)-Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP)

Subjects
reverse conducting-IGBT (RC-IGBT), device simulation, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_INTEGRATEDCIRCUITS, monolithic switching cells, stray inductance measurement, Hardware_PERFORMANCEANDRELIABILITY, Power integration
Abstract

International audience; This paper deals with the integration of power converters. The proposed integration approach combines both monolithic integration in silicon and hybrid integration on a DBC/PCB substrate. This new approach allows to devise new power converter assemblies that are of higher performance and reliability as compared to the conventional one. In this paper we present the « two-chip » multi-pole integration approach that integrates a multi-phase converter within two generic monolithic macro-chips. To validate the approach, a common anode macro-chip and two RC-IGBTs were judiciously assembled on PCB substrate to realize a first setup designed as a H-bridge generic converter. First characterization results of the converter are provided in static and switching modes.

Published
2015

8. Three Multiterminal Silicon Power Chips for an Optimized Monolithic Integration of Switching Cells: Validation on an H-Bridge Inverter.

Author

Lale, Adem, Bourennane, Abdelhakim, Richardeau, Frederic, and Videau, Nicolas

Subjects
*PRINTED circuits, *SILICON, *BIPOLAR transistors, *ELECTRIC inductance, *PIN diodes
Abstract

This article deals with the monolithic integration in silicon of a multiphase static power converter (dc/ac or ac/dc) for medium power applications, from few kilowatts to few tens of kilowatts with power devices’ blocking capability in the range of 600–1200 V. This article presents an original three-chip integration approach that combines both monolithic integration in silicon and printed circuit board (PCB) packaging process and takes advantage of both silicon-level technology and PCB-level technology within a limited and well-mastered complexity. The converter is integrated within only three new multiterminal power chips, which are then judiciously packaged on a PCB so as to minimize the switching cell stray inductance and the impact of voltage variations (dv/dt) across the common-mode stray capacitance of the assembly. The static and the dynamic operating modes of the proposed multiterminal power chips were validated using 2-D-Sentaurus TCAD simulations. The realized chips were packaged on a PCB to realize both classical and three-chip-based H-bridge inverters. First characterization results validate the electrical operating modes of the H-bridge inverter realized according to the three-chip approach. [ABSTRACT FROM AUTHOR]

Published
2019
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9. Bipolar AC Switch for Specific Mains Applications: Design, Realization, and Characterization.

Author

Rizk, Hiba, Bourennane, Abdelhakim, Breil, Marie, and Laur, Jean-Pierre

Subjects
*POWER semiconductor switches, *STANDARD hydrogen electrode, *ELECTRIC potential, *TRANSISTORS, *BIPOLAR transistors, *SEMICONDUCTOR devices
Abstract

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

Published
2019
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10. Analysis and optimization of a novel high voltage striped STI-LDMOS transistor on SOI CMOS technology

Author

Toulon, Gaëtan, Cortes, Ignacio, Morancho, Frédéric, Bourennane , Abdelhakim, Isoird, Karine, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)

Subjects
SOI, safe operating area, TCAD simulations, gate-to-drain capacitance, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Shallow Trench Isolation, LDMOS transistor
Abstract

International audience; This paper analyses the static and dynamic characteristics of a novel n-type lateral-double-diffused MOS (LDMOS) with a striped Shallow Trench Isolation (STI) structure - called Striped STI-LDMOS - for switching applications in the 100-150 voltage range by means of 3D TCAD numerical simulations. The proposed structure based on a 0.18μm SOI CMOS technology and defined with STI strips and gate field plate fingers located on top of the defined STI, exhibits much lower gate-to-drain (CGD) capacitances and gate charge (Qg) and a better electrical safe operating area (SOA) as compared with a conventional STILDMOS counterpart.

Published
2012

11. Impact of a backside Schottky contact on the thyristor characteristics at high temperature

Author

Toulon, Gaëtan, Bourennane , Abdelhakim, Isoird, Karine, Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), SYRENA, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT), and Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole)

Subjects
high temperature, High voltage thyristor, TCAD simulations, Schottky contacts, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Pulsed power
Abstract

International audience; In this paper, a thyristor structure presenting improved electrical characteristics at high temperature is analysed through 2D physical simulations. The replacement of the P emitter of a standard symmetrical thyristor by a judicious association of P diffusions and Schottky contacts at the anode side contributes to the reduction of the leakage current in the forward direction and hence improves the forward blocking voltage at high temperature. A fine-tune of the anode side configuration will improve the forward off-state behaviour with only a negligible on-state voltage drop degradation. Moreover, the comparison with the conventional anode short thyristor shows that the insertion of Schottky contacts leads to the same improvements that the anode short in terms of off-state characteristics, while keeping the reverse blocking capability.

Published
2012

12. Multiphase Power Converter Integration in Si: Dual-Chip and Ultimate Monolithic Integrations.

Author

El Khadiry, Abdelilah, Bourennane, Abdelhakim, and Richardeau, Frederic

Subjects
*ELECTRIC current converters, *MONOLITHIC microwave integrated circuits, *INSULATED gate bipolar transistors, *PRINTED circuits, *COMPUTER simulation
Abstract

This paper deals with the monolithic integration of a multiphase generic static power converter (dc/ac or ac/dc). The integration aims at minimizing wire bonds in order to improve the electrical performance as well as the reliability of power converters. To that end, three multiterminal monolithic power Si chips are devised and extensively studied by 2-D simulations. The first power chip integrates the reverse-conducting IGBT devices that compose the high-side part of the converter circuit. This chip is called the common anode and is validated through experimental realizations. The second power chip integrates the reverse-conducting IGBT devices that compose the low-side part of the converter. This chip is called the common cathode chip. The common anode and cathode power chips are judiciously packaged on a Printed Circuit Board substrate over which an insulating Kapton film is laid and through which window openings are realized. The partial flip-chip packaging, of the two power chips, enables the realization of a compact power H-bridge converter with the lowest stray inductance. The third chip integrates the power converter within a single silicon chip and, consequently, eliminates wire bonds. It is considered as the ultimate integration approach. The latter is validated on a monolithic H-bridge inverter by using Sentaurus mixed-mode 2-D numerical simulations. [ABSTRACT FROM AUTHOR]

Published
2016
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18. VDMOS electrical parameters potentially usable as mechanical state indicators for power VDMOS assemblies.

Author

Marcault, Emmanuel, Bourennane, Abdelhakim, Tounsi, Patrick, Breil, Marie, and Dorkel, Jean‐Marie

Abstract

Power device reliability is a multidisciplinary domain. It requires design and integration of sensors, implementation of signal processing algorithms that allow processing the different data provided by the different sensors in order to predict by statistical means the device failure occurrence and consequently anticipate the power device replacement. Currently, for device ageing studies in a laboratory, electrical measurements of device parameters are often used as an indicator of device ageing. Furthermore, smart metal‐oxide semi‐conductor technology integrates more and more sensors that permit to measure quantities such as on‐state resistance or junction temperature of the device. In power vertical diffused metal oxide semiconductor (VDMOS) assemblies, it would be interesting to make use of the VDMOS electrical parameters deviations in order to monitor the ageing state of the power assembly. To that end, we carry‐out in this paper a study mainly based upon electro‐thermo‐mechanical simulations in order to identify the power VDMOS electrical parameters that could be monitored in order to access to the mechanical state of the power assembly and therefore anticipate the assembly failure. The power VDMOS Ron as well as zero temperature coefficient (ZTC) point are of interest because they are sensitive to mechanical stress. Consequently, in this paper, a procedure to minimise temperature impact on the Ron of the VDMOS transistor such that one could use the Ron as mechanical state indicator is shown. Another solution that makes use of a specific operating point of VDMOS (ZTC) which is temperature independent is also studied by simulations and experiment. [ABSTRACT FROM AUTHOR]

Published
2014
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19. Analysis and Optimization of a Thyristor Structure Using Backside Schottky Contacts Suited for the High Temperature.

Author

Toulon, Gaetan, Bourennane, Abdelhakim, and Isoird, Karine

Subjects
*THYRISTORS, *SCHOTTKY effect, *HIGH temperatures, *HIGH voltages, *SILICON, *STRAY currents
Abstract

In high current, high voltage, high temperature (T>125^\circC) power applications, commercially available conventional silicon thyristors are not suited because they present high leakage current. In this context, this paper presents a high-symmetrical (voltage) thyristor structure that presents a lower leakage current and higher breakover voltage as compared with the conventional thyristor at T>125^\circC. It is shown through 2-D physical simulations that the replacement of the P-emitter of a standard symmetrical thyristor by a judicious association of P diffusions and Schottky contacts at the anode side contributes to the reduction of the leakage current in the forward blocking state at high temperature. A fine tune of the anode side configuration will improve the forward OFF-state behavior with only a negligible ON-state voltage drop degradation. Moreover, the comparison with the conventional anode short thyristor shows that the insertion of Schottky contacts leads to the same improvements in terms of OFF-state forward breakover voltage and leakage current and also presents a high reverse blocking voltage. [ABSTRACT FROM PUBLISHER]

Published
2013
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