Analysis and optimization of a novel high voltage striped STI-LDMOS transistor on SOI CMOS technology

International audience; This paper analyses the static and dynamic characteristics of a novel n-type lateral-double-diffused MOS (LDMOS) with a striped Shallow Trench Isolation (STI) structure - called Striped STI-LDMOS - for switching applications in the 100-150 voltage range by means of 3D TCAD numerical simulations. The proposed structure based on a 0.18μm SOI CMOS technology and defined with STI strips and gate field plate fingers located on top of the defined STI, exhibits much lower gate-to-drain (CGD) capacitances and gate charge (Qg) and a better electrical safe operating area (SOA) as compared with a conventional STILDMOS counterpart.