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In this paper, we propose a SiC LDMOS structure with a step compound drift region (SC-LDMOS). The proposed device has a compound drift region which consists of an n-type top layer, a step p-type middle layer and an n-type bottom layer. The step p-type middle layer can introduce two new electric field peaks and uniform the distribution of the electric field in the n-type top layer, which can modulate the surface electric field and improve the breakdown voltage of the proposed structure. In addition, the n-type bottom layer is applied under the heavy doping p-type middle layer，which contributes to realize the charge balance. Furthermore, it can also increase the doping concentration of the n-type top layer, which can decrease the on resistance of the proposed device. As a simulated result, the proposed device obtain a high BV of 976 V and a low R sp,on of 7.74 mΩ·cm 2 . Compared with the conventional single REUSRF LDMOS and triple RESURF LDMOS, BV of proposed device is enhanced by 42.5% and 14.7%, respectively and R sp,on is reduced by 37.3% and 30.9%, respectively. Meanwhile, the switching delays of the proposed device are significantly shorter than the conventional triple RESURF LDMOS. [ABSTRACT FROM AUTHOR]

A silicon-on-insulator (SOI) lateral double-diffused MOSFET (LDMOSFET) with a buried field plate (BFP-LDMOS) is proposed. Its characteristics are studied using 2-D simulations. The proposed structure features double buried field plates which are surrounded by buried oxide (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents a premature breakdown at the interface of the silicon/BOX and enhances the dielectric field. The source buried field plate (SBFP) introduces a new electric-field peak and modulates the distribution of the horizontal electric field. In addition, the BFPs replace part of the BOX, which is useful to minimize self-heating effects (SHE). According to the simulation results, compared to a conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V. The specific on-state resistance ( R on,sp ), however, decreases from 20.46 mΩ cm 2 to 18.50 mΩ cm 2 . Moreover, the maximum lattice temperature at 1 mW/μm and V gs = 10 V is reduced by 33.8 K compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

In this paper, a SiC LDMOS with double L-shaped buried oxide layers (DL-SiC LDMOS) is investigated and simulated. The DL-SiC LDMOS consists of two L-shaped buried oxide layers and two SiC windows. Using 2-D numerical simulation software, Atlas, Silvaco TCAD, the breakdown voltage, and the self-heating effect are discussed. The double-L shaped buried oxide layers and SiC windows in the active area can introduce an additional electric field peak and make the electric field distribution more uniform in the drift region. In addition, the SiC windows, which connect the active area to the substrate, can facilitate heat dissipation and reduce the maximum lattice temperature of the device. Compared with the BODS structure, the DL-SiC LDMOS and BODS structures have the same device parameters, except of the buried oxide layers. The simulation results of DL-SiC LDMOS exhibits outstanding characteristics including an increase of the breakdown voltage by 32.6% to 1220 V, and a low maximum lattice temperature (535 K) at room temperature. [ABSTRACT FROM AUTHOR]

In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current ( I ON ) and reduce the OFF-leakage current ( I OFF ). We find that reduction of the initial energy barrier between the source and channel is the origin of this I ON enhancement. The reason for the I OFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance ( C gg ) and decreasing the intrinsic delay (τ). [ABSTRACT FROM AUTHOR]

The performance for P + Sidewall Trigate Junctionless nanowire MOSFET is investigated. The new device has a P + sidewall near the source. A comprehensive device comparison includes the subthreshold slope (SS), Drain-induced barrier lowering (DIBL) and the stability for threshold voltage (V TH ). High performance for SS and low leakage currents can be achieved by P + sidewall JL. As a result, SS nearly at 70 mV/dec, I ON /I OFF > 10 6 , and DIBL nearly at 60 mV are achieved at L G = 10 nm for P + sidewall JL NMOSFET, which is the highlighting excellent electrostatic performance for trigate JL NW MOSFEETs. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a new silicon-on-insulator superjunction lateral double-diffused MOSFET (SOI SJLDMOS) with a p-trench layer and stepped buried oxide, is investigated using 3D numerical simulation. The p-trench layer and stepped buried oxide distinguish it from a conventional SOI SJLDMOS. The etched buried oxide layer, with its stepped buried -oxide structure, which facilitates a more even electric field distribution via the electric field modulation effect, increases the breakdown-voltage (BV). Furthermore, the p-trench layer improves the doping concentration through compensation depletion, which further decreases the specific on-resistance (R on,sp). The simulation indicates that the new device has a higher BV (increased by 29%) than the conventional SOI SJLDMOS. At the same time, R on,sp decreases by 20% for the on-state for a given drift-region length. Highlights • A new SOI SJ LDMOS with p-trench and stepped buried oxide is proposed. • The p-trench layer for a higher doping concentration and lower on-resistance of the device. • The stepped buried oxide layer modulates the electric field distribution more uniform. • A 29% increase in the breakdown voltage for the SOI BSJ-PT LDMOS device. • A 20% decrease in the specific on-resistance for the SOI BSJ-PT LDMOS device. [ABSTRACT FROM AUTHOR]