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In this paper, we present a temperature and variability-aware Verilog-A-based compact model for simulating Ferroelectric FET. The model captures the rich physics of ferroelectric materials and the important electrical characteristics, such as the history effect, the impact of pulse width and amplitude on threshold voltage, and temperature-dependent degradation of polarization. The impact of variability is also explored regarding reliable operation of the FeFET. The developed model is robust and can accurately capture the experimentally observed trends, such as the change in polarization due to temperature, increased memory window on reading from the back-gate, etc. Further, we discuss two applications of our developed model viz. (a) multi-level-cell storage and (b) FeFET-based array for MAC operations. The designs are tested using the proposed model in commercial SPICE simulator at different temperatures including the effect of variation. Analysis presented in this article reveals that variability and temperature can be detrimental for operation of FeFET-based systems. • We presented impact of temperature and variability on FeFET. • New compact model incorporating these effects • FeFET multi-level cell storage with 8 different states. • 8×8 FeFET crossbar for multiply-and-accumulate (MAC) operation. • Impact of temperature and variability on these applications [ABSTRACT FROM AUTHOR]

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, I d , and maximum transconductance, g m_max , values are demonstrated. Current gain cutoff frequency, f T , increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space). [ABSTRACT FROM AUTHOR]

• An EZFET is a simple and reliable characterization device for substrates and gate stacks. • Junctionless EZFET removes the temperature limitation of junctions activation for low temperature integration applications. • A complete model reproduces the peculiar device behavior. • A simplified parameters extraction methodology provides reliable substrate and gate stack evaluation. • The junctionless EZFET can be used for two-dimensional that cannot be doped. The junctionless EZ-FET is a device with simplified architecture and processing. With only two lithography levels and using regular process steps, it enables fast electrical characterization of semiconductor films on insulators (SOI) with undoped source and drain. An electrical model reproducing the peculiar transfer characteristics of a junctionless EZ-FET is presented in this work. Based on this model, a simplified parameter extraction methodology is proposed and used to access the electrical properties of SOI structures (i.e. threshold voltage, mobility). [ABSTRACT FROM AUTHOR]

• Efficacy of heat removal from channel by different heat sinks in back-end of line studied. • Lowering of thermal resistance demonstrated with increasing sink dimensions. • Tradeoff between RF performance and self-heating reduction needed. • f T degraded more due to increased gate capacitance, f max lesser due to reduced gate resistance. This work compares the effect of different heat sink dimensions in the back-end of line (BEOL) on the self-heating (SH) parameters. To assess the self-heating (SH) parameters, the RF characterization technique is employed, which involves measuring S-parameters across a broad frequency spectrum. In addition to the standard device without a sink, two sinks of different dimensions, both connected to the gate, are considered: one smaller and one bigger in size. We experimentally demonstrate lower self-heating as the sink size increases. By using a smaller and a larger sink, a mean reduction of 4.7% and 8.9% in thermal resistance is observed, showing greater SH reduction with increasing sink size, which is also verified from comparison with previous works. The impact of the sinks on RF figures-of-merit (FoMs), namely the cutoff frequency f T and maximum oscillation frequency f max is investigated. f T is seen to degrade stronger due to increased gate capacitance whereas f max degradation is limited because of reduced gate resistance. [ABSTRACT FROM AUTHOR]

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. [ABSTRACT FROM AUTHOR]

In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI) CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution is expected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixel and the detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters and dedicated post-processing analysis are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device but also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability, the dark count rate and the photon detection probability. A comparison between the efficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flight applications. [ABSTRACT FROM AUTHOR]

Reconfigurable FETs (RFETs) are optimized in planar Fully Depleted (FD) SOI. Their basics, electrostatics and performance are studied and compared with standard 28 nm FDSOI and other RFETs results in the literature. The main challenge for future broad adoption is analyzed and commented. Finally, some tips to improve the performance such as the asymmetric silicidation at source/drain are discussed. [ABSTRACT FROM AUTHOR]

In a MOSFET transistor, the subthreshold swing defines the switching efficiency, and the associated slope factor, or so-called body factor, is a critical parameter in charge-based models. However, in an advanced Fully-Depleted Silicon-On-Insulator (FDSOI) process, the slope factor is influenced by a strong back gate coupling due to a thin buried oxide (BOX). A conventional constant expression cannot describe the slope factor at various back-gate voltages. Therefore, this paper proposes a general slope factor expression for front- and back-gate transfer characteristics of long-channel FDSOI MOSFETs in a strong gate coupling. The proposed expression is a continuous function of the surface potential difference between the front and back sides, which explains the slope factor behavior versus the back-gate voltage. Besides, the systematic study is presented for the front/back interface states. The proposed model is applied to evaluate the down-scaling of FDSOI technologies in terms of the gate-coupled slope factor. The scaling in the buried oxide layer degrades the front slope factor, which a thinner channel or a reverse body bias can compensate for at the cost of a higher vertical electric field. Compared to the SiO2 , the application of high- κ dielectric for the buried oxide layer shows a better stand to the degraded slope factor by the interface states. • The model is proposed for subthreshold swing and slope with strong gate coupling. • The reverse body bias shows the efficient enhancement on the subthreshold swing. • The proposed model gives insight into the down-scaling of FDSOI technology. [ABSTRACT FROM AUTHOR]

Through 3D-TCAD simulations this work aims to demonstrate the benefits of Reconfigurable FETs based on dual doping with respect to the Schottky junctions counterparts using the 28 nm FDSOI platform. These devices feature both N and P dopant species at source and drain to allow for electron and hole symmetrical currents instead of using mid-gap metallic regions. Quasi-static results reveals much larger currents thanks to the enhanced carrier injection with analogous capacitances, leading to faster logic circuits in mixed-mode simulations. Dynamic results also show lower energy-delay products making these devices more efficient and appealing to implement reprogrammable logic. • Dual doped Reconfigurable FETs are functional with two top gates. • Dual doped RFETs have greater currents than Schottky barrier RFETs. • DD RFETs are more immune to manufacturing variability than SB RFETs. • DD RFETs are appealing for 28 FDSOI technology to implement in-situ reprogrammable logic. [ABSTRACT FROM AUTHOR]

In this paper, we present a Verilog-A based compact model for simulating Ferroelectric Fully Depleted Silicon-on-Insulator (Fe-FDSOI) FET. The model can capture the rich physics of ferroelectric (FE) materials and reproduce the important electrical characteristics, such as history effect, the impact of threshold voltage on pulse width and amplitude as well as potentiation–depression characteristics. The FE switching is modeled using Preisach model to capture the Polarization (P)–Voltage (V) characteristics. In addition, we capture the history-dependent minor loop characteristics to obtain multiple states of polarization. This allows the modeling of multiple conductance states, which forms the fundamental prerequisite for neuromorphic applications as well as multi-level non-volatile memories. The underlying baseline FDSOI FET is modeled using the industry-standard BSIM-IMG compact model. The model is then augmented with the physics-based model of FE capacitor to realize Fe-FDSOI FET. Our model is computationally efficient and carefully calibrated to reproduce experimental measurement data. • Fe-FDSOI device is modeled using Preisach equations. • Computationally fast and requires much less memory. • Compact model implemented in Verilog-A • The working of the model is validated through matching of SPICE simulations against experimentally available data. • Design space exploration of our model ranging from simple back-bias dependent IdVg curves to neuromorphic potentiation–depression characteristics is demonstrated. [ABSTRACT FROM AUTHOR]

• Medium thick gate oxide devices with steeper doping profiles on FDSOI. • Enabling gate length scaling and reduce Ron, thus increase Ft and Fmax. • Electron mobility increase due to low channel doping. • Improved switch FoM Coff*Ron/Vmax. In this paper two processes with different source and drain out diffusion into the channel of medium thick gate oxide devices in 22FDX® are compared in terms of HCI reliability (electrical field) and DC/RF performance. The margin to pass HCI reliability of the under-drive device allows a steeper source/drain doping profile which enables further gate length reduction. The steeper doping profile reduces R on significantly while improving the electrostatic behavior due to the longer effective channel. Gate length scaling allows a better trade-off between electrostatic behavior, DC/RF performance, breakdown voltage and reliability. For switch applications the C off *R on,AC /V max figure of merit can be reduced while ft and fmax is increased for power amplifier applications. [ABSTRACT FROM AUTHOR]

With the maturity of CMOS technologies and their use for various digital, analog and RF applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Non-Quasi-Static (NQS) effect is one of them; this paper proposes here to present a pragmatic NQS approach adapted to L-UTSOI model and compared to TCAD simulation, segmented model and experimental data. • Review of different techniques, which are the main motivation of the choice of NQS-RTA approach. • New physical insights included in L-UTSOI model version relative to NQS effect. • NQS-RTA solution is formally illustrated, discussed and compared with TCAD, segmented case and experimental datas. [ABSTRACT FROM AUTHOR]

• Multi-gate FD-SOI qubit MOS devices were electrically characterized. • At deep cryogenic temperatures and in linear regime, oscillations in both the current and the transconductance were observed above threshold. • These are likely related to the formation of one-dimensional sub-bands in the silicon active region. • A compact model taking into account a 1D density of states (DOS) has been developed in order to fathom how the 1D confinement influences both the inversion charge and the transconductance. • Furthermore, the impact of drain voltage was also investigated, showing that the oscillations were smoothed out at high drain biases. Multi-gate FD-SOI qubit MOS devices were electrically characterized. At deep cryogenic temperatures and in linear regime, oscillations in both the current and the transconductance were observed above threshold. These are likely related to the formation of one-dimensional sub-bands in the silicon active region. A compact model taking into account a 1D density of states (DOS) has been developed in order to fathom how the 1D confinement influences both the inversion charge and the transconductance. The impact of temperature was shown to be crucial in order to distinguish the sub-bands contribution to the transconductance oscillations. Furthermore, the impact of drain voltage was also investigated, showing that the oscillations were smoothed out at high drain biases. [ABSTRACT FROM AUTHOR]

The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs . height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11 nm. [ABSTRACT FROM AUTHOR]

As today’s 28 nm FDSOI (Fully Depleted Silicon On Insulator) technology is at the industrialization level, this paper aims to summarize the key advantages allowed by the thin BOX (Buried Oxide) of the FDSOI, through the technology evolution but also new opportunities, among logic applications and extending the possibilities offered by the platform. We will summarize how the advantages provided by the thin BOX have been first explored and developed, and how the back biasing techniques are the key to the outstanding performances provided by the FDSOI at low voltage. Then, as the FDSOI technology is also a solution to develop innovative platforms and applications, we will detail some opportunities. In particular, we will present monolithic 3D integration, ultra-low power devices for IoT (Internet of Things) and ultra-sensitive sensors. [ABSTRACT FROM AUTHOR]

The floating body retention time is investigated on fully depleted SOI devices with UTBOX. The retention is occurring through the junctions and strongly assisted by defects in the junction space charge region during the holding state at a negative gate voltage. For standard devices with a gate overlap, the junction field is high and the dominant mechanism in this case is the generation by band-to-band tunneling. For optimized extensionless devices with lower junction field, the Shockley–Read–Hall generation enhanced by the field and Poole–Frenkel mechanism takes over the band-to-band tunneling. Therefore, reducing the concentration of Si impurities closer to the junctions is the key to approach an ideal retention time only due to band-to-band tunneling with the Si bandgap as the energy barrier for tunneling. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications. [ABSTRACT FROM AUTHOR]

In this work self-heating and its effect on analogue device parameters are compared in 28 nm technology bulk and FDSOI MOS devices. It is shown that for self-heating characterisation in advanced MOSFETs the RF extraction technique is more suitable than the pulsed I – V . It is found that the thermal resistance is ∼3.4 times higher and the temperature rise is ∼2.5 times higher in 28 nm gate length FDSOI than in bulk. However, in spite of stronger self-heating, FDSOI devices outperform bulk over a wide frequency range. Moreover, device parameters degradation with temperature is attenuated in FDSOI transistors. [ABSTRACT FROM AUTHOR]

The back-gate terminal biasing has been used to improve the SRAM cells' performance. In this paper, the impact of back-gate bias on the performance of 22 nm FDSOI SRAM 6T cell is analyzed. The cell is fabricated in the regular well and two back-gate terminals are connected to Pwell and Nwell, respectively. The influences of back-gate bias on the cell are studied by the variations of the metrics of leakage current, read current, static noise margin (SNM) and N -curve under the three back-gate bias combinations. Through measurements and HSPICE simulations, the mechanism of the variations of the cell metrics caused by the changes of the back-gate bias is explained by the shift of electrical characteristics of transistors inside the cell. [ABSTRACT FROM AUTHOR]

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing. [ABSTRACT FROM AUTHOR]

The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of I ON / I OFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films. [ABSTRACT FROM AUTHOR]

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental I d – V g measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness. [ABSTRACT FROM AUTHOR]

This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance g m , the output conductance g d , the intrinsic gain A v and the cut-off frequencies f T and f max . Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, g m – A v analogue metric is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that f T of ∼280 GHz and f max of ∼250 GHz are reachable in the shortest devices. These values are compared to those of the first generation of UTBB devices through the effect of parasitic elements. [ABSTRACT FROM AUTHOR]

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C – V and I – V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction. [ABSTRACT FROM AUTHOR]

This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC and for the first time one RF methods to extract the threshold voltage down to 4.2 K for channel lengths down to 28 nm. Measurements are performed on CMOS transistors integrated in 28 nm Fully Depleted Silicon-On-Insulator (FDSOI). First, two methods based on DC measurement are explained: the constant-current and the second derivative technique. Besides, the gate-channel capacitance derivative method based on RF measurements is presented. Finally, we discuss and compare the advantages and limits of these different methods. [ABSTRACT FROM AUTHOR]

• We demonstrate the feasibility of FDSOI device TCAD simulations down to deep cryogenic temperatures. • Maxwell-Boltzmann carrier statistics is replaced by an analytical approximation for the Fermi-Dirac integral. • The electrostatic is investigated by solving the Poisson equation, whereas the transport is simulated using the Drift-Diffusion model. • We explore the impact of temperature on device performances in linear and saturation regions. • The obtained results are compared to some experimental data. In this paper we demonstrate the feasibility of FDSOI device TCAD simulations down to deep cryogenic temperatures. To this purpose, Maxwell-Boltzmann carrier statistics is replaced by an analytical approximation for the Fermi-Dirac integral with 3D density of states. The device electrostatic is investigated by solving the Poisson equation in 2D, whereas the transport is simulated using the Drift-Diffusion model. We explore the impact of temperature on device performances in linear and saturation regions as well as the impact of short channel effects, accounted for various gate and spacer lengths, at room and deep cryogenic temperatures. Finally, the obtained results are compared to some experimental data, highlighting the role of TCAD simulations in providing insights in device physics and performances. [ABSTRACT FROM AUTHOR]

• RF performances of octagonal inductances integrated at cryogenic temperature. • Experimental cryogenic set-up is presented. • Inductances are modelled by a lumped elements circuit to explain the measurements. This paper investigates the RF performances of octagonal inductors integrated in a Fully Depleted Silicon On Insulator (FD-SOI) technology at cryogenic temperature. The RF performances characterization of passive and active components is a first necessary step towards the design of RF circuits optimized for cryogenic CMOS applications. Among passive components, inductors are key to design low noise amplifier needed for instance in qubits read-out circuit. First, the experimental set-up and the experimental protocol is presented in detail. Then inductance with 0.5nH to 4 nH values are characterized in frequency from room temperature down to 4.2 K and modelled by a lumped elements circuit. We used a simple RLC circuit to describe the self-resonance behaviour. A calculation is proposed for the inductance and the capacitance, whereas the resistance is extracted by DC measurements. This circuit description is improved by including coil proximity and skin effects. We observed that the quality factor is improved by a factor of two at low temperature, thanks to the metal resistivity decreases, in qualitative agreement with DC measurements. We also discussed the limits of the proposed model. [ABSTRACT FROM AUTHOR]

FD-SOI five-gate (5G) qubit MOS devices are electrically characterized in linear regime down to deep cryogenic temperatures. The Lambert-W function is successfully used for the modelling of such 5G MOS devices from subthreshold regime to strong inversion. Its applicability is demonstrated down to deep cryogenic temperatures. The 5G device is modeled as a series of five independent transistors: the "active" one, that directly controls the current, and the "external" ones, that act as access resistances. The Lambert-W function enables to accurately reconstruct the inversion charge and the active channel resistance from weak to strong inversion. This approach allows reproducing the drain current characteristic avoiding the evaluation of the mobility attenuation factors. The main device parameters are extracted versus temperature. Furthermore, the role of different scattering mechanisms has been investigated, underlying the impact of defects for the gates in proximity of source and drain. The experimental characterizations have been completed with some Poisson-solver based simulations, carried out down to cryogenic temperatures. In this regime, Maxwell-Boltzmann carrier statistic has been replaced by an analytical expression of the Fermi-Dirac function. [ABSTRACT FROM AUTHOR]

• Kubo-Greenwood modelling of FDSOI MOSFETs down to deep cryogenic temperatures. • Single set of mobility parameters needed for drain current transfer characteristics description. • Neutral scattering mobility found at small gate length due to increased impact of neutral defects. • Closed-form analytical expression for Coulomb scattering has been developed. A comprehensive Kubo-Greenwood modelling of FDSOI MOS devices is performed down to deep cryogenic temperatures. It is found that a single set of mobility parameters is only necessary to fit the capacitance and drain current transfer characteristics versus temperature for long channel devices. In contrast, in short channel transistors, the neutral scattering mobility component µ N is found to decrease at small gate length due to the increased impact of neutral defects close to source/drain ends whatever the temperature. Moreover, a closed-form analytical expression for the Coulomb scattering has been developed, useful for device compact modelling. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI). [Copyright &y& Elsevier]

Abstract: We investigate in this work an original contact architecture to address 64nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage V DD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption. [Copyright &y& Elsevier]

Highlights: [•] UTBOX nMOSFEts with different spacer lengths and HDD tilt-implantation are studied. [•] Better performance is achieved for longer spacer length device (L UL =20nm). [•] GIDL and the short channel effects are reduced in extensionless structures. [•] Device with L UL =10nm or tilt-implantation shows strong lat. diffusion and worse behavior. [•] Longer spacer length devices are more immunity to the temperature influence. [ABSTRACT FROM AUTHOR]

Abstract: This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high R OFF/R ON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints. [Copyright &y& Elsevier]

Abstract: With the current scenario of different candidates to lead the road to 14nm node and beyond, this work presents a thorough Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the scaling possibilities of Extremely Thin Silicon on Insulator technology (ETSOI) considering the impact of Buried Oxide (BOX) engineering on the electrostatic integrity of devices addressed for the forthcoming technological nodes. The simulations show that the combined use of Ultra Thin BOX (UTBOX) and Ground Plane/Back Bias (GP/BB) plane are enabling techniques to ensure an adequate control of Short Channel Effects (SCEs) in order to extend the roadmap of ETSOI technology down to 11nm node and beyond. BOX engineering also makes possible a redefinition of standard scaling rules relaxing the constraints on L G /T Si ratio with the advantage over Multiple Gate FETs (MuGFETs) based architectures of a fully compatible fabrication process with main stream planar technologies. [Copyright &y& Elsevier]

Abstract: For the first time we performed the CMOS integration on hybrid SOI/Bulk wafers obtained by the local internal dissolution technique of the buried oxide (BOX). We compared the electrical performance of transistors fabricated on hybrid wafers and co-processed Ultra-Thin Body and Buried oxide (UTBB) and bulk silicon wafers. Devices on the FDSOI and bulk parts of hybrid substrates present similar carrier mobility than the references. Moreover, diodes with high forward current are achieved on the bulk part of the hybrid wafers. [Copyright &y& Elsevier]

Abstract: A new parameter extraction methodology based on split C–V is proposed for FDSOI MOS devices. To this end, a detailed capacitance theoretical analysis is first conducted emphasizing the usefulness of the Maserjian function. Split C–V measurements carried out on various FDSOI CMOS technologies show that the Maserjian function exhibits a power law dependence with inversion charge as ∝Qi−2 whatever the carrier type and gate oxide thickness. This feature enables to confirm the validity of a two-parameter simple capacitance model and allows for a reliable MOSFET parameter extraction in FDSOI devices. [Copyright &y& Elsevier]

Abstract: In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at a drain bias superior to the circuit operation alimentation. The several type of ground plane and forward or reverse back biasing do not modify significantly the bipolar breakdown voltage. The thicker EOT gate oxide is more sensible to parasitic bipolar breakdown. Finally, results have been reinforced by using calibrated TCAD simulation tool. [Copyright &y& Elsevier]

Abstract: Power consumption and matching are the principal issues at the 32nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present thin-film technologies (FDSOI, LSOI and bulk+) leading to the integration of single gated thin films devices for 22nm nodes and below. [Copyright &y& Elsevier]

• Lambert-W function-based MOSFET parameter extraction down to cryogenic temperature. • Lambert-W function-based modeling of drain current MOSFET characteristics using classical mobility law down to 4.2 K. • Main FDSOI MOSFET parameters extracted versus temperature and gate length. • Mobility degradation at short channel length due to increased neutral defect scattering. The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28 nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2 K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering. [ABSTRACT FROM AUTHOR]

Poisson-Schrödinger (PS) simulations and an analytical charge model for a back biased FDSOI structure operated at deep cryogenic temperatures have been developed. PS simulations have been conducted down to 0 K, where metallic statistics applies, by replacing the F 0 Fermi integral by a Heaviside function. Considering, as a first approximation, two separated channels for front and back interface, a set of implicit equations has been established based on a single subband scheme within the Airy approach, providing a good description of surface potential, inversion charge and capacitance characteristics of FDSOI structures operated at very low temperature and for various back biases and silicon thicknesses. This analytical charge model is a first step towards a compact model of FDSOI MOSFET for circuit design at cryogenic condition. [ABSTRACT FROM AUTHOR]

Raised source/drain (S/D) or raised extension in fully-depleted-SOI (FDSOI) is necessary to boost saturation current, because of increased resistance from the very thin film. We demonstrate that the choice of raising the extension versus the S/D, will depend upon the maximum achievable mobility in the structure at a 60 nm physical gate length. We also study the effects of minimum BEOL via spacing on performance, and its consequence on choosing a raised extension or S/D. [Copyright &y& Elsevier]

• Self Heating affects advanced CMOS devices degrading their performance. • Variation in output conductance due to self-heating allows for its extraction. • Heat sink in the back-end of line helps in evacuating heat from the transistor. • Using the sink, 15–30% reduction in thermal resistance is observed. This work studies the effect of heat sink in the back-end of line (BEOL) on the self-heating (SH) parameters of transistors in a Fully Depleted Silicon-on-Insulator (FDSOI) technology. The RF characterization technique, which involves S-parameter measurements over a wide frequency range, is used to evaluate SH parameters. Two types of sink configurations in the BEOL are considered; one connected to the gate and the other left floating. We experimentally demonstrate that gate-connected heat sink allows for a reduced self-heating in 22 nm FDSOI devices. Around 15% to 30% reduction in thermal resistance is observed for the gate-connected heat sink in comparison to the floating sink. [ABSTRACT FROM AUTHOR]

• In this work, we have used detailed DC TCAD simulations to explain the complex variations of current and electrostatic potential in different regions of the S-Shaped I D -V D curve. • The Z2-FET is actually the consequence of electrostatic coupling between two pseudo-diodes: N-type Gated region & P+ Drain diode (governed by positive front-gate bias) and P-type Ungated region & N+ Source diode (controlled by negative back-gate bias). • We proposed a surface potential approach (including an empirical formulation of Quasi-Fermi Level) to calculate V ON and V OFF , which are the key parameters of our model. • Following the implementation in Verilog-A, parameter extraction has successfully been performed on experimental data and TCAD simulations. • Finally, we extended the voltage-current model to 1T- DRAM application. • Our approach consists in shifting V ON in accordance with the memory state through an equivalent circuit. • This pragmatic DC and memory model allows further investigation of the design to optimize Z2-FET performances, especially at circuit level. Z2-FET, a partially gated diode, was explored for Electrostatic Discharge (ESD) protection. Its sharp switching behavior is also promising for single-transistor (1T-DRAM) memory application. Based on detailed TCAD simulations, we develop a pragmatic SPICE compact model, including DC and memory operation. The model is validated via TCAD and experimental data. The proposed model reproduces the S-shaped V-I characteristics, the hysteresis and the turn on/off voltages. This model is implemented using Verilog-A and allows to evaluate, through SPICE simulation, the figures of merit for DC, transient and memory operation. It is useful for cell optimization and memory matrix design. [ABSTRACT FROM AUTHOR]

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage V min by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs. [ABSTRACT FROM AUTHOR]

• Straining of FDSOI demonstrated by elastic edge relaxation of a buried SiGe stressor. • Ultra-thin body and ultra-thin BOX wafers fabricated with SiGe under the buried oxide. • Strain imaging shows 0.5% tensile strain in the FDSOI and relaxation of the SiGe layer. • n-channel MOSFETs fabricated in a foundry FDSOI process have 9% higher drive current. We report for the first time the implementation of SiGe buried stressors in the context of research and development of an advanced foundry FDSOI process and the observation of improved transconductance and current drive performance of n-channel FDSOI MOSFETs. Epitaxial SiGe stressors grown by CVD at Applied Materials were incorporated under the buried oxide of 300 mm FDSOI wafers by Soitec using lower temperature SOI bonding, splitting and thinning processes and the wafers were subsequently processed through an FDSOI development line at GLOBALFOUNDRIES. The use of FDSOI with buried stressor under the BOX eliminates the risk of extended defects in the epitaxial SiGe layer penetrating up into the SOI channel and also provides an opportunity to obtain a high level of strain in any semiconductor on insulator. A 70 nm thick SiGe buried stressor with 20% Ge is shown to provide a 10% improvement in I dsat at a fixed I off for n-FETs with 20 nm gate length and transconductance, g m is correspondingly improved by 15%. [ABSTRACT FROM AUTHOR]