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In this study, a 300 °C-annealed 3 × 4 V/ZnO multilayer structure demonstrates the lowest resistivity (3.82 × 10−3 Ω cm) and the highest mobility (18 cm2/V s) among the studied V/ZnO multilayer structures. By measuring the energy bandgap (Eg), work function (Φ), and electron affinity (χ) by ultraviolet photoelectron spectroscopy and photoluminescence analysis, the corresponding energy band diagram at the ZnVxOy/ZnO interface can be constructed. A potential is observed at the ZnVxOy/ZnO interface, which induces the two-dimensional electron gas (2DEG) effect, and this is attributed to the high-mobility conduction path. The potential well directly relates to the Φ difference between the ZnO and ZnVxOy layers, which is determined to be 0.22, 0.46, and −0.1 eV for the as-deposited, 300 °C-annealed, and 500 °C-annealed V/ZnO multilayer structures, respectively. The 300 °C-annealed V/ZnO multilayer structure could possibly have the largest depth in the potential well. This supports the 2DEG mechanism for the high mobility of the 300 °C-annealed V/ZnO multilayer structure.

In addition to the development of the nano-wire device, the vertical gate-all-around (V-GAA) Si nano-tube (NT) device structure is proposed with the promising device performance in this work. The vertical device structure makes the transistor easy to be scaled down continuously to meet the complementary metal-oxide-semiconductor scaling needs of the 10/7 nm technology node and beyond. The NT device with the center hollow structure has the capability to deplete the out-of gate control carriers in the center of the nano-wire device and further results in the better device short channel control. Based on the simulation data, the V-GAA Si NT device can keep the Ion-state current the same and reduce the Ioff-state stand-by power. With the demonstration of the promising device performance, the proposed V-GAA Si NT device can be regarded as one of the most promising candidates for the future application of the sub-10/7 nm logic device.

Based on the stress extraction and measurement by atomic force microscope-Raman technique with the nanometer level space resolution, the high compressive stress about 550 MPa on the Si active region (OD) is observed for the current complementary metal-oxide-semiconductor (CMOS) transistor. During the thermal budget for the standard manufacture process of the current CMOS transistor, the difference of thermal expansion coefficients between Si and Shallow Trench Isolation (STI) oxide results in this high compressive stress in Si OD and further degrades the electron carrier mobility seriously. In order to relax this intrinsic processed compressive stress in Si OD and try to recover this performance loss, the novel process is proposed in this work in addition to the usage of one-side pad SiN layer. With this novel process of additional N-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress about 438 MPa in Si OD can be achieved by the smaller difference of thermal ex...

The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal-oxide-semiconductor field-effect transistors is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si OD region with and without dislocation edge stress treatment is extracted by atomic force microscope-Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the STI intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM-Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agrees well with each other in this work. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines is simulated and investigated clearly. It can be found that longer dislocation line and smaller dislocation angle can relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.

High efficient surface textured SiGe-based solar cell is proposed by the designed top nano-level surface trench structure and the optimized SiGe/Si type-II substrate hetero-junction design. The surface reflectance rate of solar cell can be successfully reduced about 3 times (totally from 32% to ∼10%) by the nano-surface textured structure with obvious photonic crystal effect, simulated by finite differential time domain simulation. With different top surface trench spacing (d) structure design on the nanometer level, broadband antireflection and total absorption rate can be realized and enhanced greatly, respectively. Moreover, SiGe/Si hetero-structure substrate is also implemented to enhance an additional solar cell efficiency about 3% in this work, not only due to the originally higher absorption rate in SiGe-based material but also due to optimized SiGe/Si type-II hetero-structure substrate design. The offset and discontinuousness of the energy band between n+-Si and grown fully strained Si0.9Ge0.1 type-II hetero-junction structure can prevent hole diffusion into the n+-Si layer and have the larger Voc. With the integration of these two key technologies including nano-level surface trench structure design and SiGe/Si type-II hetero-structure optimization, the high efficient (∼18% for the stable production and 21% for the peak record) nano-surface textured SiGe-based solar cell can be achieved and demonstrated in this work.

Transmission line pulse measurements were used to investigate the reliability of the HfO2 dielectric under an electrostatic discharge event. Time-dependent dielectric breakdown of the gate oxide was characterized down to the microsecond time regime. The positive oxide-trapped charges Qot+ were observed beyond a certain electric field and the corresponding centroid evolution was examined. In the high-field stress regime, the field acceleration parameter of the HfO2 dielectric is smaller than that of the silicon oxynitride. We also demonstrated this phenomenon can be attributed to the stronger phonon-assisted tunneling process in the high-k dielectrics.

A metal-oxide-semiconductor tunneling diode is used to emit electroluminescence from a Si/Si0.2Ge0.8 heterojunction. Besides the 1.1 μm and 1.6 μm infrared emission from the band edges of Si and SiGe, respectively, 2 μm infrared emission is also observed due to the radiative recombination between the electrons in the Si conduction band and the holes in the SiGe valence band. This type II recombination can emit photons whose energy is below the SiGe band gap to extend the emission range of Si/Ge-based light-emitting devices. The emission line shape can be fitted by the electron-hole-plasma recombination model.

Secondary-ion mass spectroscopy, energy dispersion spectrometry, and Raman spectroscopy reveal that SiGe dots grown by ultrahigh-vacuum chemical vapor deposition at 600°C exhibit significant intermixing with an average Ge composition of ∼50%. Raman spectroscopy shows the top SiGe quantum dots of the 20-layer sample to be more relaxed than those of the 5-layer samples. As a result, the electroluminescence from the top SiGe quantum dots of the 20-layer sample has the higher peak energy at ∼0.84eV as compared to ∼0.82eV for the 5-layer sample. The external tensile mechanical strain can compensate the built-in compressive strain of SiGe quantum dots and increase electroluminescence energy.

Buckled SiGe films on viscous oxide with different Ge content are studied by wafer bonding and smart-cut process. Compressively strained SiGe layers on the viscous oxide were relaxed to form the buckled state after thermal treatment. Two-dimensional buckling on blanket films is observed. A higher Ge concentration results in a smaller buckling amplitude and a smaller buckling period. Both buckling amplitude and period increase as oxidation time is increased. A small SiGe film (mesa) area can inhibit buckling. Semiempirical analysis gives the critical area size, below which no buckling is observed in the equilibrium states. The critical area size decreases with increasing Ge concentration and decreasing thickness of SiGe films.

The strain effect on the hole mobility is investigated by bulk Si field-effect transistor, substrate-strained Si devices, and these devices under biaxial tensile mechanical strain. The hole mobility along ⟨110⟩ direction on (001) Si substrate degrades at small biaxial tensile strain (