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We investigated the effect of adding small amounts of hydrogen during DC magnetron sputtering of SnO x films followed by annealing in a nitrogen atmosphere at temperatures below the instability of SnO. Hard X-ray photoelectron spectroscopy analysis showed a difference in the initial Sn content in the as-deposited samples, which suggests an increased number of V Sn vacancies. This led to the formation of V Sn -H complexes, resulting in a doubling of the concentration of holes from 5.89 × 1017 cm−3 to 1.38 × 1018 cm−3 and a slight increase in the mobility from 1.17 cm2/(Vs) to 1.45 cm2/(Vs) after annealing. Thermal desorption spectroscopy revealed increased desorption of hydroxyl groups after the addition of hydrogen, indicating that hydrogen presence in the film as OH bonds may be the reason for the undesired increase in SnO2 content and raising of the crystallization point. The average transmittance of the hydrogen-added sample was 10% greater than that of the hydrogen-free sample.

An (AlGa)2O3 back barrier was employed for Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) with a Si-implanted n-Ga2O3 channel layer. The insertion of the back barrier led to strong confinement of electrons in the channel layer, and a shallower pinch-off characteristic with shifting a threshold gate voltage by +8 V was attained for the MOSFET with the back barrier compared to the conventional one without it. The excellent gate controllability represented by a subthreshold slope of 129 mV/decade was also achieved for the back-barrier MOSFET; whereas it was 337 mV/decade for the non-back-barrier one.

The capacitance characteristics of pentacene metal-oxide-semiconductor (MOS) capacitors with a large uncovered pentacene area have been investigated. The capacitance measured was examined by assuming that the uncovered area is represented by a distributed constant circuit. The frequency dependence of the capacitance was reproduced by an equation derived based on the assumption. The sheet resistance for the uncovered area of a MOS capacitor was calculated as a function of the gate voltage from the capacitance measured. The mobility of a MOS capacitor with an uncovered area was estimated by fitting a curve to the gate voltage dependence of the sheet resistance, and was in the range of 0.48-0.64 cm(2) V(-1) s(-1). In addition, the mobilities were compared with those calculated from the current-voltage characteristics of pentacene transistors fabricated on the same substrate.

Three SiN offset spacers were compared regarding the suppression of the gate-edge metamorphoses (GEMs) of scaled TaSiN/HfSiON n-type metal–oxide–semicondutor field-effect-transistors. The offset-spacer-induced GEM appears only in short-channel devices as a high threshold voltage (Vth) and a parasitic resistance. On the basis of the device characteristics, the origin of GEMs was hypothesized to be the negative fixed charge in HfSiON on the gate edges. The low-temperature, Cl-free SiN offset spacer is promising for use in scaled metal/high-k devices because it provides the lowest Vth and the highest drivability, particularly in short-channel devices, by suppressing GEMs.

We demonstrate that electron holography can be used to map the electrostatic potential in source–drain extensions (SDEs) of 30-nm-gate-length metal–oxide–semiconductor field-effect transistors (MOSFETs). To reduce specimen-preparation artifacts, which have prevented the electron holography of advanced MOSFETs, we prepared specimens using low-energy backside Ar ion milling. Our analysis revealed the potential distributions in SDEs formed by a co-implantation technique and those formed by a conventional BF2 implantation technique and showed that the potential change at the p–n junctions is more abrupt in the former. We also show that our electron holography results clearly describe the roll-off characteristics of the MOSFETs.

In this study, the characteristics of Ta/chemical SiO2/Si devices with their chemical oxides formed by various chemicals, including HNO3, SC1, and H2SO4+H2O2 solutions, were first investigated. We found the HNO3 split depicts the lowest leakage current and the best hysteresis behavior. Next, chemical oxide formed by HNO3 was applied to form the interfacial SiO2 layer for metal–oxide–semiconductor (MOS) devices with Ta/HfAlO/chemical SiO2/Si structrue. The effects of a high-temperature spike anneal were then studied. We found that the spike-anneal process can effectively reduce the thickness of the chemical oxide from 10 to 7 A, thus is beneficial in preserving the low effective oxide thickness (EOT) of the structure. Furthermore, both the gate leakage current and stress-induced leakage current (SILC) were also effectively suppressed by the high-temperature spike-anneal.

Analytical formulae for electrostatic potential and electron density profiles in the n-type planar metal oxide semiconductor field-effect-transistor inversion layer are presented. Equations based on the density gradient model are analytically solved using singular perturbation theory. The formulae give good agreement with exact numerical solutions over a broad range of voltages and device structures.

In this paper, we present a novel dry-type glucose sensor based on a metal–oxide–semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance–voltage (C–V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes ΔI before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The ΔI sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

The dependencies of the electrical characteristics of n-metal–oxide–semiconductor field-effect transistors (n-MOSFETs) on the nano-scale Si thickness (

The photodetective characteristics of aluminum grid gate–ultrathin silicon dioxide–silicon structures have been studied. The on–off ratio calculated from the photo and dark current densities rapidly changes at the threshold optical-power density. The threshold optical-power density is controlled by the silicon dioxide film thickness and increases with decreasing silicon dioxide film thickness. The difference between the surface potential with and without light irradiation rapidly changes at the same optical-power density. Holes do not significantly accumulate under optical-power densities lower than the threshold.

This paper presents an inversion capacitance–voltage (C–V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (Rii) model. The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Since the Rii model is scalable with VGS and L, our Rii approach is physically accurate. Due to its simplicity, this method may provide an option for regular process monitoring purposes.

Evaluating the statistical variation of the metal–oxide–semiconductor field-effect transistors (MOSFETs) is important for realizing the accurate analog circuits and highly large-scale-integration (LSI) devices. In this paper, a new evaluation method for the statistical variation of the electrical characteristics of MOSFETs is presented. We have developed the test circuit for understanding the statistical and local variation of MOSFET in very short time. It is demonstrated that a large number of MOSFETs, about 30,000 MOSFETs, are measured in very short time of 0.05 s, and that the measured results are very useful to develop the process technology to reduce the statistical and local characteristic variation.

The double-gate (DG) metal oxide semiconductor field-effect transistor (MOSFET) is considered to be a promising for the next-generation device. We have developed a model describing the short-channel effects of the DG-MOSFET. The model describes suppression of the short-channel effect with the reduction of the silicon layer thickness. Modeling for further suppression of the short-channel effect is achieved by considering the volume inversion effect. The developed model reproduces the suppressed short-channel effect of the DG-MOSFET as a function of the silicon layer thickness down to 10 nm for any gate length with three model parameters.

We previously reported on a decomposition system of organic wastes by the use of thermally excited holes in TiO2 at high temperatures. A good feature of our system is that it makes use of a large number of holes formed, for example, at 350 °C for the oxidation of organic wastes. In this investigation, we aim at applying this technology to the complete decomposition of benzene, toluene, and particulate matter (PM) included in the exhaust of diesel engines. Special attention has been paid to the adsorption process of benzene and toluene onto the surface of TiO2, as well as to their subsequent decomposition, as studied by thermal analysis, Raman spectroscopy, and ESR in consideration of the specific surface of TiO2 powders. Both benzene and toluene are found to completely decompose into H2O and CO2 at about 350 °C, via fragments of ethylene, butene, propene, and butadiene. On the other hand, PM appears more difficult to decompose due to its powdered form. However, PM was finally confirmed to be decomposed when the mixture of PM and TiO2 was heated under a pressure of about 280 N/m2 at about 350 °C.

Ultrathin-channel formation of a vertical-type double-gate metal oxide semiconductor field effect transistor using a low-energy neutral-beam etching (NBE) is proposed. The NBE can completely eliminate charge buildup and photon radiation damage from the plasma. By optimizing NBE conditions, rectangular vertical channels were fabricated with a SiO2 hard mask under low-energy NBE conditions.

A unified model of roughness scattering in single-gate silicon-on-insulator metal–oxide–semiconductor field-effect transistors is proposed based on a formulation suitable for perturbation theory. This unified model includes the roughness scattering model both in bulk MOSFETs and in thin SOI MOSFETs. The SOI-thickness-fluctuation-induced scattering component is naturally derived from the proposed roughness scattering model. The experimentally observed dependence of inversion layer mobility on SOI thickness in thin SOI MOSFETs is explained well by the proposed roughness scattering model.

In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 µm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 µm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 µm showed the longest on-resistance hot-carrier lifetime of 9.34 ×105 s, along with a breakdown voltage of 22 V and an on-resistance of 23 mΩmm2.

We have observed for the first time negative differential conductance (NDC) at room temperature in a silicon single-electron transistor (SET). The device is in the form of an ultranarrow wire channel metal oxide semiconductor field-effect transistor (MOSFET), which acts as a multiple-dot SET and shows large Coulomb blockade oscillations at room temperature. In the finite drain-bias characteristics, double-peak negative differential conductance (NDC) is observed even at room temperature. The reason behind the observed characteristics is considered to be the interplay between the resonant tunneling through a discrete quantum level in the ultrasmall dot and the classical Coulomb staircase effect in another dot.

We propose a carrier-velocity model dependent on the lateral electric field and based on momentum and energy balance equations. The model reproduces the corresponding experimental data more accurately than the previous Sodini's model. Using the carrier-velocity model, we derived an analytical model for expressing drain current. Our drain-current model deviates from Sodini et al.'s model with decreasing gate length. This is attributed to the difference of the carrier-velocity dependence on the lateral electric field; hence, our drain-current model should be more suitable for short-channel devices.

We investigated intrinsic transconductance of carbon-nanotube field-effect transistors (CNTFETs) with carbon nanotubes (CNTs) grown by chemical vapor deposition. The measured transconductance at a drain voltage of -1 V was 8.7 µS for a CNT with a diameter of 1.5 nm. Very high intrinsic transconductance of 20 µS was estimated by considering the contribution of parasitic resistance. Apparent and intrinsic transconductance per unit channel width were 5800 µS/µm and 13000 µS/µm, respectively. These are considerably larger than those for the state-of-the-art Si metal oxide semiconductor field effect transistors (MOSFETs). Parasitic resistance is dominated by the resistance of the CNT portions between the gate and contacts. We expect the performance of CNTFETs will advance further by improving CNT quality and by optimizing device structures.

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

It is demonstrated that the appropriate external mechanical stress applied by the conventional IC chip's package straining can enhance device and circuit performance. A drain current enhancement of 4.9% at saturation is observed for 90-nm-node n-channel metal oxide semiconductor field effect transistor (nMOSFET) under a biaxial tensile strain of 0.096%. The current enhancement is nearly independent of gate width for 90-nm-node logic devices. Moreover, there is a 2.3% speed enhancement for a 90 nm-node logic ring oscillator using a parallel layout under the same biaxial tensile strain of 0.096%.

A trivalued memory circuit based on two cascoded metal–oxide–semiconductor field-effect transistor bipolar-junction-transistor negative-differential-resistance (MOS-BJT-NDR) devices is investigated. The MOS-BJT-NDR device is made of MOS and BJT devices, but it can show the NDR current–voltage characteristic by suitably arranging the MOS parameters. We demonstrate a trivalued memory circuit using the two-peak MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35 µm SiGe process.

A working p-type SiGe double-quantum-well metal–oxide–semiconductor field effect transistor (DQW-pMOSFETs) has been fabricated and characterized. The upper quantum well with 15%-Ge acts as an induced-carrier buffer to slow holes into the Si surface channel and increases the number of high-mobility holes in the 30%-Ge well at the bottom under high gate voltage by improving carrier confinement. DQW devices with a thinner Si-spacer layer between the two SiGe quantum wells exhibit an improved effective hole mobility and wider gate voltage swings but also reduced 1/ f noise levels than Si-controlled pMOSFETs. The DQW has an enhanced carrier confinement compared to a single quantum-well (SQW) device; however, the degradation of mobility and transconductance observed in a sample DQW indicates that this poor transport mechanism may result from an additional hole scattering effect at the Si/SiGe interface.

We report on oxide-channel ferroelectric-gate thin-film transistors (FeTFTs) with the bottom-contact structure for source and drain electrodes. FeTFTs with the bottom-contact structure have faster switching characteristics than those with the top-contact structure, especially for the switching from ON to OFF. First, we confirmed that FeTFTs with the top- or bottom-contact structure exhibit similar ID–VG characteristics and retention properties to each other. Next, we measured the C–V characteristics and confirmed that the oxide semiconductor channel under the source and drain electrodes is depleted in the top-contact structure. This depleted channel impedes the switching from ON to OFF. Finally, we demonstrated that FeTFTs with the bottom-contact structure possess fast switching characteristics for the switching from both OFF to ON and ON to OFF.

The recent progress and development of corundum-structured III-oxide semiconductors are reviewed. They allow bandgap engineering from 3.7 to ∼9 eV and function engineering, leading to highly durable electronic devices and deep ultraviolet optical devices as well as multifunctional devices. Mist chemical vapor deposition can be a simple and safe growth technology and is advantageous for reducing energy and cost for the growth. This is favorable for the wide commercial use of devices at low cost. The III-oxide semiconductors are promising candidates for new devices contributing to sustainable social, economic, and technological development for the future.

We have recently discovered that films of a widely used In–Ga–Zn oxide (IGZO) with have different material composition states when sputter-deposited under different conditions using the same polycrystalline IGZO target. Significant improvements in on-state current and mobility (as high as 40 cm2·V−1·s−1) are obtained. The results of local composition analysis indicate that the deposited film is not composed of any known homogeneous IGZO compound and that the components of this film are separated into two types of nanoparticle regions: one type is composed mainly of GaO x and GaZnO x , which contribute to on/off (switching) characteristics, and the other is composed mainly of InO x and InZnO x , which contribute to on-state characteristics. These regions constitute a new type of oxide semiconductor (OS) film. The nanoparticles with a blurry boundary extend like a cloud, probably complementing one another. We consider that this OS film has a novel composition, which can be described as a “cloud-aligned composite OS” (CAC-OS).

The device characteristics and hot-carrier-induced degradation of high-voltage n-type metal–oxide–semiconductor transistors with traditional and gradual junctions in the drift region are studied in this work. The gradual junction used in this study is realized by self-aligned N− implantation through dual thicknesses of screen oxide during N− drift implantation. Compared with traditional devices, devices with gradual junctions have improved off-state breakdown voltage (V BD) without sacrificing on-state driving current and hot-carrier-induced degradation. More improvement in V BD is observed if the dimensions of the device are larger. The mechanism responsible for V BD improvement in devices with gradual junctions is also investigated by using technology computer-aided-design simulations.

Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

This paper reports a concise physical model considering energy transport and source resistance for deep submicron n-channel metal-oxide-semiconductor (NMOS) devices. As verified by the experimental data, the closed-form analytical model shows good accuracy in the IV characteristics.

A novel ion implantation method for electrostatic discharge protection, often called as ESD implantation, is proposed to significantly improve machine-model (MM) ESD robustness of N-channel metal-oxide semiconductors (NMOS) device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300 µm/0.5 µm for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-µm complementary metal-oxide semiconductors (CMOS) process.

In this paper, we compare the drivability between single-gate, double-gate and intrinsic-channel double-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) by simulations that are based on the hydrodynamic-transport model; the band-to-band tunneling effect is considered. It is shown that double-gate SOI devices do not offer better drivability than single-gate SOI devices because of low electron drift velocity. In particular, in the 20 nm channel regime, intrinsic-channel double-gate SOI devices show poor performance than single-gate SOI devices.

This work investigates the hot-carrier effect (HCE) in partially depleted 0.1 µm SOI nMOSFETs. Hot-carrier degradation was investigated with respect to body-contact nMOSFET (BC-SOI) and floating-body nMOSFET without body contact (FB-SOI). It was found that hot-carrier-induced degradation exerts different influences on the drive capacities as well as subthreshold characteristics of FB-SOI and BC-SOI nMOSFETs. In FB-SOI nMOSFET, the floating body effect (FBE) and parasitic bipolar transistor effect (PBT) affect hot-carrier-induced degradation of device characteristics.

50 nm metal oxide semiconductor field effect transistors (MOSFETs) with two poly-Si side-gates are designed. We discuss the device structure and its fabrication process. Then, we investigate the improvement in device performance focusing on short channel effect, current drivability and hot carrier effect with two-dimensional and two-carrier device simulation. The proposed fabrication method maintains compatibility with the conventional MOS technology. The simulation results reveal that when the side-gate length is equal to the main-gate length, the device can be operated in an optimal condition.

Nitrogen implantation was used to improve the performance of Ni-salicide process for n-type metal oxide semiconductor field effect transistors (MOSFETs). It is found that the driving current and transconductance of nMOSFETs increase with the nitrogen implantation. The hot carrier degradation of the nMOSFETs is significantly reduced as the nitrogen dosage increases.

We observed characteristic "carpet-bombing-like concaves" after time-to-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) measurement for silicon carbide metal–oxide–semiconductor capacitors with a thermally grown oxide. A multiple breakdown model is proposed to explain the formation mechanism of the carpet-bombing-like concaves in TZDB measurement. Results and analysis of our TDDB measurements consistently support our multiple breakdown model.

The random telegraph noise (RTN) characteristics in numerous metal–oxide–semiconductor field-effect transistors were evaluated accurately with small floor noise of 59 µV. Because of the small floor noise RTN characteristics with small amplitudes could be measured. The time constants: time to emission (τe) and time to capture (τc) were extracted from measurement results with sampling period of 1 µs and sampling time of 600 s, and they were distributed for over six orders of magnitude. Based on the extracted data of τe and τc, there is no correlation between and . Also, it was clarified that the time constant ratio ( ) were distributed over nine orders of magnitude. Additionally, the gate bias dependence of , , and were analyzed. The distribution of is shifted to larger values with the increase of drain current (I D) and that of is shifted to smaller values with the increase of I D.

Conventionally, CoSi2 is considered to be a better choice than TiSi2 for integrated circuit fabrication due to its lower resisitivity and better thermal stability. In this letter we compare for the first time the stress reliability of metal–oxide–semiconductor (MOS) devices with CoSi2 and TiSi2 as gate electrode materials. We found that the use of TiSi2 as a gate electrode material can provide a better stress resistance than CoSi2, when negatively-biased constant current stress and constant voltage stress are applied.

Silicon carbide (4H-SiC as well as 6H-SiC) is known to be an anisotropic material. Among others, the transport parameters in the c-direction such as low field mobility and saturation velocity, are moderately different from those in the a- and b-directions in the case of 4H-SiC, while this difference becomes remarkable in the case of 6H-SiC. The aim of this study is to investigate the effect of this anisotropy on an analytical model for “drift region voltage drop” in a 4H-SiC vertical double implanted metal oxide semiconductor (VDIMOS) structure.