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In the paper, the novel topology of the resonant DC link three-level soft-switching inverter is proposed to reduce switching losses and improve the efficiency of three-level inverter at high switching frequency. Symmetrical auxiliary resonant circuits are set in the DC link of three-level hard-switching inverter. Moreover, the terminal voltage of the resonant capacitors between the DC buses periodically drops to zero via the resonance of auxiliary circuits. Furthermore, under such condition, the main switches of the three-level inverter would be operated, in order to achieve zero-voltage switching. Based on the equivalent circuits in different operating modes, the paper analyses the working process of the soft-switching inverter in detail. In addition, a 3 kW laboratory prototype of resonant DC link three-phase three-level soft-switching inverter is built. The experimental results show that the main switches and auxiliary switches of the inverter are operated under soft-switching conditions, and the efficiency is significantly improved compared with the three-level hard-switching inverter. Therefore, the proposed topology can effectively reduce switching losses and prove to be more practical in engineering. [ABSTRACT FROM AUTHOR]

An auxiliary switching device is usually set on the DC bus of the resonant DC link inverter, which restricts the efficiency of the inverter and is also one of the reasons for its not extensive application and promotion in the high-power field. To solve the problem, auxiliary circuits and DC bus of the resonant DC link soft-switching inverter designed in this paper are connected in parallel, and auxiliary switching devices and resonant elements are not connected in series on the DC bus, which help to improve the efficiency and reduce the power losses of the auxiliary resonant circuits. Based on the equivalent circuits in different operating modes, the paper analyzes the working process of the soft-switching inverter, soft-switching realization conditions and design rules. A 10 kW laboratory prototype is built, and through the comparison of the experimental results from it and the hard-switching inverter, it is shown that the efficiency improvement value of the designed inverter at full load is higher than that at light load. Therefore, the soft-switching inverter designed in this paper is conductive to reducing the power losses of the auxiliary resonant circuits and ensuring the efficient use of the electric energy. [ABSTRACT FROM AUTHOR]

Approximate computing is an emerging paradigm that can tolerate some loss of accuracy to improve the energy consumption and design complexity. Multiplication is one of the important computational components in various digital signal processing (DSP) applications. Improvement of multipliers, as the building blocks of an approximate computing systems, has received significant attention. Compressors are key elements in an approximate multiplier to have an optimal design with high performance. This paper proposes an approximate/exact 4–2 compressor and an exact 5–2 compressor in carbon nanotube field-effect transistors (CNTFET) technology for utilisation in an approximate multiplier. Four efficient designs for utilising the proposed compressors are introduced and analysed for a Wallace multiplier. All of the proposed circuits are analysed in 32 nm CNTFET Stanford technology and are simulated by HSPICE. In addition, as an image processing application of approximate multipliers, this paper compares the quality metrics of the image multiplication for the proposed designs and previously presented approximated multipliers. For example, the proposed schemes provide excellent results in structural similarity index up to 99%, and peak signal-to-noise ratio more than 45 dB. Also, it uses figure of metric (FOM) that includes the accuracy and quality metrics of the approximate multipliers. The simulation results demonstrate the efficiency of proposed designs. [ABSTRACT FROM AUTHOR]

This article is an interesting substrate material for environmental-friendly printable electronics. In this study, screen-printed RFID tags on paper substrate are examined. Their reliability was tested with low temperature, high temperature, slow temperature cycling, high temperature and high humidity and water dipping test. Environmental stresses affect the tag antenna impedance, losses and radiation characteristics due to their impact on the ink film and paper substrate. Low temperature, temperature cycling and high humidity did not have a radical effect on the measured parameters: threshold power, backscattered signal power or read range of the tags. However, the frequency response and the losses of the tags were slightly affected. Exposure to high temperature was found to even improve the tag performance due to the positive effect of high temperature on the ink film. The combined high humidity and high temperature had the most severe effect on the tag performance. The threshold power increased, backscattered power decreased and the read range was shortened. On the whole, the results showed that field use of these tags in high, low and changing temperature conditions and high humidity conditions is possible. Use of these tags in combined high-humidity and high-temperature conditions should be carefully considered. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

In this paper, a Dickson-based RF-DC (Radio frequency power to direct current power) rectifier for energy harvesting system is designed. Dickson double-voltage structure, voltage-dividing structure and switching transistors are integrated in the system to fulfil the synchronous rectifying function, which can upgrade PCE (Power Conversion Efficiency) value, reduce the threshold voltage and decrease the leakage current, etc.. The simulation is conducted on the designed synchronous rectifier for energy harvesting of 900 MHz signal. It shows that when the input voltage $${V_{IN}} = 1V$$ V IN = 1 V , the peak output DC voltage can be stabilised at 1.8 V with the assistance of LDO (Low dropout) regulator, while the reverse leakage current is below 20 µA and the PCE value reaches 58%. The designed rectifier is assembled and tested in the paper. Both the simulation and testing results demonstrate the feasibility of the proposed synchronous rectifier. [ABSTRACT FROM AUTHOR]

This paper describes a printed Thai character recognition method which uses topological properties. The recognition system is divided into two stages. In the rough classification stage, a thinning technique is applied to eliminate noise and fine features. The thinned characters are separated into cluster domains by using a linear decision function based on the height and width of each character. In the fine classification stage, the ‘connected numbers’ of points in the character pattern are computed. Topological properties are then used to distinguish between the characters. [ABSTRACT FROM AUTHOR]

A method of comparing the basic performance of electron guns is described. The method is applied to some recently computed results on two versions of an electron gun which has a hairpin-filament cathode.
In an interesting and useful paper by Worster (1979 a), hereafter referred to as JW, computed results are given relating to two electron guns. When the performance of the guns was compared it was concluded that one gun was better than the other in all respects. However, in making the comparison the electron beam divergence was not taken into account. Although the method of comparison used in JW may, of course, be satisfactory for some purposes, the computed results in JW are comprehensive enough to provide information for an alternative method of comparison which includes beam divergence. Such an alternative method, described in this note, leads to different conclusions. [ABSTRACT FROM AUTHOR]

Examines the characteristics of travelling waves along the non-linear transmission lines for monolithic integrated circuits. Analysis of slow-wave structures like MIS and Schottky-barrier strip lines; Examination of suitable equivalent circuits leading to characteristic wave equations; Parameters of the non-linearity, dispersion and dissipation and the boundary conditions of practical devices.

Examines the use of distributed, monolithic travelling-wave amplifiers. Guidance on reducing amplifier noise by rendering dipole-domain-generated noise contributed by the individual field effect transistor (FET); Use of insulated gate FET to permit higher gate breakdown voltage operation in the accumulation mode; Reduction of even harmonics and the improvement of efficiency.

Discusses the statistical properties of randomly generated boolean functions. Effect of prime implicant errors in the minimization algorithms; Relationship between the number of variables in the boolean expression on the k-subcube probability to be a prime implicant.

In this paper, we present a design method for a highly efficient retrodirective array (RDA)-based microwave power transfer (MPT) system for the mMTC scenario, and evaluate its characteristics through experiments. Long-range wireless power transfer is required to effectively support the mMTC situation. RDA-based MPT controls and tracks the power beam towards the device within a certain range and it enables efficient power transfer. The overall link budget analysis is examined first and the required antenna gain is calculated. The required antenna gain can be secured using multiple-antenna modules. So, it is possible to design an RDA-based MPT system. In this paper, we implement a reduced RDA-based MPT system and evaluate its characteristics to confirm the feasibility of this design method. Through experiments, it has been confirmed that additional gain can be secured by using multiple antenna modules, and the RDA function can be effectively operated to effectively make a power beam in the direction of the power receiver. Conclusively, the gain of about 2.2dB increased whenever the number of antennas is doubled. The experimental results also show that the RDA-based MPT system designed in this paper is capable of adaptive power beamforming from −30 degrees to 30 degrees. [ABSTRACT FROM AUTHOR]

This paper presents the performance analysis of a five-level T-type multilevel inverter (MLI) based six-phase induction motor drive (SPIMD) for high-power industrial applications. In the adopted T-type MLI, the sensorless self-capacitor voltage balancing control is designed, which controls the voltage across the capacitor at half the magnitude of the direct current (DC) source value, creating a symmetrical five-level output voltage waveform. Moreover, self-capacitor voltage balancing control reduces complexity and improves system performance. The SPIMD with distributed neutral is taken as the load, and the whole system is simulated using MATLAB/Simulink software. The system's performance is determined by considering the power loss and efficiency. This paper also presents a comparative performance analysis of the adopted T-type, cascaded h-bridge (CHB) and Flying Capacitor (FC) MLI-based SPIMD. Finally, a prototype is developed as a proof of concept and tested experimentally to validate the analytical development of the adopted system. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 $$W$$ W power and achieves a 235.50 MHz operating frequency. [ABSTRACT FROM AUTHOR]

The first part of the paper discusses designing of the lowpass filter that gives both a constant group delay over the passband and a sharp cut-off slope, which is one of the most difficult challenges in continuous-time signal processing. Furthermore, equalisation of the group delay distortion of the Chebyshev filter has been performed through a cascade connection of the allpass filters. The Newton–Raphson method is applied for solving the system of nonlinear equations that calculate the allpass filter parameters for equalising the constant group delay in an equiripple sense. This procedure gives nearly symmetric impulse response of the resulting filtering system, as well as a longer duration. In the second part of the paper, two solutions for synthesising polynomial filter transfer functions are discussed: filter with monotonic amplitude characteristic (LSM) and filter using Chebyshev polynomial. For the purpose of comparison, the passband ripple factor of the Chebyshev filter is necessary to be adjusted so that both filters have the same stopband insertion loss, group delay and transient response. It is shown that Chebyshev filter is preferable since the passband magnitude distortions and sensitivity to the element deviation tolerance are significantly superior. [ABSTRACT FROM AUTHOR]

The grid-forming inverter (GFI) plays an indispensable role in the microgrid (MG). Thus, it is critical for a microgrid to control the GFI flexibly and accurately, because of its voltage-forming and frequency regulation capabilities. The conventional proportional integral (PI) control strategy is usually used to control the GFI. However, the conventional PI control strategy has a high output voltage total harmonic distortion (THD) and deteriorative performance under external disturbances, which results in several problems in system flexibility, reliability and stability. This paper proposed a novel adaptive sliding mode control (ASMC) based cascaded control of the GFI system, which involves an ASMC-based inner current loop and outer voltage loop, and shows some superior performances of low THD, fast dynamic tracking performance and good robustness. Both the MATLAB/SIMULINK-based simulation and StarSim Modelling Tech-based semi-physical experimental results were presented to validate a perspective: the control strategy proposed by this paper has a better performance than the conventional PI control strategy under transient and steady-state condition. [ABSTRACT FROM AUTHOR]

Comments concerning on inconsistencies in the analysis of alpha-particle scattering. Validity of the field concept; Relation between the laws of physics and relativity; Information on the theory of electromagnetic.

The paper presents the measurement study of a double channel pHEMT device. Its focus is on examining impacts of several parameters including probe pitch size, position and the applied pressure on the measurements. The impact of probe pitch size, position and applying suitable amount of pressure and more pressure than required on the measuring perspective of a double channel pHEMT was investigated. As noted from the collected data, these impacts are most likely related to the stability factor, current gain and maximum available gain of the studied microwave device. The measurement was done using two probes with pitch sizes of 200 µm and 150 µm, and the probes were placed in the middle of the device's contact pads while exerting appropriate pressure. For double channel pHEMT on wafer, the outcome can be deemed similar for both pitch sizes. On the other hand, the probe with pitch size of 200 µm is utilised for applying more pressure than required where the probe occupied the entire pads of the device and the findings are skewed. Finally, it was found that the RF measurement is frequently affected by these conditions while the DC measurements are unaffected or have a minor effect. [ABSTRACT FROM AUTHOR]

The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour. [ABSTRACT FROM AUTHOR]

This paper presents a novel low-voltage low power fully differential class AB current output stage with high linearity and unique current drive capability. The proposed circuit is based on a simple and efficient structure to obtain high linearity by minimising the channel length modulation effect and also avoids cascade structure to act best in low-voltage applications. Giving the complete analyses and equations of the circuit, its properties are verified by Cadence using TSMC 0.18 µm CMOS parameters. In order to study its performance at the presence of non-idealities, Pre-layout and Post-layout both plus Monte–Carlo simulations are also performed. Under±0.9 V supply and 35 µA output bias current, it can deliver the ever high output current of ±350 mA with THD of −49 dB and output impedance of 2.8 MΩ, which leads to a unique high current drive ratio (Ioutmax/Ibias) of 10,000 and low consumed power of 150 µw in pre-layout simulation. In post-layout plus Monte–Carlo simulation, the results will be as ±320 mA output current, −42 dB THD, 2.2 MΩ output impedance, 40 µA DC current of the output branch, 8000 current drive ratio and 160 µw consumed power. These remarkable results prove the proposed novel COS not only as the unique one in the world but Longley ahead of the yet second rank COS by some unbeatable ratios as 11300×,14×,4× and3× in FT, Ioutmax, (Ioutmax/power), and current drive, respectively, that promise to keep it as the lead one for many years in low-voltage/power ultra-high current applications. [ABSTRACT FROM AUTHOR]

In modern days, MLIs comprise a lot of concentrations in academia and industry. As they are altering interest in a feasible technology in supporting frequent applications of renewable energy conversion systems and drives, these huge power and medium/higher voltage applications and MLIs are extensively used as one of the sophisticated powers converter topography. The MLIs are divided into two types such as asymmetric and symmetric. MLIs of the asymmetric kind have more amount of output AC voltage stage with fewer DC input source voltage and switching components. In this research paper, asymmetric single-phase cascade full-bridge MLI is developed with carrier-based unipolar PWM techniques. This MLI can generate nine-stage of output AC voltage through eight switches and two input DC sources. It is tested through a variety of multicarrier unipolar PWM control combinations. The Phase Disposition (PD), Alternating Phase Opposition Disposition (APOD), Carrier Overlapping (COP) and Variable Frequency (VF) are all PWM control which included in support of preference of single-phase nine-stage ternary cascade multilevel inverters. With various modulation indices (ma), the harmonic substance of output AC voltage for each approach is observed and tabulated. The proposed design for generating nine-stage output AC voltage is demonstrated using MATLAB-SIMULINK and confirmed using a laboratory-based prototype model. The results show that the unipolar Alternating Phase Opposition Disposition PWM technique that provides a high-quality output voltage with less harmonic distortion. Besides, the performance of Carrier Overlapping PWM techniques is greater since it produces a superior fundamental RMS output AC voltage. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiphase hybrid matrix converter topology dedicated to grid-connected five-phase wind generation. The proposed converter, named Five-phase Ultra-Sparse Series Z-source Matrix Converter (FUSSZMC), aims to facilitate the integration of the five-phase wind turbine generators. This is done by taking into account the improvement of the injected power quality and allowing the fixed output converter voltage level to that of the grid, thanks to the use of the series Z-source, under the variable voltage magnitude of the wind turbine generator, which depends on the wind speed. The proposed space vector modulation as a control strategy for FUSSZMC was detailed, where it was demonstrated that a suitable use of both large and small current vectors improves the input current waveforms. The global model of the proposed system was tested by simulation under Matlab/Simpowersys environment. The obtained results demonstrate clearly the advantages of using FUSSZMC and its modulation strategie. These benefits includea good input and output current waveforms, as reflected by the obtained total harmonic distortion (THD) values, that fall within the range prescribed by international standards. Additionally, FUSSZMC is capable of operating with unity input power factor, regulating input voltages and improving the quality of injected power into the grid. [ABSTRACT FROM AUTHOR]

In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide ($$Si{O_2}$$ Si O 2 + $$Hf{O_2}$$ Hf O 2 ) approach, and asymmetrical doping at the P+ source ($$S{i_{1 - X}}G{e_X}$$ S i 1 − X G e X ) and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device's switching ratio ($${I_{ON}}$$ I ON / $${I_{OFF}}$$ I OFF ), average subthreshold swing ($$S{S_{Avg}}$$ S S Avg ), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with $$S{i_{1 - X}}G{e_X}$$ S i 1 − X G e X source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with $$S{i_{0.6}}G{e_{0.4}}$$ S i 0.6 G e 0.4 exhibits an average subthreshold swing ($$S{S_{Avg}}$$ S S Avg ) of 28.8 mV/decade, switching ratio ($${I_{ON}}$$ I ON / $${I_{OFF}}$$ I OFF ) of 2 × 1012, cut-off frequency ($${f_T}$$ f T ) of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications. [ABSTRACT FROM AUTHOR]

A novel approach for the dielectric characterisation of 3D printed substrates in S-band applications of patch antennas with different infill percentages is presented in this paper. The meta-structure substrate design has been 3D printed with a fused deposition modelling technique using bio-sourced material poly-lactic acid (PLA). Combining different infill patterns changes the dielectric parameters, and hence, the RF(Radio-Frequency) performance of the design. To validate the usefulness of this approach, the Taguchi sampling technique is used, where nine samples of a meta-structure substrate were designed to determine the dielectric properties of the substrate. The ring resonator technique is used for measuring the dielectric constant and loss tangent of the fabricated substrates. All nine meta-structure substrate shows varying dielectric properties, which can be used for tuning of RF characteristics of the patch antenna. The measured permittivity of various substrate structures ranges between 2.39 and 2.71. The concept of propagation delay is chosen as the selective parameter for the fabrication of the antenna. The results of antenna simulation and fabrication were mapped closely. The proposed meta-structure design antenna resonates at 2.43 GHz with an S11 of −26.60 dB. Gain enhancement of 5% is seen in the selected meta-structure design compared with the simple (solid) structure. This meta-structure substrate design approach using different patterns is simple, scalable and can be realised in other 3D printed antenna applications. [ABSTRACT FROM AUTHOR]

Remarkable characteristics like simple structure, high starting torque, simple maintenance, good efficiency at all speeds and cost-effectiveness have made switched reluctance machines (SRMs) suitable candidates for electric cars, electric bicycles and variable speed applications (VSAs) such as wind turbines. In this paper, a three-phase Outer-Rotor SRM (ORSRM) with 6 stator poles and 10 rotor poles (6/10) for VSA has been investigated. Unlike conventional SRM structures such as 6/4 and 12/8, an SRM model with higher number of rotor poles can reduce torque ripple much more effective than conventional SRMs. First, the SRM design is done accurately, then, by changing some parameters, the sensitivity analysis is performed on torque ripple and average torque. Finally, the optimisation process on the geometry and structural dimensions of the SRM like rotor pole arc, stator pole arc, rotor yoke thickness, rotor pole height, rotor diameter and the number of turns per phase are executed to minimise the torque ripple and maximise the average torque via genetic algorithm (GA). The initial design, optimisation and performance of the proposed model are validated via a 2-D finite element method (FEM) technique by ANSYS-Maxwell. [ABSTRACT FROM AUTHOR]

In this paper, a high-efficiency class-F power amplifier with a harmonic control circuit is proposed. The harmonic control circuit is realised by loading microstrip branch lines to achieve a short-circuit state for the second harmonic. The double spiral defected ground units are loaded on the ground of the microstrip line of the drain bias circuit to produce a low-pass filtering and stopband suppression effect outside the passband, so as to suppress the third harmonic. Meanwhile, it would provide an open-circuit state for the third harmonic, and finally meet the harmonic impedance tuning demands of class-F power amplifier. Through theoretical analysis and simulation, a high-efficiency class-F power amplifier operating at 2.5 GHz ~2.7 GHz is designed. The measured results show that in the working frequency band, the drain efficiency is 66.3%~71.1%, the output power is 40.9 dBm ~42.1 dBm and the gain is 10.9 dB ~11.8 dB. [ABSTRACT FROM AUTHOR]

Aiming at the problem of unstable output voltage and rapid reduction of efficiency caused by coil misalignment in the wireless charging process of wireless chargers, a hybrid wireless power system with anti-misalignment and constant current (CC) output characteristics is proposed. The system uses a high-order compensation network and a four-coil bipolar (BP) coupler to implement high anti-misalignment and CC output characteristic that is decoupled from the load. By inserting a high-order compensation network, the two overlapping coils in the same side of the transmitter and receiver sides of the BP coupler can be effectively decoupled and the design methodology can be simplified. Moreover, by adjusting the inductance value of the transmitter compensation network, the BP coupler can be made available for the occasions with different equivalent mutual inductance (MI) fluctuation requirements. While the receiver coil is suddenly removed, the system has a self-protection function, which can effectively limit the current flowing through the inverter. The design ideas of the coupler and compensation network are also discussed in this paper. Ultimately, a 1-kW experimental prototype is built to validate the proposed scheme. [ABSTRACT FROM AUTHOR]

Wireless power transfer (WPT) has been developed as a suitable candidate for energy transfer in various applications, recently. Resonant tank is the main passive part of such systems and various topologies are introduced to improve WPT systems performance. Characteristics of these topologies definitely affect system overall performance. Therefore, each topology's specification and performance indexes should be evaluated and compared to choose a suitable one for a required application. In this paper, the characteristics and behaviour of voltage gain, input admittance and efficiency of well-known compensation topologies are thoroughly investigated for the first time. By calculating the voltage gain sensitivity, some analysis are performed on typical compensation including SS, SP, LCL-S, LCL-P, LCC-S, LCC-P and double-sided LCC under key parameter variations such as load resistance, switching frequency and coupling coefficient. In addition, by introducing a new formula for efficiency, the effect of resonant tank elements on efficiency is studied analytically which has not been performed before. In order to evaluate the theoretical analysis, the performance of all compensation topologies is investigated in MATLAB environment. By employing prototype SS and SP compensated inductive power transfer (IPT) test-bed system, some experimental verification are performed and the results confirm the analytical and numerical simulation findings. [ABSTRACT FROM AUTHOR]

In this paper a new non-isolated converter with ultra-high voltage gain is presented. The proposed converter utilises coupled inductors, lift circuits and interleaved technique to convert low-level DC voltages to high-level DC voltages without high turn ratios or large duty cycles. Winding-cross-coupled inductors are employed to raise the voltage ratio. The voltage and current stress of semiconductors are reduced, which causes low conduction losses and improves the efficiency. The way the clamp circuit is used limits not only the spike voltages but also effect on the conversion ratio of the proposed converter and make it larger. The main features of this converter are high voltage gain, low voltage stress of semiconductors, low reverse recovery of diodes, low input current ripple, low conduction loss and high efficiency. A prototype of the proposed circuit is constructed in laboratory at 100 W converting 20 V to 450 V. The experimental results are compared with theoretical analysis which verifies them. [ABSTRACT FROM AUTHOR]

This paper proposes a new generalised boost integrated multilevel inverter (MLI) with reduced components. The proposed MLI is developed by using a modified boost integrated switched capacitor unit, which provides four-level output from each cell. The operation of the proposed MLI for symmetrical 17-level operation with sinusoidal pulse width modulation & nearest level control and asymmetrical 31-level operation with NLC is explained and validated experimentally. The experimental results of static and dynamic load conditions are analysed and discussed in detail. In addition, the proposed topology is compared with recent boost MLI topologies in terms of component count, device stress, efficiency, capacitor size and cost. From the comparative study, it is evident that the proposed MLI provides features such as reduced component count, capacitors size, overall cost and improved voltage gain. [ABSTRACT FROM AUTHOR]

Digital filters with variable bandwidth can be used for a variety of applications. Arbitrary change in the bandwidth of a digital Finite Impulse Response (FIR) filter can be acquired using sampling rate converters (SRCs). In this paper, a SRC is proposed which is generated from Pascal structure, a fractional delay filter having low hardware complexity and high modularity. A low-pass filter having a single bandwidth sandwiched between two SRCs can contribute multiple bandwidths in such a way that each bandwidth is an arbitrary variation of the original bandwidth. A two-stage frequency response masking (FRM) approach is used for the hardware efficient design of the original low-pass filter. A low complexity and high modularity novel design for a continuously varying bandwidth of a digital FIR filter is proposed in this paper using the proposed SRC. The modularity of the Pascal structure can be used to control both pass band ripple as well as stop band attenuation of the continuously variable bandwidth FIR filter design. Different communication standards in a software-defined radio (SDR) channelizer is realised using the proposed design of continuously variable bandwidth filter. [ABSTRACT FROM AUTHOR]

The Multiple-Input Multiple-Output (MIMO) scheme uses multiple antenna configurations to achieve high throughput data transmission in current communication systems. The new generation wireless communication system considers using generalised frequency division multiplexing (GFDM) due to its advantages such as lower out-of-band (OOB) emission and peak-to-average power ratio (PAPR), etc. However, inter-symbol interference (ISI) and inter-carrier interference (ICI) occur due to GFDM utilises the pulse shaping filter. This paper proposes a low-complexity joint minimum mean square error (MMSE) receiver to suppress ISI, ICI, and multi-user interference (MUI) for multi-user MIMO-GFDM (MU-MIMO-GFDM) system. The conventional approach is to design the equalisation and the GFDM demodulation separately. This paper jointly designs the equalisation and demodulation process that significantly reduces the complexity and enhances the error rate performance. This paper also analyzes the closed-form expression and two low-complexity methods for the proposed receiver. The simulations demonstrate the effectiveness of the proposed low-complexity multi-user MIMO-GFDM receivers. [ABSTRACT FROM AUTHOR]

For meeting the actual demand of constant current (CC) and constant voltage (CV) in lithium-ion battery-charging process and improve the flexibility and safety of charging, this paper proposes a family of hybrid inductive power transfer (IPT) topologies that can realise CC and CV output and are not limited by the parameters of coils. Starting from a single existing topology with configurable CC or CV output, which can achieve zero-voltage switching (ZVS), load-independent and approximately zero reactive power, and the missing configurable CC or CV output is obtained by circuit transformation through cascaded T-type network. Then, the cascaded T-type network is switched by mode switches, so as to derive a family of hybrid IPT topologies suitable for lithium-ion battery wireless charging. In order to reduce the number of devices in the compensation network, the T-type network can be integrated with the existing compensation networks. Hence, this paper also proposes some hybrid IPT battery chargers and their design ideas. The control logic of mode switches and the sensitivity of compensation parameters are also discussed. Ultimately, a hybrid IPT battery charger based on S-S and S-LCC compensation networks is developed to test the correctness of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents an implementation of inductorless and resistorless Chua's chaotic oscillator using voltage-differencing gain amplifier (VDGA). The chaotic oscillator circuit is implemented by designing a resistorless Chua's diode using a single VDGA and a VDGA-based tank oscillator with coupled network circuit. The proposed chaotic oscillator uses two VDGAs and three grounded capacitors only. Although resistors and inductors may also be fabricated, the use of no resistor and inductor makes the circuit suitable for fabrication in terms of cost and area. It offers the advantages of an increased frequency spectrum having a dominant operating frequency of 21.1 MHz. The Chua's circuit is simulated in Pspice using both macro models of IC MAX435 and 0.18 µm CMOS TSMC Technology parameters. As a result, chaotic waveforms (V1 and V2) and the various attractors (V1 versus V2) are found in the simulation. These results confirm the theoretical predictions of Chua's chaotic oscillator. Various aspects of the proposed implementation of Chua's oscillator are compared with the earlier implementations. Finally, the paper concludes with simple remarks on the proposed circuit. [ABSTRACT FROM AUTHOR]

Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction. [ABSTRACT FROM AUTHOR]

A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance. [ABSTRACT FROM AUTHOR]

This paper introduces a hybrid multilevel inverter (MLI) with reduced switch count, which can generate higher output voltage level with minimum number of DC input sources. The operation of this proposed MLI is carried out with unequal DC sources to achieve the desired output voltage level. The reduced MLI output voltage is set to minimal total harmonic distortion (THD) with the help of modified JAYA (MJAYA) algorithm. A JAYA algorithm with improved steps by adopting an accelerating parameter has been proposed in this research work to obtain a faster convergence of the objective function. The MJAYA algorithm has provided the suitable switching angles for the proposed three-phase 15-level MLI and reduced the output voltage THD to 2.23%, which satisfies the standard set by IEEE-519. To prove the efficiency of this proposed modified algorithm, the comparative analysis is carried out through MATLAB program and Simulink tool using common JAYA and modified particle swarm optimisation algorithms. The performance and productivity of the proposed MLI have been investigated through simulation and experimental setups. [ABSTRACT FROM AUTHOR]

This paper investigates the design and analog the behaviour of an L-Patterned Negative-Capacitance Dual Tunneling Vertical TFET (L-NC-DT-VTFET) device with the idea of corner tunnelling and vertical tunnelling. In this proposed structure, the tunnel junction can be used over a large region in a perpendicular alignment to the channel direction. Furthermore, the gate of an L-NC-DT-VTFET is positioned vertically in the L-shaped to boost ON current. Moreover, adding the p+ pocket in the channel helps reduce ambipolar current and improves the ON current. By adjusting the thicknesses of the ferroelectric layer and pocket, the device design is created deliberately to improve the on current to off current ratio $${{({I_{ON}}} \mathord{\left/ {\vphantom {{({I_{ON}}} {{I_{OFF}}}}} \right. \kern-\nulldelimiterspace} {{I_{OFF}}}})$$ (I O N / I O F F ). The tunnelling current generated by dual tunnelling and negative capacitance extricates the collected holes, minimising the kink effect. The characteristics of the proposed L-NC-DT-VTFET structure are examined to those of known TFET architectures, and the suggested design appears to be a better match for high-performance, low-power applications as the device design maximise vertical tunnelling over corner tunnelling. [ABSTRACT FROM AUTHOR]

In this paper, a type of variable step size LMS named weighted zero attracting variable step size (WZAVSSLMS) is equipped with the control algorithm for governing DSTATCOM. In WZAVSSLMS, the ability of zero attracting nature to a variable step size (VSSLMS) for improving convergence rate is observed. WZAVSSLMS algorithm-based fundamental extractor is developed to identify the fundamental quantity of the load current for a three-phase four-wire DSTATCOM with non-linear load in this work. This type of variable step size LMS has provided a concession for quick convergence rate and steady-state error. Precision and convergence of responses are accomplished by the learning rate control. As a result of these features over conventional LMS, the authors choose WZAVSSLMS based approach in well-known DSTATCOM system to compensate power quality issues. The fundamental extraction from the distorted load current constitutes the main divergences in the proposed study. Further, the Finite control set model predictive control (FCS MPC) of the distribution static compensator (DSTATCOM) using Weighted Aggregated Sum Product Assessment Solution (WASPAS) method is implemented. [ABSTRACT FROM AUTHOR]

This paper proposes a system with Non-linear Carrier (NLC) controller for a high-voltage gain Quadrupler Converter (QRC). The system is 400 V DC Micro Grid (DCMG) with Wind Energy Conversion System (WECS). The quadrupler converter is a non-isolated topology that achieves single-stage high voltage gain with a low duty ratio and reduced voltage stress of semiconductor devices. The proposed system assures robust dynamics against changing operating conditions, variations in circuit parameters, and external load conditions. The parameters, such as voltage gain, voltage ripple, current ripple, delay time, settling time and peak overshoot, are assessed to ensure the agility of the proposed system. The performance of the proposed system is analysed with various wind speeds using Matlab Simulink-based simulation studies. The results inferred that the proposed method provides a fast response for various input and load variations and high gain at low duty ratio. A 200 W wind-connected QRC system with an NLC controller prototype is developed to validate the simulation results. [ABSTRACT FROM AUTHOR]

Traditional central control system is unable to deal with the optimal control tasks of modern distribution networks due to its low reliability, high computation and communication burden and poor expansibility. Based on distributed collaboration principle, this paper presents a multiple-object distributed optimisation control strategy for distribution network utilising DG grouping method. Distributed control strategy for node voltage control group is developed by taking the capacity utilisation ratio (CUR) of DG as the consensus variable, to comply with the feature of high resistance/reactance ratio of distribution network feeder line. Distributed control strategies for exchanged power control groups, which respectively takes CUR and power factor as the consensus variable, are formulated according to the different conditions of exchanged power imbalance. The parameter tuning method for three kinds of distributed optimisation control strategies are presented. The correctness and effectiveness of the proposed method are verified by simulation examples in the IEEE 14-node system, and simulation results on the IEEE 33-node test system are presented to show the robustness of the method to the disturbances related with distributed generation. [ABSTRACT FROM AUTHOR]

This paper proposes a novel compact tri-band bandpass filter based on two coupled asymmetrical stub-loaded resonators (ASLR). The proposed filter can achieve three resonant frequencies by tuning uniform impedance line, short-circuit stub, and open-circuit stub, respectively. In addition, the asymmetrical stub can be loaded at any position of the main branch, which will facilitate the circuit design for no impedance of special ratio is needed, and the design bound can be alleviated. Meanwhile, thanks to its simple structure, the whole filter occupies an area of 0.021 λg2 based on RO4350B substrate, much smaller than other similar tri-band filters. Measurement results show that the filter achieves fractional bandwidths (FBW) of 7.5%, 6.4% and 4.2%, respectively for three bands. The proposed filter is small and can achieve a high-frequency selectivity at 2.45 GHz, 3.5 GHz and 5.25 GHz, corresponding to Bluetooth, World Interoperability for Microwave Access (WiMAX) and Wireless Local Area Network (WLAN), respectively. The proposed filter will find a wide application in wireless communications thanks to its attractive advantages. [ABSTRACT FROM AUTHOR]

Photovoltaic (PV) systems are widely recognised as one of the most essential renewable energy sources for meeting future energy demands. The use of various multi-input DC–DC converters (MICs) to interface PV systems for output voltage regulation has been reported in the literature. PVs have inherent limitations, such as being extremely sensitive to changes in atmospheric conditions and human design/installation errors. Therefore, output voltage regulation suffers because of wide input voltage variations which have been ignored. In this regard, a novel MIC topology is proposed in this paper and it can operate under wide input voltage variation in buck, boost, and buck-boost modes of operation to achieve desired output voltage. The proposed topology is capable to integrate multiple energy sources and it offers an individual or simultaneous operation of the connected energy sources. Further, it also has additional features including high voltage gain, modularity, and control flexibility. The steady-state and thermal analysis have been presented, as well as a comparison with the state-of-the-art literature to prove the suitability of the proposed topology for PV application. The proposed MIC topology has been validated experimentally with wide input voltage variation. [ABSTRACT FROM AUTHOR]

The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported. [ABSTRACT FROM AUTHOR]

This paper proposes an interleaved multilevel converter (MLC)-based charger with power rating 2.8 kW to charge on-board battery of electric vehicle (EV). It comprises two stages: (1) an interleaved multilevel ac–dc converter; and (2) an LLC-resonant dc–dc converter. The interleaved approach efficiently maintains the optimum power level. The switching scheme implemented for MLC maintains the source current sinusoidal, supports unity power factor (UPF) and has the capability to balance the capacitor voltage. The MLC maintains UPF and balances capacitor voltage without any auxiliary circuit. In addition, MLC provides lower voltage stress and reduced total harmonic distortion (THD), therefore, making it a better choice for ac–dc conversion stage in battery charging application. The dc–dc converter furnishes regulated and wide output voltage range for on-board charging system. The principle of operation, modulation technique and control strategy for both the converters are analysed. Following theoretical analysis, laboratory experiments were conducted to validate the implemented approach. The results signify that for output voltage range of 24−72 V, UPF is maintained at input, lower stress across switches and capacitor voltage is balanced. The performance of MLC is satisfactory as it attains a peak efficiency of 97% with THD of 2.07%. [ABSTRACT FROM AUTHOR]

Power-domain NOMA can enlarge the spectrum efficiency and capacity via serving multiple users in the same time slot. Up to now, there are still some issues to be addressed in the NOMA system with multiple users: how many users the NOMA system can accommodate with limited power, how to mitigate the interference among the users, what's the achievable bound of capacity with limited power at the base station, and how to tackle with two or more users having similar distances to the base station. In the paper, the approximated CPM capacity in the NOMA system over Rayleigh channel is derived. Then, an adaptive user-clustering is proposed in downlink NOMA system, such that the achievable sum-rate will get high enough. Moreover, the optimal allocation of power for each user in each cluster is derived and evaluated. In the end, the performances such as outage probability, capacity, peak-to-average power ratio (PAPR), and bit error ratio (BER) are simulated as comparison. [ABSTRACT FROM AUTHOR]

This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high- κ gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage ( V T h ), I O N and I O N / I O F F ratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here. [ABSTRACT FROM AUTHOR]

In this paper, we propose an mm-wave local oscillator generation (LOG) method based on a voltage-controlled oscillator (VCO) with low phase noise (PN) and a novel injection-locked frequency tripler (ILFT), which can significantly improve the PN performance and power efficiency. The VCO features the source-to-gate feedback architecture with a third-impedance enhancement transformer so that the fundamental signal with the boosted third-harmonic output voltage in the source terminal is delivered to ILFT and the relatively pure 20-GHz signal from the gate node can be fed back to the phase-locked loop (PLL). The proposed ILFT adopts the high-order transformer-based resonator, injection-current-boosting (ICB), and class-D tail-switching techniques leading to a wide locking range (LR). Designed and simulated in 40-nm CMOS technology, the post-simulation results exhibit 1-MHz offset PN of better than −102 dBc/Hz over a continuous frequency tuning range (FTR) of 10.9% from 56.6 to 63.1 GHz while consuming 23.5 mW. The figure-of-merit (FoM) achieves up to 186.2 dBc/Hz at 1-MHz offset. [ABSTRACT FROM AUTHOR]

This paper introduces a new structure of a multi-level inverter (MLI) to generate high-level AC voltages using a low number of switches with a quasi-sine waveform. The small number of driver circuits utilised in bidirectional switches is a salient characteristic of this inverter. Also, the number of conducting switches at each voltage level is low in this structure. This results in lower conduction losses of the switches. The proposed topology can be used as the cascaded structure with different approaches to select the value of voltage sources. Power losses are discussed for the proposed structure. To compare the proposed multi-level inverter and demonstrate its superiority, a comparison has been made with some recently presented topologies. According to the comparison results, the advantage of the proposed structure is producing high voltage levels with a smaller number of switches and driver circuits. To prove the suitable performance of the proposed MLI, a 21-level symmetric and 37-level asymmetric inverter containing 14 switches are designed and simulated in the MATLAB/Simulink program. A laboratory prototype for each of these inverters is implemented. The experimental results finely verify the simulations. Besides, an accurate comparison with recently introduced multilevel inverters has been carried out to confirm the effectiveness and superiority of the proposed structure. [ABSTRACT FROM AUTHOR]

Limited by resources, single centralised ZigBee cannot be deployed in very large-scale application. To solve this problem, the paper presents a strategy design of ZigBee network that can be centralised and decentralised deploying in a wide area. There are two kinds of networks structure: the mobile independent network and the multi-sink large-scale network. The paper analyzes their performance, and then focuses on researching the main mathematics problems of the mobile independent network. In the paper, its mathematical model is multi-domain stochastic process.In the end, its main metric are simulated with MATLAB, the results of simulation and experiments show the feasibility of this network. [ABSTRACT FROM AUTHOR]

This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU) utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm node using Cadence Virtuoso simulator. Various ALUI/ALUII designs are presented with different data words. The result of ALUI proves its superiority compared with the traditional CMOS-based design in terms of power consumption, propagation delay and transistor count. The energy of the proposed 4-bit ALU reduced by 32% compared to CMOS based. Scalability of the proposed ALUI and ALUII designs are tested by extending length of the processed bits to 32-bits, through testing the performance of 8-bit, 16-bit, 32-bit ALUs based on the proposed ALUI and ALUII design. It is seen that the energy of the 4-bit ALU reduced by 21.2%, the power efficiency of the DSP and image processing circuits can be improved utilising the proposed designs of the ALUs. The experiment clears the superiority of the proposed ALU units and its suitability for long data words. [ABSTRACT FROM AUTHOR]

The rapid growth of the communication frequency band leads to the diversity of receiving frequency bands of smart devices. This paper proposes a reconfigurable wireless superheterodyne receiver for multi-standard communication systems. The receiver is designed through architecture design, chip selection, layout drawing, and physical measurement. The designed receiver consists of receiving module, local oscillator module, and control module. Unlike previous receivers, the proposed receiver selects the frequency channel, local oscillator frequency, and link gain through the control module in the current scene. The control module consists of a single-chip microcomputer and computer. The receiver can work in application scenarios including 2.4–2.5 GHz, 3.3–3.6 GHz, and 4.8–6.0 GHz. This paper discusses the design process of the proposed reconfigurable receiver in detail. Compared with the traditional receiver, the proposed receiver can change its working mode by software and has the characteristics of flexible reconfiguration. In addition, it has the advantages of a large link gain range and good demodulation performance. Moreover, the receiver is low in design cost and easy to manufacture. Therefore, it can be widely used in receiving modules of WLAN and 5G communication systems. [ABSTRACT FROM AUTHOR]

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high-performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy-delay product (EDP) are extracted and compared for the proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value of 1.377 µW and the NMNFA exhibits a highest value of 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages, the proposed adder delivers low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At a supply voltage of 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported minority-function bridge-style full adder in this paper. [ABSTRACT FROM AUTHOR]

In order to solve the problem of low detection rate of frequency hopping (FH) signal under low SNR, an FH signal detection technology based on deep neural network (vgg16 network) is proposed. Firstly, this paper introduces the principle of FH signal. Then, this paper presents the SSD deep neural network detection framework, and uses this framework to detect FH signal and estimate its parameters. Time-frequency distribution maps of FH signals are used as the input of deep neural network model to carry out tag learning and training, and then the trained model is used to realise FH signal detection. At the same time, aiming at the noise problem of time-frequency distribution map, the time-frequency graph correction method of K-means clustering algorithm is proposed. After modification, it is more tolerant to noise. The simulation results show that when the SNR is –4 dB, the detection rate of FH signal can reach more than 88%. Finally, the performance of parameter estimation of FH signal is analysed. [ABSTRACT FROM AUTHOR]

WSN consists of many sensors, they need high throughput and network lifetime to get involved in communication. Duty Cycle is a key factor in sensor nodes to maintain sleep, active condition in the presence of overhearing, collisions of packets while data transmission between sensor nodes. The key challenge of sensor nodes is to attain high energy efficiency, throughput and low End-End Delay. This paper presents several of existing approaches for MAC protocol. They are (1) Synchronization between nodes (2) Mathematical Analysis (3) TDMA based MAC and (4) Cross-Layer Design. We proposed a new method for MAC protocol with variable duty cycle. Neighboring nodes follow same duty cycle and same active time. Far away nodes doesn't maintain same duty cycle, hence their active time is not same. The duty cycle is maintained in synchronous way and adaptive manner among the nodes within the network. In this paper, a conventional MAC and proposed MAC are simulated using NS-2.35. Variable duty cycle approach in the proposed MAC with sleep and idle states for the nodes yields better throughput and energy efficiency with respect to other conventional technique. These results validate that the proposed variable DC-MAC is feasible for Wireless Sensor Network applications. [ABSTRACT FROM AUTHOR]

In this paper, we consider a power splitting (PS)-based simultaneous wireless information and power transfer (SWIPT) system, which is having I and Q (in-phase and quadrature) imbalance hardware impairment. The prime objective of this paper is to maximize the harvested energy for a SWIPT PS system, satisfying a minimum signal to noise ratio (SNR) requirement for information signal processing in the presence of IQ imbalance hardware impairment. The paper uses four types of bio-inspired algorithms like Particle Swarm Optimisation, Artificial Bee Colony, Firefly Algorithm and Invasive Weed Optimisation to attain the maximum harvested energy considering parameters of PS ratio, amplitude and phase imbalances in a Rayleigh fading environment. The simulation results show that under ideal power conversion efficiency and minimum hardware impairments, a maximum SNR of 16.7 dB and harvested energy of 11 dB is achieved for a transmit power of 20 dB in SWIPT systems for IWO bio-inspired algorithms in the 32 QAM modulation scheme. [ABSTRACT FROM AUTHOR]

Please replcae the abstract with the following text:In this paper, a new isolated high step-down dc-dc topology based on buck converter is proposed. This structure reduces the amplitude of the voltage on the primary side of the transformer (which is an ideal type), which reduces the turn-ratio and leakage impedance. The recommended structure uses active clamped strategies to return the energy of leakage impedance and to repress voltage spikes. Under this condition, the overall efficiency of the converter can be enhanced impressively. The benefits of the proposed structure are simple structure, a simple control system that needs only two signals with a 180O phase shift, reduced power circuit components, the lower standing voltage of the semiconductor components in the high-voltage side, and a high conversion ratio. The proposed converter can be applied in low voltage (5V) applications with high input current such as computer applications. The operation modes of the recommended converter, designing of utilized circuit elements, steady condition analysis, and finally some experimental results of the built prototype of the recommended structure have been provided completely. The overall efficiency of the proposed topology at 250W is equal to 92%. Also, the amplitudes of input and output voltage are 380 V and 5 V, respectively. [ABSTRACT FROM AUTHOR]

The traditional coprime parallel array (TrCPA) is prone to suffer from the problem of angle ambiguity, due to its larger inter-element spacing and limited array aperture, for two-dimensional direction of arrival estimation. And the classic multiple signal classification (MUSIC) algorithm has heavy complexity and has poor estimation ability in some unsatisfactory situations. Both restrict the improvement of angle estimation performance. In this paper, we design a novel displaced coprime parallel array termed NDCPA, by rearranging and misplacing all subarrays of TrCPA along the coordinate axis, which brings about larger array aperture making contributions to superior angle estimation accuracy. Besides, we propose an improved two-step reduced-dimensional MUSIC algorithm to further enhance angle estimation accuracy. The proposed method reconstructs the covariance matrix, which can fully exploit the information contained in uniform linear subarrays. Meanwhile, the transformation of angle domain divides the original two-dimensional search into two one-dimensional searches, reducing complexity to a certain extent. Finally, simulation results verify the effectiveness and applicability of the proposed configuration and method compared with the other structures and methods. [ABSTRACT FROM AUTHOR]

This paper presents a highly isolated pattern diversity multiband MIMO antenna using two ring-shaped radiating elements with a rectangular stub placed inside it. The proposed multiband MIMO antenna is resonating at three frequencies centred at 2.45 GHz, 3.5 GHz, and 5.4 GHz. A high-quality factor U-shaped bandstop filter is designed and placed between the two antenna elements to achieve simultaneous high isolation and pattern diversity. The isolation between the antenna elements at 2.45 GHz, 3.5 GHz, and 5.4 GHz is −25 dB, −20 dB and −35 dB, respectively. The diversity gain is 10 dB, while the ECC is less than 0.05. The antenna is fabricated on a low-cost substrate, FR4, and its dimensions are 31 mm × 31 mm × 0.8 mm. Measured results verify the multiband behaviour of the proposed MIMO antenna. The proposed MIMO antenna is useful for WLAN, WiMAX and 5 G sub-6 GHz-based applications. [ABSTRACT FROM AUTHOR]

This paper presents a hepta-band planar monopole antenna which exhibits circular polarization (CP) at two bands and linear polarization at other five bands. Combination of rectangular slots to form a single E-shaped structure has been introduced in half ground to excite hepta-band operations. Asymmetric trapezoidal parasitic element is also placed under the monopole radiator positioned at upper half ground plane of antenna. Due to asymmetric effect attained by the placement of trapezium, CP is achieved at 4.2 GHz and 10 GHz with 3-dB axial ratio bandwidth of 4.21–4.29 GHz and 9.92–10.01 GHz, respectively. The antenna acquires remaining five resonant modes at 2.4 GHz, 5.4 GHz, 7.2 GHz, 8.86 GHz and 11.8 GHz with 10-dB impedance bandwidth of 90 MHz, 160 MHz, 100 MHz, 200 MHz and 410 MHz, respectively. Sensitive study of the E slot and trapezoidal structured geometry is conducted. The proposed antenna is designed on low cost FR4 (εr = 4.4, tanδ = 0.02). To ensure the practicability, the proposed antenna design is fabricated and measured. A good agreement of simulation and measurement validates the proposed designed. The antenna has potential to cover frequency bands of IEEE802.11, Bluetooth, WLAN, WiMAX, Satellite Communication, Short Range RADARs and Radio band applications. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

In this paper, a new Buck-Boost converter with coupled inductor that can eliminate right-half-plane (RHP) zeros is proposed. The steady-state model and small-signal model of the proposed Buck-Boost converter in continuous conduction mode (CCM) are established and analysed, and its control-to-output voltage transfer function is obtained. The condition for this proposed converter to eliminate RHP zeros is derived based on the Mason formula. The comparisons among the other extant four Buck-Boost converters and the proposed Buck-Boost converter are carried out, and it shows that the proposed Buck-Boost converter has the advantage of eliminating RHP zeros. Finally, some simulations and circuit experiments are presented for confirmation. [ABSTRACT FROM AUTHOR]

In this paper, a self-multiplexing textile antenna aided by a substrate integrated waveguide (SIW) is designed for wearable applications. The proposed antenna operates at wireless body area network (WBAN) frequencies such as 5, 5.2, 5.5 and 5.8 GHz. Extended unequal half mode substrate integrated waveguide (HMSIW) cavities are utilised for self-multiplexing operations with the open-ended magnetic wall working as the radiator for the proposed textile antenna. All the four unequal HMSIW cavities share the same electric wall which is realised using brass eyelets. The textile antenna is fabricated and the antenna parameters are measured to elucidate the proposed antenna concept. The port isolation has achieved above 33 dB between any ports. The measured gains for the four frequencies are above 5.1 dBi with high efficiency. The proposed multiplexing antenna is designed in 90 × 65 * 0.57 mm3 dimensions and the proposed antenna has exhibited good performance which makes it suitable for integrating with wearable devices and obviating the extra multiplexer circuits. [ABSTRACT FROM AUTHOR]

A compound reconfigurable monopole antenna (CRMA) having ability to change its frequency, polarisation and also pattern is presented in this paper. Only 6 PIN diodes are positioned on the monopole and ground to achieve reconfigurable operations and thus the antenna can operate over 8 different states. The radiation patterns of the proposed antenna can be tilted into two different directions. In each direction, the antenna can shift its operation in between two different frequency bands, and for each band, switching between two orthogonal circularly polarised (CP) radiation can be possible. A prototype is fabricated and measured. Based on various parametric analyses, a simple design guideline is also presented. By considering its overall simple configuration, low profile, and planar geometry, proposed antenna can be a useful candidate for future wireless applications like cognitive radio, 5 G devices, and so on. [ABSTRACT FROM AUTHOR]

This paper proposes an improved version of Synchronous Reference Frame (SRF) based phase locked loop (PLL). The conventional SRF-PLL structure is modified and made adaptive using a Least Means Square (LMS) algorithm. The benefit of the proposed scheme is that the tuning of proportional controller (PI) gain parameters can be achieved automatically without having to optimise these parameters manually. The PLL is utilised to track important electrical grid parameters such as phase angle, unit synchronisation templates and voltage magnitude. This performance study investigates several cases such as voltage sag/swell, wide frequency deviation, phase jump, presence of noise and harmonics in the supply voltage. The impact of constant and adaptive PI parameters influencing PLL performance is investigated. Finally, a fair comparison is presented which discusses the proposed adaptive SRF-PLL(ASRF-PLL), conventional fixed gain SRF-PLL, unit template-based synchronisation technique and Delayed Signal Cancellation based PLL (DSC-PLL). [ABSTRACT FROM AUTHOR]

This paper presents the design of a direct-type adaptive control structure for current regulation of a single-phase grid-tied Voltage-Source Inverter (VSI) with an LCL filter under very weak grid condition. The initial content of this work was previously published, where the controller was presented and its discrete-time stability proof was provided. Power converters connected to weak grids bring challenges to the control system, since the grid can change abruptly from a strong to a very weak condition , degrading system power quality. This study evaluates the feasibility of a RMRAC-based robust adaptive Super-Twisting Sliding Mode controller for current control of VSI when the grid inductance changes substantially, from 0 mH (strong grid) to 10 mH (very weak grid). To show the benefits of the control strategy and its robustness, hardware-in-the-loop (HIL) simulation results are presented, comparing its performance with two other controllers.. [ABSTRACT FROM AUTHOR]

This paper proposed a new quadratic boost converter featuring a high voltage conversion ratio, high efficiency, and comparatively low inductor currents using reduced redundant power processing and voltage lift configurations for PV applications. The proposed Quadratic Boost Converter (QBC) consists of fewer components and improves voltage gain at a lower duty cycle. Furthermore, the inductor and capacitor are controlled to reduce output current and voltage ripples. The operational modes, steady-state analysis, design aspects, and dynamic modelling of the converter in continuous conduction mode are discussed clearly. The performance of the proposed QBC is compared with different existing converters in terms of component count, voltage gain, voltage and current stress of the switching components, effective index, total switching device power, and component losses. A110W hardware prototype has been developed. The simulation and experimental results of the converter validate its performance and stated benefits. The efficiency curves for the proposed QBC for various load currents are presented, with a peak efficiency of 93.8%. [ABSTRACT FROM AUTHOR]

This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written '1', enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications. [ABSTRACT FROM AUTHOR]

In recent days, due to the wide verities of applications of Wireless Sensor Networks, it gets recognition from research communities. As the sensor nodes are operated through limited battery capacity, how to utilise the battery power or energy in an optimum way is a major concern. In this paper, we have addressed the energy issue of wireless sensor networks. We have developed an energy-efficient routing protocol. This paper proposes the Novel Elite group concept where the cluster-head selection process is restricted to only a few high-energy nodes rather than all nodes in the network, which substantially reduces the number of cluster-head selection overhead in every iteration, decreases the energy consumption and increases network lifetime. Our method is compared with three well-known routing protocols, i.e. EECRP (Energy Efficient Centroid-Based Routing Protocol) protocol, NCBR (New Cooperative Balancing Routing Protocol) and Mod-LEACH (Modified low-Energy Adaptive Clustering Hierarchy Protocol). We have conducted a simulation in NS-2 simulator. We have computed various network quality parameters like Throughput, transmission delay, analysis of the number of dead nodes (reciprocal of alive nodes) and energy dissipation with respect to the number of simulation rounds. The simulation results show that our proposed methodology outperforms the rest of the protocol. [ABSTRACT FROM AUTHOR]

This paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency. [ABSTRACT FROM AUTHOR]

This paper represents, for the first time, the linearisation method of RF power amplifiers, which is based on using the second- and fourth-order nonlinear signals shaped by digital signal processing in a baseband domain. The linearisation signals are generated by the second- and fourth-order nonlinear modifications of the baseband signal in the proposed manners. The composite second- and fourth-order linearisation signals modulate carrier second harmonics, and the modulated signals are then driven to the gate and drain of the amplifier transistor. The linearisation effects of the proposed method are evaluated on a single stage power amplifier for the simulated QAM and OFDM digitally modulated signals at diverse input power levels up to the 1 dB compression point. Moreover, the FPGA implementation of a system for the generation and processing of the fundamental signal, and the second-order linearisation signals is presented in the paper, and the proposed technique is verified for the generated QAM signal. In addition, the linearisation of the two-way asymmetrical Doherty amplifier is performed in the experiment by using software defined radio platforms for synthesising the fundamental signal and the second-order linearisation signals. [ABSTRACT FROM AUTHOR]

With the advancement in technology and population growth, the motivation of integrating utility grid with the microgrid through power electronic converters increases. This paper presents the control of power electronic converter connected at the grid side. This converter regulates the power flow between renewable energy system (RES), load and grid in addition to the compensation of harmonic and reactive power. The reference currents are generated to decide the power flow from RES to the load and to suppress the harmonic and reactive power in the grid making grid current sinusoidal. In this paper, the reference current generation techniques like instantaneous real-reactive (p-q) method and extension p-q method are implemented and compared. Linear Quadratic Regulator (LQR) is used to track the reference current. The control law of LQR is designed in a simple way using simplified equivalent circuit of a three-phase grid integrated renewable energy system. The system is tested experimentally under balanced and unbalanced conditions in two different modes such as insufficient renewable power and excess renewable power. The supremacy of extension p-q method over instantaneous p-q method is proved by getting low total harmonic distortion and better power factor under balanced and unbalanced conditions experimentally. [ABSTRACT FROM AUTHOR]

The International Mobile Telecommunications-2020 (IMT-2020) specifies the data rates for enhanced mobile broadband (eMBB) is approximately 10 Gb/s. Millimetre-wave (mmWave) has a vast spectrum and can be used with only slight authorisation, making it an ideal solution for eMBB. This paper proposes optimal detectors with low cost, low power consumption, and low complexity for mmWave massive multi-user multiple-input multiple-output (MU-MIMO) communication. The mmWave broadband communication faces many challenges in system implementation. One of the challenges of mmWave broadband systems is using the analog-to-digital converter (ADC) in the receiver. The ADC power consumption will significantly increase with the frequency bandwidth. The ADC power consumption will also considerably increase with the bit number used in the conversion simultaneously. The mmWave broadband communication also challenges the cost of transmitters, especially wideband linear amplifiers are costly. Hence, it is necessary to transmit a signal with a low peak-to-average power ratio (PAPR) to relax the linearity of the power amplifier. The radio-frequency (RF) port connects to two high-precision ADCs in conventional MIMO systems. Scaling such architectures to massive multiple-input multiple-output (MIMO) with hundreds or thousands of active antenna elements would lead to excessive-high power consumption and hardware costs. Hence, this paper proposes optimal detections for massive multi-user (MU) MIMO-GFDM communications with coarse quantisation. It achieves substantial cost and power savings and provides a high system capacity. The optimal detections for coarse quantisation in large-scale MU-MIMO-GFDM systems have minimal capability loss compared with the ideal case. There is no additional base-band processing complexity. The simulation results show that the SNR gap between the second mismatched quantiser and the precise quantiser is small. When the ratio of receiving and transmitting antennas is the same, the larger the number of antennas, the smaller the SNR difference between the second mismatch quantiser and the precise quantiser. [ABSTRACT FROM AUTHOR]

This paper proposes a new modified level, increased nearest level modulation (NLM) method to improve the THD quality and enhance the quality of output voltage of modular multilevel converters (MMCs). Offshore wind farm links need connections from onshore national grids, and this paper is consistent with higher level voltage generation techniques by using MMC. By changing the on-number sub-modules (SM) at the middle position after using the round function, the generated gate logic by using the proposed method maintains a fixed magnitude value of phase voltage with a maximal number of (2 N + 1) levels, where N is the number of sub-modules per arm. The proposed method maintains the advantages of the conventional NLM such as simple implementation and low switching loss and avoids the disadvantages of the existing NLM method such as capacitor voltage ripple, peak value of arm inductor voltage, complexity in topology, etc. Both the advantages and disadvantages of the proposed and the conventional schemes are also studied, and an illustrated comparison shows the THD result differences for four methods. The system is simulated using MATLAB-Simulink to validate the feasibility of the proposed scheme and carried out by a hardware-in-the-loop simulation (HILS) system. By reviewing the simulation and experimental results, it was found that the proposed scheme improves the output voltage and THD quality. [ABSTRACT FROM AUTHOR]

In energy harnessing applications there are instances where energy should be transferred from a low-power, low-leakage backup battery to a temporary power delivery output capacitor. The high power delivery feature of the storage capacitor usually comes at the price of higher leakage current and thus it cannot replace the long-term energy storage backup battery. This paper presents a CMOS capacitor charger circuit which connects a long term low power battery to a short-burst high power delivery capacitor. The proposed circuit uses a switching output stage with an external inductor to reduce the dissipation during the capacitor charge-up cycle. A sigma-delta modulation approach is used to control the power switches. Under low power transfer scenarios which perform transfer in a longer duration, the proposed approach shows better performance compared with previously presented techniques. It is shown that under different transfer durations the control section only consumes 970nWs. The efficiency of the proposed circuit is more than 90% for average input powers in the 0.7 mW to 2 mW range. [ABSTRACT FROM AUTHOR]

This paper elucidates the working of shunt active filters in dynamically varying grid conditions. The accuracy of harmonics eliminated is based on the harmonic extraction technique and the switching techniques used. The harmonics of the electrical system are computed and based on the various harmonics produced; the shunt active filter has to supply a compensating current in opposition at the point of common coupling. Space Vector Pulse Width modulation (SVPWM) is an effective switching technique used but its performance is not satisfactory in the over-modulation regions. In this paper, optimised switching technique using a neural network for SVPWM is used which has lesser computation time and computes the gating pulses effectively in the over-modulation regions. Shunt active filter mitigates the impact of harmonics even in the over-modulation regions. The hardware is implemented using FPGA Spartan 6 controller, which utilises fewer hardware resources. The optimised switching topology results with improved harmonic reduction even in the over-modulation regions with unbalanced loading conditions is presented in this paper. [ABSTRACT FROM AUTHOR]

Presents a reply on the inconsistency in the analysis of alpha-particle scattering. Correlation between electromagnetic field and vectors; Analysis of the geometry of vector functions; Distinction between motion and force.

Micro-grid needs to integrate islanding operation mode and grid-connected operation mode together. Smooth switching between islanding operation mode and grid-connected operation mode is the key to ensure stable operation of micro-grid. In order to solve the problem of transient electrical quantity mutation in the process of dual-mode switching in microgrid, a dual-mode combined seamless switching control strategy based on current tracking is proposed for the battery inverter of the main control unit in this paper, to make the reference current of the input current inner loop controller can follow the current state at the moment before the switching moment, and maintain the correct initial value, so that the microgrid can switch smoothly and stably between grid-connected state and islanding state. Simulation results are provided to verify the effectiveness of proposed control strategy, by Power Systems Computer-Aided Design/Electro Magnetic Transient in DC System (PSCAD/EMTDC) simulation software. [ABSTRACT FROM AUTHOR]

Image skeletonisation plays an important role in applications such as object identification, object's shape description, pattern recognition, computer vision, telemedicine, and image compression. In this paper, an architecture is developed for the extraction of a skeleton for the 3-D greyscale object. The algorithm used in this paper is an extension of the 2-D greyscale skeletonisation algorithm presented in the literature. The skeleton of a 3-D greyscale object is extracted by using the boundary peeling off method. The skeletonisation algorithms are computationally intensive and difficult to achieve requirements in real-time. Field Programmable Gate Arrays (FPGAs) are selected for implementation so the real-time requirements are met. The proposed architecture is implemented on Virtex-5 FPGA and tested for an 8 × 8 x 3 greyscale object. Resource utilisation of FPGA and timing performance are investigated and are encouraging. [ABSTRACT FROM AUTHOR]

With reference to reducing dimensionality or predicting data missing mechanism, this paper approaches the function between distribution of missing data and topology of wireless sensor networks, and presents a recombination information missing data process method. As the missing data normally come from communication especially media accessing mechanism of carrier sense multiple access (CSMA) or time division multiple access (TDMA), the paper shows that the packets loss process is normally Poisson stochastic process. And the paper studies maximum missing data rates of some different topology networks (for example, the topology of star, hierarchical cluster tree, and mesh). In the end, the paper estimates the recombination information missing data processes method by simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a model for three-dimensional (3-D) wireless ad hoc networks with randomly distributed nodes and unknown node locations. In this model, the nodes are assumed to be randomly distributed in a cubic torus. The distances between neighbouring nodes (hop lengths) and the distance between thesource and destination nodes (route length) are assumed to be random. In the first part of this paper, exact analytical expressions are derived for the cumulative distribution function (CDF) and the probability density function (PDF) of the hop and route lengths.Then, these distributions are used to find the average hop length,route length and number of hops analytically and numerically. The performance of the system is studied in terms of the average route bit error rate (BER) and the optimal transmit power needed to achieve a given threshold BER to maintain network connectivity. Moreover, the performance of decode-and-forward (DF) relaying scheme over Rayleigh fading channels in the presence of cochannelinterference (CCI) is studied. It is assumed that CCI is modelled as the sum of independent-not-identically distributed Rayleigh variates. [ABSTRACT FROM AUTHOR]

Floating-capacitor-based nine-level inverter topology for open-ended winding induction motor (OWIM) drive is presented in this paper. The proposed multilevel inverter topology (PMLIT) essentially consists of four three-phase two-level voltage source inverters (VSI), three isolated DC sources and a floating-capacitor (FC). Out of four inverters, three inverters are fed from DC sources, and the fourth inverter is connected with the FC. The advantage of the PMLIT is that the maximum output voltage will be twice the source voltage with nine levels across each phase winding. The PMLIT employs least number of components which makes the inverter cost-effective and has lowered control complexity. The PMLIT can deliver seven, five or three-level output voltage with a decrease in modulation index. Conventional sinusoidal pulse-width modulation (PWM) techniques can be employed to generate switch-gate pulses. The intermediate-voltage levels are realised by proper charging and discharging of the FC. The performance of the PMLIT under possible switch faults is investigated, and modified switching logics are proposed to deliver a balanced supply for the OWIM drive in post-fault operation. Simulations are performed in the MATLAB/Simulink environment, and an experimental setup is designed to validate the simulations, and the results are presented. [ABSTRACT FROM AUTHOR]

In cooperative spectrum sensing (CSS), in order to maximise the energy efficiency (EE) of cognitive radio (CR) users, users are divided into clusters. In this paper, the optimal inter-fusion rule threshold formula for different number of clusters and users is proposed for maximum EE in cluster-based CSS (CB-CSS). Different fusion rules are investigated for this purpose over Nakagami and Rician fading channel conditions. Simulations are conducted for different number of clusters and users using AND and OR intra-fusion rules and inter-fusion rule threshold is optimised in CB-CSS over the Nakagami-m fading channel and the Rician fading channel. The obtained mathematical expression for the inter-fusion rule threshold is verified by the results. It is investigated that when number of clusters are P = 4 and number of users in a cluster are K = 6 , OR-AND ( n = 1 , r = P) fusion rule achieves 2.46% more EE than AND-OR ( n = K , r = 1) fusion rule in case of Nakagami fading channel and 5.06% more EE than AND-OR fusion rule in case of Rician fading channel. Further, EE with respect to number of users is compared between additive white gaussian noise (AWGN) channel and Nakagami and Rician fading channels. [ABSTRACT FROM AUTHOR]

Internet of Things (IoT) is a smart technology that allows communication between humans and all things that contain sensors, actuators, embedded electronics, software, or storage via the internet. As a result, IoT should be seen as a part of the overall Internet of the future, which is likely to be very different from what we are using today. Despite the advantages of IoT, energy efficiency is still considered one of the main challenges in IoT. There are many algorithms that have been proposed to solve the energy efficiency problem. Unfortunately, most of them have some drawbacks. As a result, an Enhanced Threshold Sensitive Distributed Energy-Efficient Clustering routing protocol (ETSDEEC) for WSN-based IoT was proposed in this paper. Hard and soft thresholds are used in the proposed protocol to determine whether nodes are allowed to send their sensed data. From the simulation, we found that the proposed ETSDEEC protocol performs better than EDEEC and TDEEC protocols in terms of network lifetime, energy dissipationand throughput. It is also found that the proposed ETSDEEC can improve the lifetime by 59.8% in comparison to EDEEC and about 37.7% in comparison to TDEEC protocols. [ABSTRACT FROM AUTHOR]

Throughout this paper, a single-source hybrid switched-capacitor multilevel inverter is presented. The suggested topology is comprised of switched-capacitor modules. In this topology, two types of switched-capacitor modules are utilised: 1) basic module (BM) and 2) auxiliary units (AUs). By adding more AUs to the proposed topology, the voltage levels can be increased. By taking advantage of the switching procedure, three various configurations are made for the suggested MLI, in which the voltages of the capacitors are determined differently. Hence, in each configuration, according to the voltages of capacitors, different output voltage levels with different maximum output voltage and total standing voltage of switches are attained. To show the superiority of the proposed topology, a comprehensive comparison is made in terms of the number of DC voltage sources, power switches, capacitors, and diodes. Moreover, to investigate the performance of the suggested topology, a sample circuit with all configurations is simulated in MATLAB/Simulink. Finally, the experimental results are demonstrated to illustrate and verify the feasibility of the proposed inverter. [ABSTRACT FROM AUTHOR]

The demand for cost, power and area-efficient de-noising filter is increasing day by day, because of its remarkable performance in various image processing applications. In this paper, a variable-node shift-based median filter is designed for achieving low power and area utilisation. Here, the proposed design encompasses a Max Tree Extraction (MTE) unit in conjunction with various devices, like comparators, variable-node shift generators, token generators, and noise detector units, which enable low hardware requirement and minimise the power consumption. The proposed model lessens the need of complex operations, like rank generation, rank calculation and median selection. Moreover, the proposed median filter is structured by Xilinx software and the hardware implementation is done by FPGA (Virtex 7 ×C7VX980 FPGA). Additionally, the proposed model is evaluated for different test images at various noise levels. The performance of the proposed median filter design is analysed under peak signal to noise ratio (PSNR), mean square error (MSE), power, delay and area. The experimental results show that the overall performance of the proposed method is superior to the state-of-art technologies. [ABSTRACT FROM AUTHOR]

This paper presents a new switching strategy by combining space vector modulation (SVM) and pulse amplitude modulation (PAM) techniques. The proposed method can eliminate harmonics and reduce power loss, leading to efficiency increment. Moreover, as one of the significant challenges in any modulation technique, the common-mode voltage is investigated. Accordingly, applying the proposed method in a conventional back-to-back two-level converter results in a substantial reduction of the common-mode voltage as well as the harmonic content of the systems' input current fed by the power grid. Also, easy implementation regardless of the converter's rating is the other advantage of using this method. Furthermore, applying this strategy does not add to the converter's volume, weight, and cost. The appropriate selection of the active vectors, the arrangement of the switching sequences for the inverter and rectifier, as well as the modulation index of the converter are key factors in this technique. The performance of the proposed strategy is investigated through both simulations and experimentations on a back-to-back two-level converter prototype. The experimental results show that the proposed method reduces the common-mode voltage by more than 50%, reaching 87.2% efficiency, making the proposed method suitable for industrial applications. [ABSTRACT FROM AUTHOR]

Model predictive control (MPC) is considered one of the best non-linear control methods for controlling the modular multilevel converter (MMC) due to various advantages, such as no need for direct modelling, high dynamic response, and the ability to manage multiple control targets simultaneously. In this paper, a current closed-loop controller (CCLC) based on the current predictive strategy (CPS) is used to control the circulating and output currents in an MMC. A bilinear mathematical model of the MMC is derived and discretized to predict the states of the MMC for one step ahead. In addition, to reduce the practical costs and reduce the converter sensors, a sensor reduction algorithm has been used to reduce the number of voltage sensors and increase the reliability of the system. The proposed method is implemented in a single-phase MMC with four sub-modules (SMs) in each arm. The accuracy and performance of the proposed method are evaluated with simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, an 8-bit programmable digital metasurface is designed in the operating frequency range from 4 to 7 GHz. A monopole antenna operating at 5 GHz is characterised by using a metasurface structure as the ground plane. Various combinations of the metasurface structure are examined by altering the state of each unit-cell between 'ON (1)' and 'OFF (0)' in the coding matrix. The purpose of the 8-bit programmable digital metasurface is to control the electromagnetic wave effectively in the frequency range of interest. Dynamically controllable metasurface structure is utilised to change the unit cells' configurations. In addition, the proposed adjustable metasurface is capable to control the monopole antenna directivity, gain and main lobe magnitude, efficiently. According to various via conditions, different metasurface-based antenna parameters such as return loss (S11), radiation pattern, directivity and surface current distribution are investigated by means of the commercial numerical simulation software, CST microwave studio. Employing the simulation results of the metasurface-based antennas, the artificial neural network (ANN) data set is obtained. 128 activation conditions are trained and tested by Levenberg Marquart learning algorithm. During the ANN procedure, MATLAB is used to obtain accurate results by changing the rate of test and training data set. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

Approximate computing can be considered a well-promising method for improving the critical performance criteria, such as latency and power consumption at the cost of accuracy penalty. The (4,2) compressor is a vital block at the heart of various arithmetic circuits like multipliers. This paper proposed two approximate (4,2) compressors with power and delay improvements with the error-correcting module. The simulation results based on 7 nm FinFET technology show that the proposed designs compared to the most efficient related approximate (4,2) compressors, reduce delay, power, and energy consumption. Furthermore, according to the comprehensive Monte Carlo simulations, the robustness of the proposed designs in the presence of significant FinFET process variations compared to the previous compressors is proven. In addition, an image multiplication process assesses the effectiveness of the proposed approach in the qualitative assessment of the inexact multiplier. The obtained results indicate acceptable accuracy of inexact multiplier based on the proposed approximate (4,2) compressor. [ABSTRACT FROM AUTHOR]

A novel four-element MIMO antenna with reconfigurable bandwidth characteristics is reported in this paper. The proposed antenna is evolved using a chamfered rectangular monopole operating from 2.2 GHz to 11.3 GHz. The frequency selectivity of the antenna is accomplished by introducing a bandstop filter adjacent to the microstrip feed line of the UWB monopole. The proposed bandstop filter is constructed by introducing a notch in an all-pass filter. The notch band is carefully chosen such that the integration of the filter with the UWB radiator provides resonances centred around 2.4 GHz and 3.6 GHz suitable for WLAN communications. The bandwidth selection is accomplished using feed selection which is enabled using a set of PIN diodes. This makes the antenna work in two distinct operating modes, namely, the UWB mode (2.2 to >12 GHz) and the dual-narrowband mode (D-NB) (2.4 & 3.6 GHz). The research is further extended towards the construction of a MIMO antenna suitable for mobile networks. The prototype of the proposed four-element antenna is fabricated and analysed for S-parameters, radiation, and diversity characteristics. The average gain of the MIMO antenna array is greater than 4.5 dBi in the UWB/D-NB mode. The proposed antenna is suitable for low power UWB communications and high throughput WLAN such as IoT, sub 6 GHz 5 G communications, etc. [ABSTRACT FROM AUTHOR]

In the modern power electronic environment, application of low power, small size and high speed drives is achieving more prominence. In domestic appliances such as power tools, high speed fans, high power blowers etc., electric motors with high performance are attaining huge acceptance. The conventional variable speed drives employed diode bridge rectifier (DBR) and DC-to-DC converter-based methodologies, which hampered the supply by introducing current harmonics and conduction losses. This made these topologies unacceptable as per the standards set by the global power electronic authorities. Although there have been large number of developments in motors and control strategies, the risk and complexity of such drives become bottlenecks in implementation. In this paper, the conventional DBR-based DC-to-DC converter-fed drives are compared and analysed with a bridgeless dc-dc converter and a voltage source inverter-fed motor drive. Due to the low power, high-speed application of Brush Less DC (BLDC) motor, the same is selected for the aforesaid drive scheme. It is envisaged to ascertain that the combination of the same will help achieve almost near Unity Power Factor (UPF) and more efficient control compared to the conventional speed control topologies. [ABSTRACT FROM AUTHOR]

Increasing short-circuit fault currents is one of the critical challenges in microgrids (MGs). In this paper, a novel AC/DC fault current limiter (ADFCL) is proposed to limit short circuit current of both DC and AC sides in hybrid AC/DC MGs (ADMGs). It includes two AC and DC ports, installed between AC MG (ACMG) and DC MG (DCMG). Also, it has only one common limiting resistor for limiting short circuit current in faulty MG without affecting the performance of the healthy MG. The proposed ADFCL power circuit, its principle of operation and control system are presented. Then, the feasibility of the ADFCL is verified by simulation in PSCAD/EMTDC environment and finally, a prototype is built. Both experimental and simulation results reveal that the ADFCL can limit the faulty MG by using only one limiting resistor without affecting the performance of the healthy one, which reduces the cost of using FCL in ADMGs. [ABSTRACT FROM AUTHOR]

Multiple Input Multiple Output (MIMO) system with orthogonal frequency division multiplexing (OFDM) is a promising physical layer candidate for the current and future wireless standards. MIMO increases system throughput while OFDM maximizes spectrum efficiency. To reduce the impacts of frequency selective fading and increase the capacity, MIMO requires precise channel state information (CSI). The presence of carrier frequency offset (CFO) introduces intercarrier interference (ICI) among the subcarriers which degrades the system performance. MIMO channel estimation is done under the assumption of perfect frequency synchronisation between the transmitter and receiver, or zero CFO. However, such an assumption is incorrect for time-varying and frequency-selective wireless channels, and the presence of CFO has an impact on channel estimation accuracy. In the existing methods, CFO and channel estimations are carried out independently using separate training sequences which reduces the spectral efficiency. As a result, the pilot aided interpolation approach is proposed in this paper for the joint estimate and compensation of CFO and channel effects using the same set of pilot tones. Theresults show that the proposed method offers precise CFO and channel estimation which improves the bit error rate performance and carrier to interference power ratio (CIR) of MIMO-OFDM system. [ABSTRACT FROM AUTHOR]

Due to its notable advantages, Modular Multilevel Converter (MMC) is considered to be employed for medium-voltage motor drives. In this paper, a high-performance sensorless vector control scheme inspired from the Model Reference Adaptive System (MRAS) approach is developed for an MMC-fed induction motor. Besides the well-known vector control scheme advantage, i.e. independent control of motor flux and torque, eliminating the speed sensor will notably improve the reliability of the proposed method. The motor flux components in the αβ frame are determined and used for estimating the speed value. As the errors of flux components calculated by the motor voltage and current models are continuously compensated by a MRAS-based loop, the estimation would be accurate for a wide range of speeds. Moreover, several modifications are considered to add the capability of voltage balancing for submodule capacitors, and also circulating current control to the proposed scheme. The two aforementioned features are necessary for efficient operation of MMC. Moreover, the circulating current control capability is mandatory for injection of different circulating current profiles, which is required for reducing the flying capacitors' voltage ripples at low speeds. Finally, different performance aspects of the proposed method are experimentally assessed and validated. [ABSTRACT FROM AUTHOR]

Electronic circuits must address electromagnetic interference due to high-speed transmissions and simultaneous switching actions. This paper proposes a design of novel planar EBG structure L Bridge with embedded slit type with 3 × 3 array fashion, which can be used in a plane layer of a printed circuit board to reduce simultaneous switching noise (SSN). Two sets of pattern such as alternate structure and entire embedded pattern are considered and measured the cut-off frequencies. The performance of the structure is simulated, experimentally verified using R&S®ZVH Vector Network Analyser for the frequency range 0.1 to 10 GHz and compared the outcomes. It is observed that for the −50 dB of noise depth, proposed structure is achieved 1.6 GHz to 10 GHz as lower and upper cut-off frequency. In addition, this concluded the noise suppression using equivalent circuit model and parallel plate wave guide theory. Signal integrity on this structure is also analysed with single-ended and differential mode signal transition. Eye pattern is generated and compared for measuring and validating the signal quality while using this EBG structure. [ABSTRACT FROM AUTHOR]

In this paper, a multi-digit ternary (multi-trit) Wallace tree-based multiplier in CNTFET technology is presented. In this work, a modified 1-trit multiplier is applied to reduce the number of the CNTFETs where it uses unary operators to estimate the product and the carry. An optimised architecture of a multi-digit ternary adder is also presented. It is applied at the last stage of the multiplier to reduce the overall propagation delay. Hence, higher speed is achieved spending a few more number of CNTFETs. The proposed design is simulated in HSPICE using Stanford University's 32 nm CNFET technology model. Simulation results show significant improvements in power delay products and hardware utilisation. The proposed 3-trit multiplier applies 750 number of CNTFETs where the PDP is 75 fJ. This represents an approximately 20% improvement in the PDP while more than 100 CNTFETs are saved. For further evaluation, the proposed structure is also extended to 6, 9 and 12-trit multipliers. [ABSTRACT FROM AUTHOR]