Search

In this work, the current transient method was conducted for trap analysis in the p-GaN gate high-electron-mobility transistors (HEMTs) in the OFF-state. Based on the traditional detrapping transient measurements, the pure recovery transients can be isolated by subtracting the undetected part caused by the measurement conditions. A comparison of the measured and actual recovery transients under different drain filling voltages was presented. It suggested that this method can be effective to analyze the unregular transient curves and distinguish the charge trapping type preliminarily. In addition, three traps were identified based on the time constant spectra and the hidden absolute amplitudes of traps can be corrected using the differential amplitude spectra. The information of trap levels in the buffer layer and AlGaN barrier layer was revealed, consisting of three electron traps with energy levels of 0.313, 0.265, and 0.467 eV. The identification of the traps may provide a physical foundation for better understanding of the drain-induced trapping effect during the OFF-state in p-GaN HEMTs. [ABSTRACT FROM AUTHOR]

We derived a simplified analytical expression to estimate the dynamic reduction in the 2DEG density due to the buffer trapping (${n}_{T}$) in GaN-based high-electron-mobility transistors (HEMTs). To compute ${n}_{T}$ , gate-lag drain current transient (DCT) measurements are carried out at a fixed temperature for different ${V}_{GS}$ points. The dynamic decrease in the 2DEG due to the Fe-related trap at ${E}_{C}$ -0.5 eV is found to be ~ $3.4\times10$ 11 cm−2 in AlGaN/GaN HEMT; thus, ${n}_{T}$ is an essential quantity to evaluate the current collapse effects in HEMT. The validity of the expression is further demonstrated in the C-doped HEMTs. The calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.14 eV is about $9\times10$ 12 cm−0 in InAlN/GaN HEMT with C-doped buffer, and the calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.33 eV is ~ $1.2\times10$ 13 cm−2 in AlN/GaN HEMT with C-doped buffer. These values reveal that current collapse effects are more pronounced in the C-doped HEMTs than the Fe-doped HEMTs. Thus, this work is an important first step before further improvements in the model for computing buffer trap concentration. [ABSTRACT FROM AUTHOR]

Basic ingredients universally available in the carrier transport of conductive solids are proved to be sufficient (not necessary) conditions for the formation of memory while symmetry, or the lack of it, plays a decisive role in the nature of this response. It suffices that the input driving frequency is of the order of the inverse relaxation time and that the nonequilibrium carrier densities are in the order of the quasi-equilibrium ones. Thus, memristive response with ON and OFF states at zero voltage, Type I, and vanishing ON– OFF ratio, Type II, arise naturally according to simple symmetry constraints and are contrasted here in a fully analytical picture. Figures of merit for the conductance and the robustness of the memory response are presented in the form of concise correlations between general intrinsic microscopic parameters such as relaxation times, activation energies, and efficiencies with external drives: voltage pulses, temperature, and illumination. Explicit analytical expressions unveil the mimicry of inductive- and capacitive-like leaning impedances without the need of relaxing the interpretation of flux that has been used for more stringent definitions of memristors. [ABSTRACT FROM AUTHOR]

This article proposes a new driving scheme based on an n-type low-temperature polycrystalline silicon (LTPS) four-transistor-two-capacitor (4T2C) pixel circuit to improve the quality of motion images of active matrix organic light-emitting diode (AMOLED) displays. The proposed driving scheme can prevent the effect of the lateral leakage current flowing through the OLED common layer by keeping the pixels in the upper and lower row lines in a nonemitting hold period during the program period. The simulation results show that all RGB colors maintain a shooting amount ratio (SAR) below 1% from the first frame when the image is switched from black to white, even for a concentration of the high p-doped hole transport layer (p-HTL). In addition, the parasitic capacitances of the 4T2C pixel circuit that causes OLED current errors are thoroughly analyzed for high luminance uniformity. A 1.5-in 326 pixels per inch (PPI) AMOLED panel based on the proposed driving scheme was fabricated. The results of our measurements show that the SARs of RGB colors are 0.8%, 0.2%, and 0.9%, respectively, and the average ${x}$ -coordinate shift of the color is 0.007 during the transition between black and white images due to the effective suppression of the lateral leakage current. Therefore, we demonstrate that the proposed driving scheme is suitable for AMOLED displays that require high-quality motion images. [ABSTRACT FROM AUTHOR]

Using the framework developed in the first part of this work, we demonstrate the capabilities of the extended two-state nonradiative multi-phonon (NMP) model by reproducing leakage current characteristics of two selected technologies. First, we identify the temperature-activated leakage mechanism in SiC / SiO2 stacks using a tens of nanometer thick thermally grown oxide as trap-assisted tunneling (TAT) through defects. Interestingly, this effect can be reproduced with the same parameters in a SiC / SiO2 stack with deposited oxide. Our simulations demonstrate that these charge transition centers are distributed within only a few nanometers from the SiC / SiO2 interface. The low thermal activation of the leakage current is linked to the low relaxation energies of the involved traps compared with those typically involved in bias temperature instability (BTI) and Random Telegraph Noise (RTN). Second, a similar mechanism can explain TAT characteristics and transient charge trapping currents in Metal–Insulator–Metal (MIM) capacitors with a ZrO2 insulating layer. By comparison of our model parameters to theoretical density functional theory (DFT) calculations, we identify self-trapped electrons (polarons) as a likely cause for these effects, as they have the required low relaxation energies. [ABSTRACT FROM AUTHOR]

Compact modeling of charge trapping processes in GaN transistors is of fundamental importance for advanced circuit design. The goal of this article is to propose a methodology for modeling the dynamic characteristics of GaN power HEMTs in the realistic case where trapping/detrapping kinetics are described by stretched exponentials, contrary to ideal pure exponentials, thus significantly improving the state of the art. The analysis is based on: 1) an accurate methodology for describing stretched-exponential transients and extracting the related parameters and 2) a novel compact modeling approach, where the stretched exponential behavior is reproduced via multiple RC networks, whose parameters are specifically tuned based on the results of 1). The developed compact model is then used to simulate the transient performance of the HEMT devices as a function of duty cycle and frequency, thus providing insight on the impact of traps during the realistic switching operation. [ABSTRACT FROM AUTHOR]

The present state-of-the-art of junction-based diamond electronic devices is limited by the challenges inherent to the synthesis of n-type layers, where the dopant itself forms defect complexes that are donor compensating centers. Recently, the fabrication of diamond Schottky p-i-n diodes (SPINDs) by chemical vapor deposition (CVD) of intrinsic diamond films followed by an n-type layer on p-type diamond substrates has been reported to demonstrate excellent diode-like behavior with high rectification factors and surface barrier height at elevated temperatures. However, due to the ultrawide bandgap of diamond and small contact area of the devices, it is challenging to characterize the defect centers that limit the performance of the SPINDs using conventional capacitance transient spectroscopy. In this article, we report the characterization of defect centers in the diamond SPINDs with a contact area of 280 $\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ using current transient spectroscopy (CTS), which measures thermally induced emission rates from trap centers through change in device current instead of junction capacitance. The CTS scans in the temperature range 80–800 K revealed the presence of five trap-related peaks. Results from density functional theory (DFT) calculations were used to identify the nature of the traps. While most of the detected traps were identified to be vacancy complexes coupled to phosphorus and hydrogen impurities, one trap has been identified as single carbon vacancy. Most of the phosphorus-related defect complexes were observed to be in neutral and/or negative charge states and were identified as acceptor-like states. [ABSTRACT FROM AUTHOR]

Pulse test techniques are widely adopted in characterizing both the static and dynamic performances of semiconductor devices considering various device structures and operating conditions. For gallium nitride (GaN) devices, due to the current collapse phenomenon, fast and accurate measurement of their key electrical parameters, such as dynamic ON-state resistance ${R}_{\text {ds}, \mathrm{\scriptscriptstyle ON}}$ , switching rising time, fall time, switching losses, and short-circuit (SC) robustness, becomes essential. This article presents a comprehensive review of state-of-the-art pulse test setup methods such as the double-pulse test (DPT), multiple-pulse test (MPT), and SC test (SCT) for the first time, which facilitates the GaN device structure design and practical applications in high efficiency and power density power converters. [ABSTRACT FROM AUTHOR]

In this article, a fully physically transient volatile memristor utilizing Mg as an active electrode with a structure of W/MgO/Mg/W was proposed. The fully transient device exhibited remarkable threshold switching (TS) performance via Mg2+ cations migration dynamics and emulated the paired-pulse facilitation (PPF), paired-pulse depression (PPD), and transition from short-term to long-term plasticity of a biological synapse successfully. In addition, a water-assisted transfer printing (WTP) method was exploited to fabricate the fully physically transient system on biodegradable and biocompatible substrates. This study confirms that the fully transient volatile memristor owns outstanding value toward security neuromorphic computing, biodegradable, and bio-integrated electronic systems. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor devices, researchers have proposed different types of high-frequency pulse voltage generators based on power electronic converters to meet the requirements of microorganism inactivation, water pollution purification, and piezoelectric and dielectric electroactive polymer drives. The transient modeling of these high-voltage converters aids in understanding the electrical characteristics of the devices and optimizing their performances. This article analyzes the electrical behavior of a semiconductor switching device (i.e., an insulated gate bipolar transistor) used during the switching transient of the converter and constructs an electromagnetic transient model of the flyback converter that considers both the parasitic elements and the ferromagnetic losses of the transformer. The accuracy of the proposed model is then verified by comparing calculation results obtained using the model with experimental measurement results. [ABSTRACT FROM AUTHOR]

This article studies the underlying physical mechanism and comprehensive characteristics of the N-channel IGBT (N-IGBT) with P-drift region (PD-IGBT). Distinguishing from the conventional N-IGBT with N-drift region (ND-IGBT), the main blocking junction (${J}_{\text {MB}}$) of the PD-IGBT is changed from the emitter side to the collector side, which leads to a significant enhancement effect of dynamic electric field modulation. Based on the effect, the PD-IGBT features fast dynamic electric field (E-field) building speed in the drift region and a high E-field at the edge of the field-stop (FS) layer, which can extract excess carriers stored in the device rapidly during the turn-off transient, thus reducing the turn-off loss (${E}_{\rm {OFF}}$) and turn-off time (${t}_{\rm {OFF}}$) of the device. Moreover, the change of ${J}_{\text {MB}}$ location can also alleviate the E-field crowding phenomenon at the trench gate corner, thus providing an optimized relationship between breakdown voltage (BV) and ON-state voltage, as well as high avalanche energy. Simulation results show that, when compared with the state-of-the-art N-channel ND-IGBT, the PD-IGBT offers 46% shorter ${t}_{\rm {OFF}}$ , 57% lower ${E}_{\rm {OFF}}$ , and 60% larger avalanche energy without compromising other device characteristics. [ABSTRACT FROM AUTHOR]

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique. [ABSTRACT FROM AUTHOR]

We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage ${(}{V}_{\text {OFF}}{)}$ and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified ${V}_{\text {OFF}}$ and current collapse (CC). An expression for the modified ${V}_{\text {off}}$ helps capture the pulsed current–voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and RC sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models. [ABSTRACT FROM AUTHOR]

Identifying defects/traps is of vital importance for the implementation of high-performance Ga2O3 power devices. In this work, majority and minority carrier traps in beta-gallium oxide ($\beta $ -Ga2O3) have been investigated and identified by means of deep level transient spectroscopy (DLTS) in Ni/ $\beta $ -Ga2O3 Schottky barrier diode (SBD) and NiO/ $\beta $ -Ga2O3 p+-n heterojunction diode (HJD). For both diodes, a dominant energy level of majority carrier (electron) trap states is determined to be ${E}_{C}-$ (0.75–0.79) eV with a concentration of (2.4–4.1) $\times 10^{{13}}$ cm $^{-{3}}$. Meanwhile, an additional trapping level at ${E}_{V} +0.14$ eV with a concentration of 1.2 $\times 10^{{14}}$ cm $^{-{3}}$ yield is present in NiO/ $\beta $ -Ga2O3 bipolar HJD but absent in the Ni/ $\beta $ -Ga2O3 SBD unipolar counterpart. The detection of such minority carrier traps originates from the hole injection through trap-assisted tunneling (TAT) from $\text{p}^{+}$ -NiO to $\beta $ -Ga2O3. The bias- and frequency-dependent DLTS characteristics identify that such shallow-level minority carrier traps are located in the $\beta $ -Ga2O3 bulk region rather not interfacial states at the NiO/ $\beta $ -Ga2O3 heterointerface. The identification of both majority and minority carrier traps in this work may shed light on the in-depth understanding of carrier transport mechanisms in Ga2O3-based unipolar and bipolar power devices. [ABSTRACT FROM AUTHOR]

High-voltage p-i-n diodes for space applications are sensitive to single event burnout (SEB), which may cause the failure of the entire electronic system. This article describes the SEB failure mechanism of high-voltage p-i-n diodes with field limiting rings (FLRs) termination structure, based on the electro-thermal coupled transient simulation model in the Sentaurus TCAD simulator. The simulation results show that the catastrophic failures result from the intense local heating at the edge of the main junction, because the high electric field strength at this region induces strong impact ionization of the charge carriers. The strike at the edge of the main junction shows the strongest sensitivity to SEB since the energetic particle-induced carriers are deposited exactly at the high electric field region. Then, a novel SEB hardening technique of localized carrier lifetime control at the edge of the main junction region is proposed based on the analysis on the failure mechanism. Our simulation results demonstrate that the reduction of the localized carrier lifetime can alleviate the peak electric field and reduce the local heat accumulation, thereby improving the SEB performance of high-voltage p-i-n diodes. [ABSTRACT FROM AUTHOR]

In this study, the single-pulse avalanche capability of two types of 1.2-kV silicon carbide (SiC) trench MOSFETs was investigated through unclamped inductive switching (UIS) testing and numerical TCAD simulation. It was found that the UIS failure mechanisms differed in the two MOSFETs. In the asymmetric trench MOSFET, the failure was caused by high temperature, which can damage the SiC layer during the UIS transient, whereas in the double-trench MOSFET, the failure was caused by a high electric field concentration at the trench gate bottom oxide, and the physical damage was confirmed by optical beam induced resistance change (OBIRCH) and scanning electron microscopy (SEM) cross-sectional analysis. In addition, the UIS-based local damage phenomenon was investigated with varying inductance. Nonuniform contact resistance may have been a cause of the avalanche current concentration. [ABSTRACT FROM AUTHOR]

In this work, the steady-state and transient behavior of the metal–insulator–semiconductor tunnel diodes with designed high-low (H/L) oxide layers were studied, by performing experiments and TCAD simulations. The H/L oxide layers were formed by thickening the oxide around the gate edge while still in a tunneling-transparent thickness. This could reduce the leakage or tunneling current at reverse bias by decreasing the minority carrier density near the gate edge via the induced lateral electric field caused by H/L oxides. The characteristics of devices with various designed parameters were under investigation to discover the necessary conditions for the tunneling current reduction. Due to the leakage current reduction, the enhancement of transient current was found out, accompanied with enlarged transient capacitance change. Steady-state and transient simulation could help to confirm the observed phenomenon and also illustrated the existence of lateral electron current flow that reduced the minority carrier density near the gate edge at reverse bias. A memory operation using the H/L device was demonstrated. The read current at 120 ms improved more than an order of magnitude in current window with respect to planar. The stable performance under endurance testing made the H/L device a possible future volatile memory application. [ABSTRACT FROM AUTHOR]

In this work, Sentaurus TCAD was used to study the transient surge current mechanism of the 4H-SiC merged pin and schottky (MPS) diode. For the first time, a structure combining multicells with transition region was used to analyze the transient surge current mechanism of the MPS diode. The electrothermal simulation analysis of the surge characteristics of the MPS diode is carried out. Internal carrier distribution and lattice temperature in the surge current transient process of the device are mainly studied. The simulation results show that the hole current distribution and the electron current distribution in the MPS diode are not uniform. In the transient process of surge current, the transition region first enters the bipolar conduction mode, and then, the cells in the active region enter the bipolar conduction mode in the order from outside (close to transition region) to inside. The voltage–time (${V}$ – ${t}$), maximum temperature–time (${T}_{\text {max}}$ – ${t}$), and ${I}$ – ${V}$ curves of MPS diode in surge current events are obtained by simulation. Combined with the current density distribution diagram, the device behavior of multiple critical time nodes is analyzed in detail, and a reasonable explanation is given. In addition, the influence of different transition region contact types on the internal current distribution of the MPS diode is studied, and the simulation results are reasonably explained. [ABSTRACT FROM AUTHOR]

This article proposes a new junction barrier Schottky diode (JBSD) design based on P-GaN/N-Ga2O3 heterojunction with faster switching characteristics and higher breakdown ability than the traditional two-terminal power switches. Calibrated models have been used for technology computer-aided design (TCAD) simulations of the proposed JBSD after a comprehensive review of various physical models and model parameters in the present literature. Analysis in terms of static and transient behavior for a varying proportion of PN area to the Schottky contact area (PN:SBD ratio) was looked upon for the JBSD. With the increase of PN:SBD ratio, the reverse voltage handling capability increased as expected, but the reverse recovery time and maximum reverse recovery current decreased. This might be counterintuitive initially, as with an increase in PN:SBD ratio, the PN behavior would dominate over SBD, and slower transient behavior is expected. However, due to redistribution of electric field and the reduction in depletion capacitance across the JBSD with increase in PN:SBD ratio, JBSD with PN:SBD ratio of 8 gives us a breakdown at 1890 V and a switching time of 9.72 ns. Furthermore, a comparison of the transient response with state-of-the-art SiC Schottky diode reveals the efficiency of the proposed structure in terms of reverse recovery parameters to be significantly better, translating to 7.4 times lower power losses at higher frequencies. Overall, the design and analysis presented here suggest the promising potential of P-GaN/N-Ga2O3 vertical devices for high-voltage and fast switching applications. [ABSTRACT FROM AUTHOR]

In this article, the single-event-transient (SET) in reconfigurable field-effect transistor (RFET) is evaluated by 3-D technology computer-aided design (TCAD) simulation for the first time. The effects of linear energy transfer (LET) values, electrical bias, strike location, and angle are investigated in detail. For heavy ion with LET of 10 MeV $\cdot $ cm2/mg and characteristic radius of 1 nm, the peak value of drain SET current is up to 0.237 mA for n-type program, which is much higher than the saturated conduction current of $2.22~\mu \text{A}/\mu \text{m}$. The peak SET current increases from 0.18 to 0.36 mA as ${V}_{\text {DS}}$ ranges from 0.8 to 1.4 V. The drain voltage (${V}_{\text {DS}}$) has a great impact on SET response and a higher lateral electric field will worsen the SET effects. The most sensitive position is confirmed to be not only related to the electric field distribution, but also the distance away from drain terminal. A serious SET effect is observed with a smaller angle. Furthermore, the impact of SET effect on NAND2/NOR2 multifunctional logic gates circuit based on RFETs is also evaluated. When striking the end of the changing edge of the input signal, the rise and fall relative propagation delays of NAND2 logic gates circuit are up to 34.49% and 35.04% respectively, with LET of 6 MeV $\cdot $ cm2/mg. This work provides guidelines for RFET radiation-hardened technology in future extreme environment electronics applications. [ABSTRACT FROM AUTHOR]

In this work, we developed the voltage-transient method to characterize the properties of traps in AlGaN/GaN high-electron-mobility transistors (HEMTs) in the OFF-state. By monitoring the drain voltage transients of the HEMTs at various temperatures, three types of trapping mechanism were identified: 1) buffer charge trapping, which occurred on a timescale of approximately 1 ms; 2) charge trapping in the AlGaN layer at the gate–drain edge with the energy level (${E}_{a}$) of approximately 0.54 eV; and 3) surface charge trapping with ${E}_{a}$ of approximately 0.28 eV. In particular, we extracted accurate amplitudes for the first two trapping behaviors and studied the dependence of the trapping effect on the filling bias conditions. The results showed that the buffer charge trapping was primarily affected by the drain voltage, whereas the charge trapping on the drain side of the gate was affected by both the drain and gate voltages; these results were verified by drift-diffusion simulations. In addition, we observed the third trapping behavior, which was apparent in the measurement window beyond 308 K, thus demonstrating the advantages of our method for correctly and effectively monitoring the changes in the peaks in the time constant spectrum. [ABSTRACT FROM AUTHOR]

A TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal–insulator–metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping–detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach. [ABSTRACT FROM AUTHOR]

A stabilization method is presented for the Boltzmann equation (BE) that is based on Godunov’s approach applied directly in the phase space. This makes it possible to perform transient simulations under quasiballistic conditions and to include the Pauli principle in the scattering integral without further approximations. The method ensures positive distribution functions by construction. The BE is solved self-consistently together with the Poisson and Schrödinger equations by the Newton–Raphson method for a nanowire silicon nMOSFET, for which the stationary ${I}$ – ${V}$ characteristics, the small-signal admittance parameters, and the switching behavior are calculated. The large-signal behavior of the MOSFET as an amplifier is evaluated by cyclostationary simulations including power gain and the output power at higher harmonics. The current responsivity of the MOSFET operated as a passive mixer is simulated up to terahertz (THz) frequencies including the quasiballistic case with negligible scattering. [ABSTRACT FROM AUTHOR]

A 600 V-rated insulated gate bipolar transistor (IGBT) with improved turn-on transient characteristics is proposed and investigated by simulation. The proposed IGBT features a built-in voltage-clamping structure. The floating ${p}$ -body adjacent to the trench gate is clamped at an appropriately high voltage before turn-on. This slows down the hole accumulation process in the floating p-body during turn-on transient, and thus the self-charging displacement current through the gate capacitance is reduced. The increasing rate for the gate voltage (dVGE/dt) is then reduced. As a result, the proposed IGBT achieves a 25% decrease in collector current ($I_C$) overshoot and 34% decrease in dIC/dt, when compared with the conventional IGBT with the same turn-on loss (EON), at IC = 250 A/cm2 under hard-switching. Its fabrication process is compatible with conventional trench IGBT. [ABSTRACT FROM AUTHOR]

This report demonstrates the fabrication and performance of a novel, transient, stable breath sensor based on black phosphorus quantum dots (BPQDs) and polyvinyl alcohol (PVA) composite. BPQDs were utilized as the conduction medium, while the PVA provides a flexible substrate that disintegrates in water. The device presents an innovative solution to black phosphorous (BP) degradation in which the copper (Cu) contacts are placed within the filler of the composite, ruling out the effects of surface degradation in the evaluation of the device performance. Stability studies at the end of eight weeks have been included wherein a negligible change in device performance to breath is observed. The sensor demonstrates chemiresistive properties with a change in resistance of ~100% to exhaled breath. The fabricated device was successful in identifying different breath patterns by monitoring the amplitude and the frequency of the device’s current change upon exposure to breath. The fabricated device achieves complete transience in ~10 min when immersed in water. The study opens up possibilities for applications in the fields of biosensors, military, and consumer electronics. [ABSTRACT FROM AUTHOR]

In this work, an analysis of the impact of drain field plate (FP) length on the semi- ON degradation of AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed. A wafer-level characterization, by means of pulsed stress tests, reveals a faster and more severe decrease of the drain current in the linear region for the samples with longer drain FP. 2-D technology computer-aided design (TCAD) hydrodynamic simulations show that a time and field-dependent hot electrons (HEs) trapping takes place at the passivation/barrier interface. The higher drain current decrease in the longer FP samples can be ascribed to an enhanced HE trapping at the drain FP edge due to a different electric field distribution. [ABSTRACT FROM AUTHOR]

In this study, we investigate the threshold voltage (${V} _{{{ \text {th}}}}$) instability of p-gate GaN HEMTs induced by gate bias. Experimental results are acquired by a custom pulse setup for two commercially available devices with an ohmic gate and a Schottky gate. A transient drain current change is observed, which corresponds to a shift of ${V} _{{{ \text {th}}}}$. A negative ${V} _{{{ \text {th}}}}$ instability is identified for the ohmic gate, a mostly positive for the Schottky gate that can also become negative depending on the gate bias voltage and duration. The impact of the gate-bias-induced ${V} _{{{ \text {th}}}}$ instability on the Schottky-gate device is significantly higher compared to the ohmic-gate device, but clearly noticeable at the nominal rated ON-state gate voltage for both devices. Electron depletion and trapping as well as hole accumulation and trapping are identified to cause this transient ${V} _{{{ \text {th}}}}$ instability. [ABSTRACT FROM AUTHOR]

We theoretically investigated the effect of interface traps (${D}_{it}$) at the Si/SiO2 interface on the transient negative capacitance (NC) effect of the ferroelectric (FE) FETs. We used a metal/FE/interlayer/Si (MFIS) capacitor in series with a resistor to simulate the NC effect. Our simulation results show that appropriate ${D}_{it}$ can further improve the subthreshold swing (SS) by tuning the mismatch of the switching rate between free charges (${Q}_{f}$) and polarization charges (${P}$). In addition, we also analyzed the impact of different circuit parameters on the device performance. The following device design can improve the SS characteristics: thicker FE layer, thinner interlayer (DE), lower external resistance, and larger viscosity coefficient. [ABSTRACT FROM AUTHOR]

In this article, a new type of metal–insulator–semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current–voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance–voltage (C–V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices. [ABSTRACT FROM AUTHOR]

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor ${R}_{{1}}$ , and a proportional amplification resistor ${R}_{{2}}$. At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness. [ABSTRACT FROM AUTHOR]

Vertical biristors are small footprint (${4}{F}^{{2}}$) floating base bipolar junction transistors (BJTs) proposed for high-speed volatile memory applications. One key challenge is (i) the high latch-up voltage with Si-based biristors because of the high threshold of impact ionization (II) in Si. In this article, an epitaxial ${n}^{+}/{i}/{\delta {p}}^{+}/{i}/{n}^{+}$ -based vertical biristor is proposed with an asymmetric doping profile that enables sub-bandgap II only in the negative polarity. First, in the negative polarity, a latch-up voltage as low as 0.5 V due to sub-bandgap II is demonstrated. Faster programming with higher bias is observed. Second, erase is demonstrated in the positive bias, where II is insignificant. Overall, a large read window (${\Delta } {I}=\text {0.01 mA}$) with a low variability (${\sigma /\mu }$ in ${\Delta }{I}$) for cycle-to-cycle (C2C < 1%) and device-to-device (D2D < 5%). Retention in excess of $1 {\mu }\text{s}$ is observed, taking into account C2C and D2D variations. A high endurance (> 107cycles) is also observed. Therefore, asymmetrically doped vertical biristor is promising for very low voltage high speed memory application compared to dynamic random access memory (DRAM). [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes. [ABSTRACT FROM AUTHOR]

This article presents design for a 650-V super-junction (SJ) power metal–oxide–semiconductor field effect transistor (MOSFET) which improves tolerance to both single-event burnout (SEB) and single-event gate rupture (SEGR). Experimental measurements of SEGR in a generic commercial planar gate SJ device are used to validate the accuracy of the design. In an SJ device with a planar gate, reducing the neck width improves the tolerance to gate rupture but significantly changes the electrical device characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. The proposed trench gate structure improves the SEGR survivability by a factor of 10. [ABSTRACT FROM AUTHOR]

The gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is investigated and novel structures are proposed for the first time with numerical simulation in this article. The TGU SOI-LIGBT features two U-shaped trench gates, G1 and G2, connected together. The U-shaped trench for G2 serves as a hole barrier trench. A large number of holes accumulate in the U-shaped region during the turn-on transient because of the U-shaped architecture and the hole-blocking effect of G2. The displacement current induced by the nonuniform distributed holes overcharges the gate and leads to high di/dt. In this article, the novel structures (Novel-1 and Novel-2) with G2 partially filled by the polysilicon are proposed for the improvement in gate voltage overshoot while keeping superior turn-on loss (${E}_{ \mathrm{ON}}$). The novel structures (Novel-1 and Novel-2) can suppress the hole accumulation and slow down the rising of the electric potential in the silicon region near the G2. The di/dt can be lowered and the displacement current that overcharges G2 can be effectively shielded. Compared with the conventional TGU structure, the di/dt of the Novel-2 are improved by 56.3% at the same ${E}_{ \mathrm{ON}}$ of 2.4 mJ/cm2. [ABSTRACT FROM AUTHOR]

The distribution of trap states in the active layer of perovskite solar cells is a key limiting factor that largely controls the charge carrier mobility, rate of recombination of trapped charges, and, subsequently, the power conversion efficiency. In the present study, the charge carrier dynamics and the influences of the energetic distribution of trap states over device performance of nickel oxide based inverted perovskite solar cells have been investigated in detail by analyzing their temperature dependent transient photoresponses. The reduction in temperature during electrical measurement has induced anomalous behavior in current–voltage characteristics and distribution of trap states. The tail states energy of the valance band decreases from 150 to 50 meV as the temperature of the transient photocurrent measurement increases from 83 to 300 K. The applied bias significantly influences the shape and location of the density of states distribution, indicating their ionic origin. The transient photovoltage measurement revealed that the devices show rapid recombination of localized photogenerated charge carriers around the orthorhombic to the tetragonal phase transition region. The detailed study of trap state analysis and their various impacts on the device performances will prove beneficial for the fundamental understanding of the device physics, material design, and performance stabilization for perovskite solar cells and related devices. [ABSTRACT FROM AUTHOR]

In this article, a study of the snapback behavior of reverse conducting IGBTs (RC-IGBTs) by means of 2-D TCAD simulations is carried out. Half-cell TCAD models of 1200-V RC-IGBT structures with different snapback voltage levels were generated by varying the peak doping concentration of the punch-through N-buffer region. First observations show that snapback could be an issue for low current switching commutations of paralleled RC-IGBTs operating at low temperatures, where one device falls back into unipolar mode and current is completely misshared. Results show that the RC-IGBT snapback voltage level, circuit variations, and operating conditions play a critical role for determining whether the parallel RC-IGBTs operate in a stable or unstable mode. [ABSTRACT FROM AUTHOR]

This article reports an experimental investigation of transient heat distribution and thermal actuation crosstalk in phase-change material (PCM) germanium telluride (GeTe)-based radio frequency (RF) switches. The RF switches are designed and optimized for efficient thermal energy transport from the embedded microheater to the PCM. Various multiport miniaturized monolithically integrated complex RF components require several switches to be integrated extremely close to each other. Thermal crosstalk is crucial in multiport complex devices to ensure that individual tuning elements actuate independently without influencing nearby switches’ performance. Thermal cross section simulations are performed using multiphysics finite-element modeling (FEM) to optimize the heat distribution within the PCM channel and are experimentally validated via transient thermoreflectance imaging technique with ultrafast temporal and spatial resolution. The devices are fabricated in-house using a custom eight-layer microfabrication process. The optimum device bias conditions, melt-quench sequence, and thermal actuation crosstalk limits are experimentally validated to develop miniaturized monolithic densely packed complex reconfigurable phase-change circuits. It is the first-ever demonstration of experimental transient thermal insights on phase-change RF switches. [ABSTRACT FROM AUTHOR]

Thermal management in a heat source-based electronic package is a necessity for reliable, long-lasting performance, as it is compulsory to dissipate the generated heat effectively. In this study, a novel nickel–phosphorous (Ni–P) alloy coating on an aluminum substrate is proposed to obtain improved thermal properties such as thermal conductivity (k), total thermal resistance (Rth-tot), and device junction temperature (Tj). The performance of the electroless Ni–P coating is observed under different deposition times and test conditions. The morphology of Ni–P coating results in a cauliflower-like grown structure on a substrate with 91.2 wt% of Ni and 8.8 wt% of P. X-ray diffraction spectra indicate the presence of crystalline Ni (111) and (220) peaks and an average crystallite size of 541 nm. The thermal conductivity of the Ni–P coated substrate results in 14.42 W/mK, whereas bare Al results in 8.03 W/mK. The thermal transient measurement results in an impressive difference in both Δ Rth-tot (6.31 K/W, 4.68 K/W) and Δ Tj (11.84 °C, 5.82 °C) under different test conditions. It is found that 0.33-μm surface roughness with a 7.5- μm coating thickness potentially improves the thermal behavior of Ni–P substrates, and it is believed that Ni–P is suitable for being used as an alternative coating option for electronic packages. [ABSTRACT FROM AUTHOR]

In this article, a highly reliable radiation-hardened-by-design (RHBD) 10T static random access memory (SRAM) cell is proposed. In space, the impact of alpha particles and cosmic radiation flips the node data resulting in loss of data in conventional 6T SRAM. The proposed SRAM has quad-nodes, which stores the data. The architecture is designed with a quad-latch topology and simulated in 65-nm CMOS technology with a supply voltage of 1.2 V. The result shows that the design can tolerate both 0 to 1 and 1 to 0 single event upset errors on any one of its nodes. The read and write access times of the proposed design are 88.78 and 241.77 ps, respectively. The static noise margin for read, write, and hold operations are 379.01, 906.51, and 637.1 mV, respectively. The proposed architecture takes an area of 6.52 μm. [ABSTRACT FROM AUTHOR]

Unique electrothermal properties of graphene and the chemical nature of its degradation present a compelling set of conditions for the exploration of its breakdown at different time scales. In this work, we give a phenomenological description of graphene’s electrical breakdown ranging from a nonequilibrium (transient) electrothermal state to far-equilibrium state while spanning a time scale from few nanoseconds to few minutes. The intricate roles of Pauli-blocked states, intraband heating, and mechanism of degradation in defining a safe operating area (SOA) have been explored. The time and field evolution of defects, resulting in defect-by-defect breakdown, have been studied using Raman spectroscopy. The unified mechanism of breakdown discussed here provides a basic understanding of reliability of graphene-based devices under high-current and/or high-field conditions as well as degradation due to its prolonged operation. [ABSTRACT FROM AUTHOR]

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows 1.14×/1.17× shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay. [ABSTRACT FROM AUTHOR]

We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in OFF-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements. [ABSTRACT FROM AUTHOR]

The transient performance of gallium arsenide (GaAs) photoconductive semiconductor switches (PCSSs) triggered by laser diodes (LDs) at nano-joules (nJ) energy is of great significance for the potential high-power applications at high repetition rates. An opposed-contact GaAs PCSS with Ni/AuGe/WTi/Au electrodes is presented at single-shot and 1-kHz excitation. The influences of bias electric field up to 80 kV/cm on nonlinear characteristics are investigated quantitatively with a carriers’ avalanche multiplication factor as high as 0.8 ×104. The effect of electric field on the carriers’ dynamic process and thermal accumulation in repetitive operation is analyzed. The transient electric field distribution is demonstrated by an ensemble Monte Carlo simulation. [ABSTRACT FROM AUTHOR]

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications. [ABSTRACT FROM AUTHOR]

In this work, the study of the single event effects (SEEs) in capacitor-less one-transistor dynamic random access memory (1T-DRAM) based on an indium gallium arsenide on insulator (InGaAs-OI) transistor is conducted for the first time. The electrical properties of the 90-nm device are numerically simulated to determine appropriate operation condition. The successful memory behaviors are observed due to the gate-induced drain leakage (GIDL) programming method. The impacts of different linear energy transfer (LET) values, high-energy particle (HEP) strike positions and directions, and HEP hitting moments on the memory performance are investigated via simulations. Unlike the conventional SOI device, the source and drain in 1T-DRAM cells are found to be sensitive to SEEs with a higher transient current. The single event upsets (SEUs) are found to occur only when the HEP hits the device at reading “0” state and holding state before read “0.” An increased read-out current is obtained after the HEP strike due to the GIDL- and SEE-induced accumulative floating holes. The related mechanisms are discussed in detail. These results and discussions are useful for the development of the SEE hardening of 1T-DRAM-based embedded memory for space applications in the future. [ABSTRACT FROM AUTHOR]

In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies. [ABSTRACT FROM AUTHOR]

The (doped-)hafnia-based’ ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope low-power logic device. This requires accurate modeling of the metal-ferroelectric-insulator-silicon (MFIS) gate stack electrostatics. Here, we present a hardware-validated FeFET compact model that resolves three key aspects in the MFIS electrostatics pertaining to a multidomain ferroelectric (FE) layer: 1) the nonradiative multiphonon process-based charge trapping; 2) the source-to-drain channel percolation due to spatial nonuniformity of FE domain switching; and 3) the nucleation-growth domain reversal dynamics using a phenomenological formalism. The polarization charge is calculated by discretized domain switching in transient under distributed coercive fields. Based on the comparison of the model versus experimental data on Hf0.5Zr0.5O2 n-FeFET hardware, we prove that the onset of FE VTH lowering starts with the source-to-drain percolation path formation when enough FE domains have been flipped up by the gate bias. We further demonstrate that the field-independent domain growth is the fundamental origin of the measured steep subthreshold slope during the downward ID – VG sweep. The model ultimately aims to lay down the groundwork for a unified FeFET compact model for both memory- and logic-oriented applications. [ABSTRACT FROM AUTHOR]

Traditional charge pumping (CP) technique relies on trap-assisted recombination from the source/drain to the body contact to characterize interface trap density (Nit) of classical bulk MOSFETs. A variant of the technique called single pulse CP (SPCP) allows interface trap characterization even if the bulk contact is absent, as in silicon-on-insulator (SOI) MOSFET. Unfortunately, neither technique is useful for devices with source-body-tied (SBT) and inhomogeneous channel doping profile, as in lateral diffused MOS (LDMOS) power transistors. Here, we propose a generalization of the CP/SPCP techniques, called Super SPCP (S2PCP), to extract position-resolved localized degradations (ΔNit) in an SBT LDMOS. Careful TCAD modeling and experimental characterizations demonstrate the effectiveness of the proposed approach. Our analysis provides deep insights into the physics of the SPCP technique, demonstrating that the approach can be used to characterize a variety of transistors with nontraditional doping profiles and contact configurations. [ABSTRACT FROM AUTHOR]

During the last ten years, the miniaturization of nanoscale field-effect transistors (FETs) predicted by Moore’s law has confronted an aggressive scaling down of the FET architecture (geometry and material) of nanoelectronics devices including phone mobile and computers. Built on thinner Fin body, FinFETs technologies are nonplanar devices based on scalable architecture suitable for the industry and nanomanufacturing methods. However, those emerging nanodevices suffer from thermal challenges related to self-heating effects and highest heat dissipation caused by thermal penetration. In this article, we report the nanoscale thermal transport in sub 7-nm FinFETs technology based on phonon hydrodynamic equation (PHE). Furthermore, we highlight feasible strategies to enhance the heat ability, which can improve the thermal stability of the nanodevice. This work presents a new physical picture of thermal performance optimizations in existing and future nanoelectronics devices. [ABSTRACT FROM AUTHOR]

PrMnO3 (PMO)-based resistive random access memory (RRAM) shows selector-less behavior due to high-nonlinearity. Recently, the nonlinearity, along with volatile hysteresis, is demonstrated and utilized as a compact oscillator to enable highly scaled oscillatory neurons, which enable oscillatory neuromorphic systems found in the human cortex. Hence, it is vital to understand the physical mechanisms behind such a volatile hysteretic behavior to provide useful insights in developing a device for various neuromorphic applications. In this article, we present a detailed investigation of the transient characteristics and propose a physical mechanism to replicate the observations by simulations. First, we investigate the transient switching dynamics of the hysteresis with the voltage ramp rate. We observe that the voltage window initially increases and later decreases as the ramp rate is increased—while the current window reduces monotonically. Second, an analytical electrothermal model based on space charge limited current (SCLC) and 1-D Fourier heat equation with a lumped device model is proposed to model the codependent heat and current flow. Finally, we show that the interplay between the self-heating due to the current and the current dependence on the temperature is accurately modeled to reproduce the hysteresis dependence on the various voltage ramp rate. Such a detailed understanding of the device PMO RRAM volatile hysteresis may enable efficient device design required in neuromorphic computing applications. [ABSTRACT FROM AUTHOR]