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The article presents invitation for posters and papers for the 2013 IEEE International Reliability Physics Symposium (IRPS) to be held in Monterey, California from April 14-18, 2013. Among the areas where papers should be focused include electronic systems, automotive reliability, and circuit aging simulation. It notes the awards to be given by IRPS including Outstanding Paper, Best Student Talk, Best Poster, and Best Paper.

A high-resolution active-matrix microencapsulated electrophoretic display (EPD) driven by polycrystalline-silicon thin-film transistors (poly-Si TFTs) with integrated drivers has been developed for the first feasibility study of electronic paper. The poly-Si TFTs were fabricated with a low temperature process below 425 °C. Microencapsulated electrophoretic material was coated on the TFT backplane, which was driven at 18 V. The resolution of the display is quarter VGA (video graphics array), and pixel pitch is 131 ppi (pixels per inch). As a result, this display offers a wide viewing angle, high contrast ratio and nonvolatilization of data. In addition, four-level grayscale images were also achieved by using an area ratio grayscale (ARG) driving method. [ABSTRACT FROM AUTHOR]

We have fabricated fully transparent high performance flexible nickel-doped zinc oxide thin-film transistors (NZO TFTs) on flexible plastic substrates using magnetron sputtering. The effects of active layer thickness on the performance of NZO TFTs was investigated. We found that the channel layer thickness has a notable influence on the characteristics of NZO TFTs. The electrical characteristics of NZO TFTs reached the optimization when the active channel layer thickness was 71 nm, with a low off-current lower than 1 pA, a high on/off drain current ratio of 2.1 \times 10^9 , a high saturation mobility of 27.5 cm ^2\cdot \mathrm V^-1\cdot \mathrm s^-1 , a steeper subthreshold swing of 67 mV/decade, and a low threshold voltage of 1.88 V. It is demonstrated that NZO is a promising active channel layer materials for future transparent flexible displays. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

In recent years, triboelectric nanogenerators (TENGs) have been increasingly attracting attention owing to the ability for converting multiple mechanical energy into electricity. In this paper, we first propose a multifunctional conductive copper tape-based TENG (CCT-TENG) that is constructed completely using one piece of conductive copper tape. The triboelectric pairs, supporting structure, and conductive electrode were composed using bottom paper, silicone oil, and copper foil, all of which came from one roll of conductive copper tape. The approximate output power density of the CCT-TENG reached $240.1~\mu \text{W}$ /cm2. By spraying the aqueous solution of LiCl onto the surface of the bottom paper, a CCT-TENG incorporating LiCl was fabricated and used as a self-powered active sensor to detect the relative humidity (RH) of the environment. The obtained results revealed that the humidity sensor had good humidity response, response linearity, and reversibility. In addition, the RH was reflected by the brightness of light-emitting diodes (LEDs) that was driven by the humidity sensor. This paper realizes a promising, affordable, and portable integration of power supply systems and sensing systems, which can promote the application of TENG in the field of electronic detection device and environment monitoring. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics. [ABSTRACT FROM AUTHOR]

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer. [ABSTRACT FROM AUTHOR]

A high-harmonic traveling-wave tube (HHTWT) is designed, developed, and tested in this paper. This device is configured as a multiplier–amplifier with Q-band input signals and its third harmonic, i.e., D-band output power. The tested result demonstrates that 280 mW at 133.5 GHz is obtained as a result of 200 mW at 44.5-GHz input signal. The simulation and experiment validate that the high-harmonic radiation can be generated and amplified in the HHTWT. The approach described in this paper could find application in exploring high power, wideband tunable terahertz source. This paper is expanded from a conference paper on IVEC 2017. The detail design produce and tested result are added in this paper. The explanation of the simulation and tested results is also presented. [ABSTRACT FROM AUTHOR]

The article highlights call for papers from Ieee Transactions on Electron Devices on several topics including advanced transistors; gate dielectrics; and power devices.

The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

The article offers information on electronics devices, complementary metal–oxide–semiconductor (CMOS) logic, power and memory. Topics discussed include electronics devices with features related to experimental results and theoretical model; include advanced transitory with features of self-heating effect and variability; and discusses power devices like the metal–oxide–semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT).

The article talks about the reliability of electronic devices as an issue for technology, impact of Bias Temperature Instability on CMOS logic devices and evolving Hot Carrier Degradation and Self Heating Effect. It talks about degradation of program window, development in the field of device reliability and topics that includes Advanced Transistors, Gate Dielectrics and Memory Devices.

It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

Thin-film transistors were fabricated using 45-nm thick ZnO deposited by pulsed laser deposition and 15-nm thick Al2O3 gate insulator deposited by atomic layer deposition. A 1-D model with a constant density of interface states above and below the conduction band edge is used to explain the current-voltage characteristic. This model does not create distortion of transconductance versus gate voltage at low gate voltage that can be created by exponential tail or Gaussian distributions of interface states. The “subthreshold” regime is at the top ZnO surface away from the bottom gate, but subthreshold swing is controlled by interface states at the ZnO/Al2O3 bottom interface. The observed increase in mobility with gate voltage is delayed by filling of the interface states above the conduction band edge. Interface state filling and a rapid increase in mobility with increased gate voltage produce an apparent large threshold voltage as extrapolated from a linear fit to current measured at large gate voltage. The difference between threshold voltage and turn-off voltage is an important figure of merit (FOM) that should be kept as small as possible. In this paper, FOM is 2.5 and 1.8 V for 0.1 and 6 V drain voltage, respectively. [ABSTRACT FROM PUBLISHER]

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

A foreword to "IEEE Transactions on Electron Devices" is presented.

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM) is often considered as a strong candidate for storing the weights in non-von Neumann neuromorphic computing systems. This paper studies how nonideal memory characteristics, which include programing error, read fluctuation, and retention, affect the inference accuracy of the analog ReRAM neural networks by incorporating memory characteristics extracted from 1-Mb ReRAM into a simulated inference-only neural network. This paper also shows that the different layer in the network can tolerate different amount of such imperfects. We learned four key points: 1) the conductance range of memory with less relative fluctuation is preferred for designing the weight-conductance mapping; 2) the control of programing error is essential for high inference accuracy; 3) retention-induced conductance drift can be fatal to the neuromorphic system. A compensation scheme is proposed in this paper which can effectively recover the inference accuracy; and 4) for multilayer networks, avoiding weight errors in the front layers can help to maintain the inference accuracy by reducing calculation error which may otherwise accumulate and pass down the networks. The concepts and approaches of this paper can also be applied to evaluate other types of nonvolatile memories for artificial neural networks. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

In this paper, we aim to theoretically and experimentally study an organic light emitting diode (OLED) in a planar microcavity. One important issue that should be considered is to find an optimal design for an OLED in a microcavity: on one hand, the OLED thickness needs to be adjusted to get resonance at the desired wavelength, on another hand, the location of the emitter dipoles with respect to the metal electrode has to be consistent with the antinode condition of the emission wavelengths. This latter is important to improve the efficiency of the standing wave within the OLED microcavity. In this paper, we provide a theoretical model and carried out experiments using a microcavity OLEDs to validate the proposed model. The theoretical model is based on a classical approach valid in the so-called weak-coupling regime, which is the working regime of the considered microcavity OLED. The spontaneous emission is described as an electric dipole and some examples with experimental data are discussed in order to validate the applied approach. [ABSTRACT FROM AUTHOR]

Many methods have been proposed for the experimental determination of the collector resistance in bipolar junction transistors and HBTs. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs with a large variety of device sizes fabricated in different technologies and generations, including high-speed and high-voltage transistors. First, the accuracy of those methods, which are based on an extraction from single-transistor characteristics, is evaluated from simulated data using a sophisticated compact model and, where applicable, also device simulation. This approach allows the origin of observed inaccuracies or failures of certain methods to be identified. Second, the test structure-based methods are reviewed, and third, all methods were applied to experimental data. This paper and its results provide insight into each method’s accuracy; its application limits with respect to a technology, a device size, and an operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

A three-section coupled-cavity traveling-wave tube (CC-TWT) has been developed for avionic applications. The design parameters for a TWT operating in ${X}$ -band with a high average power, high power, high efficiency, high duty, wideband, low weight, and rugged structure have been obtained. Data presented show a good agreement between simulation results and prototype test results. The small-signal simulations were done with software developed in house for the evaluation of interaction impedance. The commercial code CST suite was used for the prediction of the dispersion diagram. The large-signal simulations were carried out with the “1-D code, computer program for analysis of CC-TWT,” by Cosmic. This paper explains the theory used for the design and shows the “cold test” and “hot test” results achieved with the prototype. The prototype has been able to deliver more than 1.5-kW average output power in a bandwidth larger than 1 GHz. [ABSTRACT FROM AUTHOR]

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node. [ABSTRACT FROM PUBLISHER]

For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or few-layer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. The monolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design. [ABSTRACT FROM AUTHOR]

A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper. [ABSTRACT FROM PUBLISHER]

A comprehensive study of dielectric modulated (DM) drift regions for power devices is presented in this paper. The performance of this structure is theoretically analyzed and compared with both conventional and superjunction (SJ) structures. In this paper, an analytical model for DM drift regions with cylindrical cells is proposed and compared with linear cells. An optimal tradeoff between breakdown voltage (BV) and specific ON-resistance ( R\scriptscriptstyle ON,sp) is obtained by a methodology developed in this paper. 3-D simulations of DM structures with hexagonal cells approximated by cylindrical cells are conducted to verify the analytical model. Optimal BV– R\scriptscriptstyle ON,sp tradeoffs for devices with conventional and SJ drift regions are also obtained through the same methodology and verified by 3-D simulations. Static characteristics of these three different drift region structures in both Si and SiC power devices are compared. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed investigation of the impact of fin width (${w}_{\text {fin}}$) on tri-gate AlGaN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs). As ${w}_{\text {fin}}$ is reduced, the threshold voltage (${V}_{\text {TH}}$) increases, which is due to the enhanced gate control (especially for ${w}_{\text {fin}} < {200}$ nm) thanks to the 3-D geometry of the tri-gate, and the reduced carrier concentration (${N}_{\text {s}}$) caused by a more pronounced strain relaxation and sidewall depletion, as explored using Hall and capacitance–voltage (${C}$ – ${V}$) measurements. Normally- OFF operation was achieved for ${w}_{\text {fin}}$ close to the sidewall depletion width (${w}_{\text {dep}}$) of 19.5 nm, since the fin is depleted from its two sidewalls. The impact of ${w}_{\text {fin}}$ on ON-resistance (${R} _{{{ {6{8} {\text {ON}}}}}}$) and current capability (${I} _{\text {D},\text {max}}$) was also investigated, along with the influence of the effective source injection, the trench conduction and the filling factor (FF) on these key characteristics. The degradation caused by the tri-gate fin etching could be fully recovered by increasing the FF. Finally, we show that the tri-gate can reduce gate capacitance (${C}_{\text {G}}$) and charge (${Q}_{\text {G}}$) in normally- ON MOSHEMTs, depending on the design of the tri-gate and the gate voltage (${V}_{\text {G}}$), leading to a smaller ${R}_{{{ {6{8} {\text {ON}}}}}} \cdot {Q}_{\text {G}}$ product that is beneficial for high-frequency switching applications. The results in this paper offer insights into important phenomena in tri-gate GaN devices and are fundamental for the further advance of this technology. [ABSTRACT FROM AUTHOR]

This paper proposes a robust to defects and short length device (RDSLD), a newly in-plane resonant tunneling diode (RTD), and its ac-modeling with the minimum length of 3 nm. The proposed structure has robust performance in the presence of defects. It also has a high degree of flexibility in tuning electronic specifications. By using bipolar doping and a special h-boron nitride barrier pattern, these unique features are obtained. The simulation results verify that the proposed structure has the potential for replacing conventional RTD diodes. Such that the peak-to-valley ratio (PVR) and the maximum current of 4500, 450 nA for perfect bowtie and 3.45, 1256 nA for rhombic barrier shape structure are obtained, respectively. Also, negative differential resistance (NDR) is observed in all of the structures with vacancy and impurity defects. The effect of the geometrical parameters on the charge transmission of the device is another issue that is addressed in this paper. Furthermore, the analytical and numerical capacitance model parameters are presented. [ABSTRACT FROM AUTHOR]

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond. [ABSTRACT FROM AUTHOR]

Photodetectors (PDs) based on organic–inorganic hybrid materials such as graphene and perovskites have recently emerged at the forefront of the research in optoelectronic devices. Despite the remarkable progress in the performance of optoelectronic devices based on hybrid materials, some aspects such as stability have so far not been thoroughly addressed. This paper serves to demonstrate a fully inkjet-printed PD fabricated by hybrid perovskite (CH3NH3PbClx-3I3) layer between the two graphene electrodes as graphene/perovskite/graphene (GPG) heterostructure. The fully inkjet-printed GPG PD is found to be effective for the visible light region, which can be attributed by the high uniformity and low defects of the printed materials. Thus, the GPG PD achieves a high responsivity of 0.53 A/W. Fully inkjet-printed hybrid perovskite PD demonstrated in this paper unveils the facile, potentially large-scale and cost-effective methods for fabrication of hybrid perovskites-based optoelectronic devices, including PDs and solar cells. [ABSTRACT FROM AUTHOR]