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Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264 and the Chinese AVS, many efficient coding tools have been introduced into MC, such as new motion vector prediction, bi-directional matching, quarter precision interpolation, etc. However, these new features enormously in crease the computational complexity and the memory bandwidth consumption. In this paper, we introduce a novel architecture design of Motion compensation (MC) for multiple video standards including MPEG-2, H.264, and AVS. The proposed design has a macroblock-level pipelined structure which consists of MV Predictor, Cache- based Fetch, and Pixel Interpolation unit. The proposed architecture exploits the parallelism in MC algorithm to accelerate the processing speed and uses the dedicated design to optimize the memory access. MV Predictor unit can cover all MV prediction algorithms for the three standards and provide a simple error concealment scheme. Cache-based Fetch unit can save 25% memory, bandwidth of MC in average and doesn't impact the performance in the worst case. Pixel Interpolation unit adopts fully separate 1-D filtering structure which is designed to effectively avoid the redundant calculations. The architecture can achieve the real-time multiple-standard decoding for HDTV 1080i (1920×1088 4:2:0 6Ofield/s) video. The efficient design can work at the frequency of 148.5MHz and the total gate count for logic circuits is about 56K. [ABSTRACT FROM AUTHOR]

A memory bandwidth efficient architecture for AVS encoder is proposed in this paper. First, simplified ME (Motion Estimation) algorithms are designed to reduce the memory and bandwidth cost. Then a data reuse method with simple control mechanism is proposed to increase the utilization of on-chip memory. The proposed architecture efficiently reduces the bandwidth and memory consumption with acceptable degradation in coding performance. The encoder¹ is implemented with 640 K logic gates in 0.18/μ m² CMOS technology and can satisfy real time encoding of 720×576 4:2:0 25fps AVS video at the working frequency of 108MHz. [ABSTRACT FROM AUTHOR]

In the advanced audio video coding standard (AVS), the motion estimation employs many new techniques such as variable block size, multiple reference frames, motion vector prediction, symmetric searching, etc, for high coding efficiency. However, these techniques are so complex for hardware implementation due to their high data dependence and high computation requirement. In this paper, we firstly improved the AVS motion estimation algorithm from the viewpoint of hardware implementation and secondly propose the architecture for the improved algorithm. This architecture has two 2-D systolic arrays and fully supports the AVS variable block size match. It is able to process forward, backward and symmetric prediction concurrently, and totally produces 27 motion vectors for each macro-block. Experimental results shows that the architecture can achieve 29 fps under the condition of two reference pictures, 65×65 search range and 720×576 picture size. [ABSTRACT FROM AUTHOR]

In this paper, we propose an optimized real- time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with NW/SW partitioning. A VS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32- bit RISC processor. We further propose the optimization of Interface and RISC processor based on the proposed architecture. The A VS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip A VS HDTV real-time decoder. At 148.5MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board. [ABSTRACT FROM AUTHOR]

In this paper, we present a VLSI design of transport processor for an A VS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bus architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18μm CMOS cell library. The circuit costs about 75k equivalent logic gates and the processing capability is up to 90Mbps. [ABSTRACT FROM AUTHOR]

This paper presents a full search motion estimation algorithm with search center prediction for A VS and the VLSI architecture to realize the algorithm. The proposed algorithm achieves comparable performance in coding efficiency with the anchor algorithm, whereas has low storage requirement, low required bandwidth and low complexity for the hardware implementation. The proposed architecture adopts J-D FE Arrays architecture and can perform variable block size motion estimation with 70k logic gates and 24kbits on-chip memory. The architecture achieves best tradeoff in terms of speed and hardware cost. The design can satisfy real-time encoding for A VS high definition application of 1280x720 picture size at 60 fps. [ABSTRACT FROM AUTHOR]

The video part of AVS has been finalized. In order to enhance coding performance, AVS video standard adopts some new features for motion estimation, such as variable block size search, multiple reference frames, and motion vector prediction. However, the better performance comes at the price of high computational complexity, data dependence and memory access requirement. These new features also make the hardware implementation more difficult, especially for real-time applications. In this paper, we firstly propose an integer motion estimation algorithm from hardware-oriented viewpoint. Experimental results show that the proposed algorithm has almost the same performance as the reference software of AVS in SDTV applications. Then the corresponding VLSI architecture is presented. The VLSI architecture has been described in Verilog HDL and synthesized using 0.18pm Artisan CMOS cells library. The circuit totally costs about 400K equivalent logic gates. At 108MHz working frequency, the circuit can meet the real-time requirement for SDTV (720×576, 25fps) applications, with the search area of 192×192. The co-design obtains better tradeoff between performance and gate-count. [ABSTRACT FROM AUTHOR]

In this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-Golomb Code, and AVS 2-D Variable Length Code. Furthermore, it has a pre- processing submodule, which can perform Start Code Detection and De-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18µm Artisan CMOS cells library by Synopsys Design Compiler. The circuit costs about 15k equivalent logic gates (not including 4kb on-chip SRAM). And the critical path is less than 6ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards. [ABSTRACT FROM AUTHOR]

Multi-core Application Specific Instruction Processors (ASIPs) are increasingly used in multimedia applications due to their high performance and programmability. Nonetheless, their efficient use requires extensive modifications to the initial code in order to exploit the features of the underlying architecture. In this paper, through the example of implementing Advance Video Coding (AVS) to a heterogeneous dual-core SIMD processor, we present a guide to developers who wish to perform task-level decomposition of any video decoder in a multi-core SIMD system. Through the process of mapping AVS video decoder to a dual-core SIMD processor we aim to explore the different forms of parallelism inherent in a video application and exploit to speed-up AVS decoding in order to achieve real time functionality. Simulation results showed that the extraction of parallelism at all levels of granularity, especially at the higher levels, can give a total speed-up of more than 195? compared to a software x86-based implementation, which enables realtime, 25fps decoding of D1 video. [ABSTRACT FROM AUTHOR]