An AVS HDTV Video Decoder Architecture Employing Efficient HW/SW Partitioning.

In this paper, we propose an optimized real- time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with NW/SW partitioning. A VS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32- bit RISC processor. We further propose the optimization of Interface and RISC processor based on the proposed architecture. The A VS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip A VS HDTV real-time decoder. At 148.5MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board. [ABSTRACT FROM AUTHOR]