An Efficient VLSI Architecture of VLD for AVS HDTV Decoder.

In this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-Golomb Code, and AVS 2-D Variable Length Code. Furthermore, it has a pre- processing submodule, which can perform Start Code Detection and De-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18µm Artisan CMOS cells library by Synopsys Design Compiler. The circuit costs about 15k equivalent logic gates (not including 4kb on-chip SRAM). And the critical path is less than 6ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards. [ABSTRACT FROM AUTHOR]