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Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

In this paper, a design methodology for SiGe HBT-based low-noise amplifiers (LNAs) is proposed that can be utilized for both sub-1-dB noise figure (NF) and wide bandwidth as an alternative to the conventional simultaneous input noise and power matching technique. This paper focuses on the removal of the series base inductor and the inclusion of an output matching network as a design parameter that can be used to achieve both sub-1dB NF and wide bandwidth. The effects of the mentioned design parameters on NF and bandwidth are described and analyzed, including the comparison of results with the conventional design technique. To demonstrate the validity of the analysis and impact of utilizing base-to-collector capacitance on LNA performance metrics, two different LNAs implemented in a 0.13- $\mu \text{m}$ SiGe technology. The first LNA achieves a lower than 1-dB NF with 26-dB gain at 8.5 GHz, and the second LNA exhibits wideband operation, with a better than 10-dB return losses in the range of 8–35 GHz and lower than 3-dB NF from 6 to 20 GHz. The sub-1-dB LNA reaches −17.3 dBm of input-referred compression point (IP1dB), with a power consumption of 62 mW and an area of 0.795 mm2. The wideband LNA achieves 17.6 dB of peak gain with a 48.5-mW power consumption and 0.69-mm2 chip area. To the best of our knowledge, this paper achieves the best NF performance in the literature utilizing a SiGe technology, while the wideband LNA exhibits the best operational bandwidth, together with a reasonable low-noise performance. [ABSTRACT FROM AUTHOR]

Phase locked loops for fractional frequency synthesis typically use Digital $\Delta \Sigma $ Modulators (DDSMs) as their divider controllers. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of their quantization errors, spur immunity and implementation costs. This paper presents a family of DDSMs that have provably high spur immunity and low folded noise when used in fractional- ${N}$ frequency synthesizers with polynomial nonlinearities. [ABSTRACT FROM AUTHOR]

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove that the fundamental noise invariants under input and output impedance transformations are the eigenvalues of a permuted version of the noise correlation matrix and that there is no feedback operation that preserves them. Known invariants, such as the minimum equivalent noise temperature ${T}_{{N}{min}}$ and ${N}$ , may be expressed in terms of such eigenvalues. In addition, we provide a complete characterization of the four noise parameters of two-port passive dissipative networks in terms of their gain parameters and derive the condition under which the invariant ${4N}{T}_{{0}}{/}{T}_{{N}{min}}$ of passive nonreciprocal networks is lower than two. We also extend the theory of special noise invariants to LNAs with lossy input matching network. Overall, the impact of the findings emerging from the theory is highlighted through theorems, remarks, circuit examples, and studies on widespread design methodologies. [ABSTRACT FROM AUTHOR]

The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for mitigating the effects of the low-frequency noise. In this paper, a novel approach is described, which can also reduce even-order distortion, another major limitation of analog circuits. It may also allow the use of single-ended circuits in applications where usually differential structures are needed. In most cases, the resulting single-ended circuit will be much simpler than the fully or pseudo-differential one. It does not require common-mode feedback circuitry, nor single-ended-to-differential and differential-to-single-ended conversions at the input and output ports. The amplifiers may be single-ended, using, e.g., inverter-based circuits, and the use of baluns can be avoided. The number of pins and pads of the chip can be reduced. In addition, the single-ended opamps of the circuit may require less power than differential ones. These factors and the omission of the common-mode feedback circuits as well as the single-ended/differential converters will usually allow significant power savings. [ABSTRACT FROM AUTHOR]

Computationally-secure cryptographic algorithms implemented on a physical platform leak significant “side-channel” information through their power supplies. Correlational power attack is an efficient power side-channel attack (SCA) technique, which analyzes the statistical correlation between the estimated and the measured supply current traces to extract the secret key. The existing power SCA countermeasures are mainly based on reducing the SNR of the leaked information, power balancing, or gate-level masking, each of which introduces significant power, area or performance overheads, which calls for an efficient generic countermeasure. This paper presents ASNI: Attenuated Signature Noise Injection, which is an energy-efficient generic countermeasure, and shows SCA resistance on the AES-128 encryption as an application. ASNI uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by ${>}200 \times $ in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the ASNI, with the AES-128 core operating at 40 MHz, shows that the system remains secure even after 1 M encryptions, with $\sim 25 \times $ reduction in power overhead compared to that of noise addition alone. [ABSTRACT FROM AUTHOR]

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6 lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard $0.18~\mu \text{m}$ CMOS technology. It achieves transimpedance gain of 68.3dB $\Omega $ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of $0.97~\mu $ Arms. The chip occupies 0.78 mm2 while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC. [ABSTRACT FROM AUTHOR]

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital $\Delta \Sigma $ modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results. [ABSTRACT FROM AUTHOR]

Recent studies on integrated circuits interconnections are mainly concentrated on the analysis of crosstalk and delay, by taking the trade-off between accuracy, speed, and complexity into consideration. The new idea of this paper is to apply the convex optimization method to analyze crosstalk and delay of the lossy coupled interconnections in identical and non-identical forms. For this purpose, a simple and comprehensive model is proposed to cover the functional and dynamic crosstalk in a computationally-effective way. More specifically, various case studies are determined to analyze the transient response of the coupled transmission lines with arbitrary excitation sources in the presence of both capacitive and inductive coupling characteristics. To validate the model, the numerical and Advanced Design System (ADS) simulation results are compared to indicate the desired accuracy. The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively. In addition, the computational speed of the proposed method is about twice higher than ADS and HSPICE. The proposed model is extendible to handle ${N}$ coupled lines, making it appropriate to model complex integrated circuit interconnections. [ABSTRACT FROM AUTHOR]

A new approach to augment existing noise models in a relaxation oscillator by including noise spikes during state change, an important aspect hitherto not covered in existing noise models, is proposed. Such noise spike is due to regeneration at the jump and this paper attempts to offer an explanation by viewing state change as a physical phase change in a thermodynamic system, which is also due to regeneration. The connection is established by viewing the relaxation oscillator as a combination of bistable circuit (exhibits metastablility) and a timing capacitor. Similarly the thermodynamic system exhibits physical phase change (metastability). Formula is derived to predict the “magnitude” of the noise spike, as a function of regeneration parameter, and hence design parameter such as gm, R, {I}_{0}. Simulations (Eldo) on circuits and simulations (Metropolis) on thermodynamic system as well as measurements on circuits fabricated in 0.13 \mu$m CMOS technology are consistent with theory. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a time-interleaved RF carrier modulation and demodulation technique, suitable for high frequency mixer applications under a constraint of active device speed limitation. The presents are in essence mixer arrays where modulated outputs by a series of time-delayed carriers with a reduced frequency, compared with a carrier frequency in fundamental mixers, will be interleaved in the time domain to synthesize the final output. The mixer arrays inherit an FIR filtering function, and the time interleaving process is equivalent to the filtering process where the arrays select the fundamental tone or its harmonics of a carrier in a periodic manner. The carrier waveform and duty-cycle play important roles in the noise performance of the mixer arrays. A comprehensive noise analysis is presented in this paper for both cases of correlated-noise and uncorrelated-noise mixer arrays. To minimize output noise power, optimization of carrier duty-cycle and noise filtering technique have been proposed and analyzed extensively for various types of carrier pulse. Finally analytical mismatch models are provided and output SNR degradations under finite mismatches amongst mixer array elements have been discussed based on the mismatch models. All theoretical analyses are verified through behavioral mixer array simulations including Monte-Carlo statistical simulations. [ABSTRACT FROM AUTHOR]

The paper introduces a new concept of a true random number generator (TRNG). Most metastability-based solutions operate on the uncertainty of a logical output state of a device (flip-flop, D-latch) aimed to be resolved from an exact metastable point. However, it has been shown that the metastable point of a bistable circuit (which is practically impossible to reach) does not guarantee absolute randomness or sufficient entropy. We propose the concept of a device in which the direct proximity of the metastable point is not mandatory. In our concept the transition times of two devices are compared. Such construction is less sensitive to the proximity of the metastable point, temperature fluctuations, and power supply instabilities. The paper briefly describes the metastability phenomena in general and other known metastability-based TRNG concepts. A new concept of a dual-metastability time-competitive generator is presented, analyzed both numerically and theoretically, and verified based on the sample circuit's implementation. Empirical and statistical test results are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a low-temperature coefficient (TC), noise, and offset bandgap reference (BGR) for the high precision applications. In order to reduce the offset voltage and noise introduced by the error amplifier, the offset and noise suppression technique is proposed. A five-piece linear compensation has been applied in the BGR to improve the TC performance. Moreover, an adaptive current loop is added to the bandgap reference to enhance the current driving capability. The proposed BGR is implemented in a $0.35~\mu \text{m}$ standard CMOS process occupying an active area of $0.22 \times 0.28$ mm2. The measured results show that the average TC is 3 ppm/°C −45 °C to 125 °C after trimming. The output reference voltage of 2.47 V can achieve $3.6~\mu \text{V}$ (rms) noise from 0.1 to 10 Hz. In the supply voltage range of 2.6 to 5 V, the proposed BGR can deliver $30~\mu \text{A}$ load current and its PSRR is about −83 dB @ 100Hz. [ABSTRACT FROM AUTHOR]

In this paper, we will present an all-CMOS oscillator based on monolithically integrated MEMS resonators fabricated from the VIA layer (tungsten) of a 0.35~\mu \textm CMOS technology process. With this CMOS MEMS closed-loop system, the nonlinear MEMS frequency response due to the electrostatic actuation has been reconstructed. Using a phase-controlled closed-loop the frequency stability of the self-sustained oscillator at different nonlinear operation points has been analyzed, showing an optimal point belonging to the unstable region of the MEMS resonator. [ABSTRACT FROM AUTHOR]

The common mode (CM) current in differential circuits generates CM noise which radiates in the environment and causes electromagnetic interference (EMI) with electronic devices in proximity. This noise is generated due to imbalance in the charging and discharging paths of the driver circuit and asymmetric equalization. A systematic study of how asymmetric equalizer increase the CM noise is still lacking. Few active on-chip solutions are proposed for wireline transmitters up to 20-Gbps speed. However, these solution does not suppress CM noise by the equalizer and they could not support four-level pulse amplitude modulation (PAM-4) optical transmitters. This paper analyzes two potential sources of EMI-related CM noise, the common mode logic (CML) driver and feed forward equalization (FFE) circuit, and presents a novel on-chip active circuit technique for automatic CM noise cancellation in high-speed PAM-4 transmitter. This solution provides the benefits of small size and low cost by eliminating the need for discrete components to suppress EMI. The post-layout simulation demonstrates that the CM noise cancellation circuit (CMNC) efficiently mitigate the EMI by suppressing the CM noise up to 90% and consumes 5 mW, with core area of $17 \mu m \times 9 \mu m$. [ABSTRACT FROM AUTHOR]

It is well known that multi-agent systems (MASs) are ubiquitous in natural and artificial systems. This paper aims at bridging the gap between transmission noise and sampled data for robust consensus of MASs. In detail, we have developed a theoretical framework for analyzing the robust consensus of MASs with sampled-data controllers and transmission noises. Using the delay-input and discretization approaches, we obtain two sufficient conditions on the existence of sampling periods and controller parameters for robust consensus of MASs, respectively. In particular, we deduce the estimates of the convergence speeds of consensus errors for the above two methods. Finally, numerical simulations are also given to validate our theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents the design of a continuous-time \Delta\Sigma modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm^2 and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]

This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 \mum CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 \muW, which corresponds to a figure-of-merit of 0.85 pJ/conv. [ABSTRACT FROM AUTHOR]

This paper presents a low-power compact analog circuit for processing time varying signals. The proposed circuit implements temporal differentiation, amplification and rectification, i.e., separation of outputs into on and off pathways. It is based on a hysteretic differentiator circuit, commonly used in neuromorphic vision sensors to implement temporal edge detection. This paper presents a thorough analysis of the original circuit and identifies the source of the problems and limitations it has for processing real-world sensory signals. The steps required to solve this problem are presented as well as an extended circuit with tunable gain and adaptable threshold that allows thresholding of small temporal changes (noise) and high-pass filtering of large temporal changes. The new circuit proposed is particularly suited for focal plane implementation of both gradient based and token based motion algorithms that require robust detection of temporal discontinuities. The circuit has been designed and successfully integrated into a 64 × 1 test prototype motion chip, fabricated in standard 350 nm CMOS technology. The paper provides extensive experimental characterization results. [ABSTRACT FROM PUBLISHER]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper is concerned with the almost sure exponential synchronization of a multilayer network which is set up on a non-strongly connected digraph that can be classified into several layers by Tarjan’s algorithm. Note that, in the multilayer network, white-noise-based time-varying coupling and drift term coupling are proposed to simulate two kinds of coexisting distinguishable interactions between vertices. We develop a normal analytical framework for studying synchronization of the multilayer network. Firstly, via aperiodically intermittent pinning noises, synchronization of vertices situated on the first layer is achieved in the layered network. Secondly, under the impact of the white-noise-based time-varying coupling in diffusion term, synchronization of the vertices located in other layer networks is developed with the support of synchronization for the pinned vertices. Employing Lyapunov method, graph theory and stochastic analysis technique, a criterion of almost sure global exponential synchronization is obtained. By adopting the concepts of average noise control rate and average noise control period proposed recently, we lessen the conservativeness of the conditions restricted on aperiodically intermittent noise control to optimize our results. Furthermore, an application to a class of Chua’s circuits is exhibited in detail. In the end, we provide a numerical example to verify the validity of the theoretical results. [ABSTRACT FROM AUTHOR]

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given. [ABSTRACT FROM AUTHOR]

Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant inter-symbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end’s first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design tradeoffs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise. [ABSTRACT FROM AUTHOR]

Variability is one of the major challenges for CMOS in the nano era. Manufacturers test each circuit sample to ensure that samples that do not meet the desired specification are discarded. However, testing is only effective for variability, which is observable right after manufacturing, such as geometric variations, work function, and random dopant fluctuation. This is in contrast to time-dependent variability (TDV), i.e., differences in the defects of transistors, which is not macroscopically observable immediately after manufacturing. In fact, defects are electrically neutral until they capture a carrier [with mechanisms called bias temperature instability (BTI) and random telegraph noise (RTN)] and thus become observable through their induced degradation. Therefore, transistors which are characterized identically after manufacturing will drift apart during their lifetime, as their susceptibility to effects such as BTI and RTN is different. In this paper, we model for the first time TDV from a defect-centric physical perspective all the way to the circuit level. Our novel defect-centric transistor reliability specification provides a fast, yet accurate method to estimate an upper bound for TDV on the transistor level, while our novel worst cell (WCL) and worst value (WVL) libraries allow for fast evaluation of the impact of TDV on the timing of circuits. Our approach is fully compatible with existing EDA tool flows, allowing us to model and optimize complex circuits like full microprocessors. By evaluating the impact of TDV with our reliability specification and variability-aware cell libraries, we are able to model TDV, which allowed us to reduce the required defect variability guardband by 46%. In addition, we provide design optimization strategies on each abstraction level such as limiting continuous stress, transistor hardening, and implement a novel variability-aware synthesis to achieve up to 57% additional guardband reduction. [ABSTRACT FROM AUTHOR]

In previous work, generally, stochastic delayed coupled systems were considered on a network with a single weight. However, stochastic delayed coupled systems on a network with multi-weights have not been fully investigated and remain to be important and challenging. Hence, in this paper, time delays and Lévy noise are taken into account in stochastic coupled systems on a network with multi-weights. Furthermore, synchronization of stochastic delayed coupled systems with Lévy noise on a network with multi-weights (SDCSLM) is first studied via aperiodically intermittent control. Then, by means of the Lyapunov method, graph theory and some techniques of inequalities, some sufficient conditions for $p$ th moment exponential synchronization of SDCSLM are obtained. Particularly, as a practical application of the theoretical results, the exponential synchronization in mean square of stochastic Chua’s circuits with time delays and Lévy noise on a network with multi-weights is studied in detail. Finally, some numerical simulations are given to show the effectiveness of the theoretical results. [ABSTRACT FROM AUTHOR]

Accurately resolving small fluorescence power variations in presence of noise and high-background tissue autofluorescence from deep brain structures with a fiber photometry system requires highly linear and sensitive photo detectors. This paper presents a high-dynamic range (DR) CMOS biosensor fusing a low-noise photosensing front-end with a high-precision extended counting analog-to-digital converter (ADC) with noise cancellation to detect florescence neural signal fluctuations of very low incident power. The 7 MSBs are resolved by a first order continuous-time resettable $\Sigma \Delta $ ADC, whereas the residue voltage is quantized by a 10-bit single slope ADC for enabling wide-dynamic range and high-precision fluorescence sensing. The reset noise is canceled out by an embedded noise cancellation scheme which is subtracting the reset noise from the signal using a correlated double sampling scheme. Unlike other solutions, the biosensor has a short conversion time of $306.5~\mu \text{s}$ compared to a typical fluoresence sampling period of 10 ms, providing a very low duty cyle of 3%, which is a key to achieve low excitation source power consumption in this application to extend system autonomy, and to avoid photobleaching and phototoxicity in the tissue. The proposed optoelectronic biosensor is implemented in a 0.18- $\mu \text{m}$ CMOS technology, consuming $93~\mu \text{W}$ from a 3.3-V supply voltage while achieving a DR of 104 dB, a minimum detectable current of $1.3~\text {pA}_{\mathrm{ rms}}$ , and a chip area of 0.475 mm2. We present the measured performance of the biosensor using an optical experimental setup including a LED driver, a fiber optic, and a test board. [ABSTRACT FROM AUTHOR]

This paper deals with the $H_{\infty }$ fault detection (FD) problem for a class of buck converter with the transmission-induced multiplicative noises and the event-triggered scheme under the network environment. The model of buck converter is approximated by a nonlinear model, and it is further analyzed based on the electricity knowledge. Due to the dynamic characteristics of network transmission, multiplicative noises need to be considered, which are described as a product of some uncorrelated standardized normal distribution and the transmitted signal. Meanwhile, an event-triggered mechanism is utilized for the purpose of reducing the energy consumption, and an FD observer is designed to detect the fault presented in buck converter. Some novel sufficient conditions are given in terms of linear matrix inequalities to guarantee the robust stability of the FD system, and the $H_{\infty }$ optimal fault tracking performance index is also achieved. Finally, an illustrative example is provided to show the validity and merit of the proposed method. [ABSTRACT FROM AUTHOR]

Perimeter-gated single-photon avalanche diodes (PGSPADs) have been shown to mitigate premature edge breakdown without unduly increasing the area of the device. PGSPADs are three terminal devices. In this paper, we develop a probability-based SPICE model for the PGSPAD and fully characterize an $18 \times 18$ pixel analog PGSPAD-based CMOS silicon photomultiplier (SiPM). The noise model is derived using theories of carrier thermal generation, carrier diffusion, and inter-band tunneling. Parameters are derived using fabricated PGSPAD devices and model validity is verified with experimental measurements. The designed PGSPAD SiPM is implemented in standard $0.5~\mu \text{m}$ 2-poly, 3-metal CMOS process, and is characterized for dark current, sensitivity, and signal-to-noise ratio (SNR) throughout the visible spectral range for varying bias voltages. Models show that the reduction of dark events in the PGPSAD is primarily caused by a reduction in band-to-band tunneling. Thus, as a function of the applied gate voltage the PGPSAD shows an improvement of SNR over a range of 1 to 1150. The sensitivity of the presented SiPM is $1.06 \times 10^{3}$ A/W/cm2. The designed PGSPAD SiPM shows great promise over standard SiPM for applications, such as neutron detection which requires high sensitivities and high SNRs. [ABSTRACT FROM AUTHOR]

In this paper, a built-in self-test and in situ analog circuit optimization platform is proposed and characterized. By integrating a fully digital optimization engine and self-test circuits along with circuits-under-optimization (CUO), this platform can automatically find an operating point that makes a good balance among multiple competing characteristic goals. Therefore, the arbitrary linear time-invariant CUO can be optimized even when there are large process-voltage-temperature variations and aging effects of devices. This platform is analyzed to determine the required accuracy of its building blocks in terms of noise and linearity. The feasibility of this platform is proved by a case study utilizing a Tow-Thomas bandpass biquad. [ABSTRACT FROM AUTHOR]

A transimpedance amplifier (TIA) in the front-end of a radiation detector is required to convert the current pulse produced by a light-detector to a voltage pulse with amplitude and shape suitable for the subsequent processing. We consider in this paper the specifications of a positron emission tomography (PET) scanner for medical imaging. [ABSTRACT FROM AUTHOR]

This paper exploits the predominance of embedded memories in current and emerging wireless transceivers as a means to save power via channel state aware voltage scaling. The paper presents a statistical model that captures errors in embedded memories due to voltage over-scaling and maps the errors to a Gaussian distribution that represents a combination of communication channel noise and hardware noise. Designers can use the proposed model to investigate different power management policies, that capture the performance of the system as a function of both channel and hardware dynamics, thus creating a much richer design space of power, performance and reliability. A case study of a DVB receiver is presented and the validity of the proposed model is confirmed by simulations. [ABSTRACT FROM AUTHOR]

In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5–14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 mm^2. Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices. [ABSTRACT FROM PUBLISHER]

Comparator power consumption is a major bottleneck to the power efficiency of a high resolution successive approximation register (SAR) analog-to-digital converter (ADC) used in low-power applications. This paper analyzes theoretically the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels. A simple and accurate mathematical model of the SAR ADC that is amenable to analysis is first presented. The mathematical formulation suggests that the comparison power allocated to each bit step need not be the same. The optimization problem, therefore, is solved so that the comparator power budget is optimally distributed among all bit steps. Simulation results show that up to 50% and 60% power savings can be achieved when 10 and 12 comparators are employed for 10 b and 12 b SAR ADCs, respectively. To reduce the implementation complexity, comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators is sufficient to achieve near ideal performance in 10 b and 12 b SAR ADCs. [ABSTRACT FROM AUTHOR]

This paper presents a new concept of multirate cascade ΣΔ modulators, in which the signal is downsampled across the cascade instead of being upsampled as done in conventional multirate architectures. This strategy is suited for hybrid continuous-time/discrete-time cascade ΣΔ modulators, where only the front-end stage is implemented by continuous-time circuits, and the remaining back-end stages are realized using switched-capacitor circuits. The main drawback of this approach comes from the implicit aliasing error signal due to the downsampling process. However, as shown in this paper, this error can be completely canceled in the digital domain, with no additional analog hardware required. The combination of these features results in a new class of ΣΔ modulators, which are potentially faster and more power efficient than conventional multirate architectures and more robust against circuit element tolerances than cascade single-rate continuous-time implementations for wideband applications. [ABSTRACT FROM AUTHOR]

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-μm CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected. [ABSTRACT FROM AUTHOR]

This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax the generation, division, and distribution of the local oscillator signal are reviewed. Last, integration issues for transmit and receive paths and for multiple beamforming transceivers are addressed. [ABSTRACT FROM AUTHOR]

Previous studies have shown that impulsive noise can weaken the performance of power line communication (PLC). Though DCSK can improve the performance in an order of magnitude comparing to the direct sequence differential phase shift keying (DS-DPSK), it is still a challenge to further improve the BER performance with signal redesign without the need of advanced and expensive extra noise suppression technologies. The paper introduces the model of asynchronous impulsive noise of Middleton class-A noise and corresponding multipath fading channels in PLC, and analyzes the bit error rate (BER) performance of the $M$ -ary differential chaos shift keying (MDCSK) scheme over different channels. Furthermore, a new replica piecewise frame of MDCSK (RP-MDCSK) is proposed to resist the impulse noise. In the proposed scheme, one piecewise of signals is transmitted first. Then, it replicates $pw$ times, which serves as the reference signal transmitted in the first half symbol period. The information-bearing signal combines the reference signal with its Hilbert transform in the second half. At the receiver, one piece of reference signals is extracted and then correlated with its corresponding information-bearing part. The BER expressions of the MDCSK and the proposed scheme are derived and analyzed over different channels, and verified by simulations. Comparing with the corresponding schemes, it is found that the BER of the proposed scheme is by 2–3 orders of magnitude lower. [ABSTRACT FROM AUTHOR]

This paper presents a noise suppression method to improve noise figure (NF) performance of a distributed amplifier (DA) in a broad frequency range. In the proposed DA topology, the input matching resistor, which remarkably increases the NF, is replaced by a common-gate (CG) stage. The noise contribution of the CG terminating network is suppressed by employing a cell weighting plan in conjunction with a gate-inductive peaking technique. Analytical methods and a circuit implementation in a $0.18~\mu \text{m}$ CMOS technology verify that the proposed noise suppression technique provides lower NF compared with the conventional DA (CDA) topology in the entire frequency range. This is in contrast to other reported low-noise DA topologies which decrease the noise contribution of the input matching element only in a limited range of frequencies. The measurement results demonstrate an average gain of 9.5 dB in 1-20 GHz frequency range, a noise figure less than 4 dB and 5.8 dB up to 16 GHz and 20 GHz, respectively, and an average IIP3 of 5.3 dBm. The chip occupies an area of 1.2 mm2, including pads, and consumes a current of 24 mA from 1.8 V supply. [ABSTRACT FROM AUTHOR]

This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to $3.1\times $ and $5.7\times $ for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of $15.1~\mu \text{W}$ for high background noise and $10.8~\mu \text{W}$ for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about $1.7\times $ reduced), while maintaining high system capability and adaptability. [ABSTRACT FROM AUTHOR]

The transformer-based input integrated matching allows the realization of the simultaneous optimum noise and maximum power transfer input impedance matching in cascode amplifiers by exploiting the mutual coupling between the two spirals of an integrated transformer. This technique has been adopted to design LNAs operating in the microwave and millimeter-wave frequency ranges; however, the analytical proofs are still missing. This paper addresses for the first time a complete and in-depth study of the circuit topology and design technique in order to provide the analytical proofs. In-depth analyses are also used to get useful circuit insights, derive effective design equations, and carry out a direct comparison with the most widespread cascode low-noise amplifier with inductive degeneration through circuit design under the same conditions. [ABSTRACT FROM PUBLISHER]

A Cartesian error feedback architecture is proposed to address the linearity-noise tradeoff in the conventional Cartesian feedback architecture. First, the tradeoff in the conventional Cartesian feedback architecture is identified, which is caused by the contradictory requirements imposed by linearity and noise on the attenuation ratio in the feedback path. Then, this paper investigates how the signal cancellation provided by the new architecture mitigates the tradeoff. The effects of nonlinearities and noise from the feedforward path are also presented in detail. Furthermore, the matching requirements of the feedforward path for effective signal cancellation are discussed and proven not stringent due to the loop effect. To verify the concept, a WCDMA signal is taken as the application example, in which our proposed error feedback architecture presents more than 8 dB noise improvement while maintaining comparable linearity performance compared with the conventional architecture. This validates the deployment of the proposed Cartesian error feedback architecture in today’s application scenarios with congested frequency spectrum. [ABSTRACT FROM AUTHOR]

This paper presents an analog baseband beamforming topology, which combines phase shifting, signal combination, and biquadratic lowpass filtering in one block. This reduces the number of stages cascaded in a receiver chain, leading to a shorter signal path, thus improving the dynamic range. Flexibility of the proposed solution is illustrated with different possible implementations depending on the top-level chip floorplan. It is shown that the proposed structure does not introduce extra power consumption compared to the conventional approach, while obtaining a higher SNR. A four-antenna-path version of the proposed topology is implemented in 40 nm low-power CMOS as a prototype together with a variable gain block forming a complete analog baseband section for a phased-array receiver. The functionality includes beamforming with a resolution better than 6.8 degrees, fourth-order lowpass filtering with a 1 GHz cutoff frequency, variable gain between 10.6 and 30 dB and automatic DC offset compensation. Output IP3 above 10 dBm and output noise below 4.2 mVrms over the whole gain range yield an SFDR larger than 31.2 dB, which is sufficient for 16-QAM modulation according to IEEE 802.11ad. The circuit consumes between 30 and 42 mW. [ABSTRACT FROM AUTHOR]

This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 \mum CMOS image sensor process with a pixel array that has an image format of 648 \times 488 and a pixel size of 5.6\ \mum\times 5.6\ \mum. The measured results show a random noise of 108 \muV, a dynamic range of 60.9 dB, a differential nonlinearity of +1.02/-0.34 least significant bit (LSB), and an integral nonlinearity of +0.64/-0.54 LSB. [ABSTRACT FROM AUTHOR]

This paper presents a loop gain optimization technique for integer-N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement. [ABSTRACT FROM AUTHOR]

A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18-\mum CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 \muW and 50 \muT, respectively. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 \muW from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper deals with the joint optimization problem of high-order error-feedback and realization for minimizing roundoff noise at the output of a closed-loop system with a full-order observer feedback system subject to l2-scaling constraints. It is shown that the problem can be converted into an unconstrained optimization problem by using linear-algebraic techniques. The unconstrained optimization problem at hand is then solved iteratively by employing an efficient quasi-Newton algorithm with closed-form formulas for key gradient evaluation. A case study is presented to demonstrate the validity and effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure. [ABSTRACT FROM AUTHOR]