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In this article, we propose a CMOS active balun targeting high linearity up to high voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of this active balun are derived using a common highly linear building block (HLBB). The HLBB is designed using an inverter with strong source degeneration. To increase the linearity of this HLBB further, its nonlinearity mechanisms are analyzed in detail. A bootstrapping technique is included in the HLBB to reduce the dominant nonlinearity. Furthermore, a pre-distortion technique cancels most of the non-linearity of the output driving stages. All the linearization techniques proposed are robust to process, voltage, and temperature (PVT) changes. The measured results of the active balun realized on-chip in a 22-nm FDSOI CMOS shows $ < -$ 44-dBc third harmonic distortion (HD3) up to 1.5- $\text{V}_{\textrm {p-p}}$ output swing over 0.01–5.4 GHz. The measured gain and phase errors of the balun action are less than 0.5 dB and $\pm 5{^\circ }$ , respectively. The chip is powered from a 5-V supply and dissipates 925 mW. [ABSTRACT FROM AUTHOR]

A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar applications is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/ $\mu \text{s}$ sawtooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth. [ABSTRACT FROM AUTHOR]

This paper describes a 23-GHz digital bang–bang phase-locked loop (PLL) fabricated in 65-nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with respect to the more conventional triangular waveform. Such a signal, however, features a very large bandwidth that requires the adoption of a two-point injection scheme. This paper, after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the accuracy of frequency modulation, presents a novel automatic pre-distortion engine, operating fully in background, which linearizes the tuning characteristic. The 19.7-mA fractional-N PLL having an rms jitter of 213 fs and an in-band fractional spur of −58 dBc is capable of synthesizing fast chirps with 173-MHz/ $\mu \text{s}$ maximum slope and an idle time of less than 200 ns after an abrupt frequency step with no over or undershoot. [ABSTRACT FROM AUTHOR]

A digital polar transmitter is introduced using 9-b thermometer-coded uniform cells for wideband signal. By analyzing amplitude and phase paths impairment which causes both in-band and out-of-band distortions, a 960-MHz delay tuner is designed for precise amplitude and phase alignment. Furthermore, two digital pre-distortion algorithms for digital power amplifier (DPA) are implemented and compared. Importantly, an on-chip dc–dc converter is included for direct battery connection and output power control. Boosted cascode gate bias improves PA efficiency at low power region. The proposed design is fabricated using a 55-nm RF CMOS technology. This DPA including digital amplitude modulation (AM) filtering achieves peak power of +21.9 dBm with 41% drain efficiency in continuous-wave measurements. It achieves EVM of 2.9% with 20-MHz IEEE 802.11ac compliance of 256-QAM OFDM signal, and also achieves EVM of 4.5% (CC0)/4.8% (CC1) with 40-MHz LTE-A carrier aggregation compliance of 64-QAM OFDM signal. [ABSTRACT FROM AUTHOR]

This paper deals with the system and circuit-level aspects of an ultra-low-power robust wireless node for an asymmetric wireless link. A single building block TX front-end for a frequency hopping spread spectrum (FHSS) transmitter implemented in silicon-on-anything (SOA) bipolar technology is presented. It is realized with a directly modulated RF cascoded Colpitts power voltage-controlled oscillator (VCO), a frequency locked loop for center frequency calibration, and a digital pre-distortion algorithm for accurate frequency bins synthesis. The TX front-end draws only 1 mA at -18 dBm output power. By combining digital system techniques for frequency hopping and merging the VCO and the power amplifier (PA), a robust solution is obtained for indoor ultra-low-power wireless links. The proposed pre-distortion concept allows reduction of the hardware complexity, while the combination of a cascode output buffer and a common-collector Colpitts VCO allows us to reduce the complete FHSS front-end to a single building block that directly drives the antenna through a balun. A dedicated digital algorithm on the receiver side reduces the center frequency offset from a maximum value of 8.2 MHz to less than 8 ppm avoiding the use of any crystal on the transmitter side. Precision in the hopping synthesis is obtained by employing a ST-DFT based demodulator with differential encoding and an offset sending technique. The novel FHSS-predistortion concept has been verified by realizing a full wireless link that achieves a bit error rate better than 1.1% at -25 dBm output power while transmitting across an 8 meters indoor non-line-of-sight (NLOS) path. [ABSTRACT FROM AUTHOR]