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Computing-in-memory (CIM) based on SRAM is a promising approach to achieving energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices; however, existing SRAM-CIM chips support only DNN inference. The flow of training data requires that CIM arrays perform convolutional computation using transposed weight matrices. This article presents a two-way transpose (TWT) multiply cell with high resistance to process variation and a novel read scheme that uses input-aware zone prediction of maximum partial MAC values to enhance the signal margin for robust readout. A 28-nm 64-kb TWT CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved ${T_{AC}}$ of 3.8-21 ns and energy efficiency of 7-61.1 TOPS/W in performing MAC operations using 2-8-b inputs, 4-8-b weights, and 10-20-b outputs.

Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply-and-accumulate (MAC)-friendly structure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwithstanding the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active-feedback-based voltage-sensing read (RD) to enable 1-8-b programmable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1-8-b inputs and weights and 20-b outputs without quantization.

This article presents a computing-in-memory (CIM) structure aimed at improving the energy efficiency of edge devices running multi-bit multiply-and-accumulate (MAC) operations. The proposed scheme includes a 6T SRAM-based CIM (SRAM-CIM) macro capable of: 1) weight-bitwise MAC (WbwMAC) operations to expand the sensing margin and improve the readout accuracy for high-precision MAC operations; 2) a compact 6T local computing cell to perform multiplication with suppressed sensitivity to process variation; 3) an algorithm-adaptive low MAC-aware readout scheme to improve energy efficiency; 4) a bitline header selection scheme to enlarge signal margin; and 5) a small-offset margin-enhanced sense amplifier for robust read operations against process variation. A fabricated 28-nm 64-kb SRAM-CIM macro achieved access times of 4.1–8.4 ns with energy efficiency of 11.5–68.4 TOPS/W, while performing MAC operations with 4- or 8-b input and weight precision.

This article presents a low-power, high-speed smart vision sensor for motion detection (MD) that realizes in-pixel frame-difference (FD) operation using a global shutter mechanism. A ping-pong pulse-width-modulation (PWM) pixel is proposed to achieve the consecutive event frame report with a balanced signal transfer function of successive FD operations. Three operating modes were implemented for varied application scenarios, such as image capture (IC) mode to capture a raw image, FD mode for MD, and saliency detection (SD) mode for low-resolution sub-block event counting. A 0.8 V 64 $\times $ 64 vision sensor prototype was fabricated and verified in TSMC 0.18- $\mu \text{m}$ standard CMOS technology. In IC mode, it consumed 71.2 $\mu \text{W}$ @360fps with an achieved iFoM of 48.3 $\text {pJ/pixel}\cdot \text {frame}$ . In FD mode, it consumed 74.4 $\mu \text{W}$ @510fps with full-resolution (64 $\times $ 64) event reporting and achieved iFoMs of 35.6 $\text {pJ/pixel}\cdot \text {frame}$ . In SD mode, it consumed 121.6 $\mu \text{W}$ @890fps with block-level (8 $\times $ 8) saliency reporting and achieved iFoMs of 2.1 $\text {nJ/block}\cdot \text {frame}$ .

The emerging edge intelligence requires low-cost energy-efficient neural network (NN) processors. Supporting various types of edge NN models leads to extra circuit overhead. Designing a unified NN processor with high energy/area efficiency is challenging. This work presents a frequency-domain-accelerated unified NN processor, named STICKER-T. It combines algorithm, architecture, and circuit-level optimization to achieve high energy/area efficiency. By utilizing the block-circulant NN (CirCNN) algorithm, this work supports frequency-domain acceleration and a unified workflow for convolutional, fully connected, and recurrent NN (CNN/FC/RNN). Three key innovations are proposed. First, a block-circulant-accelerated chip architecture is implemented to support unified CNN/FC/RNN workflow. Second, a multi-bit 8-128-point global-parallel local-bit-serial fast Fourier transform (FFT) module is designed for efficient high-throughput FFT/inverse FFT (IFFT) operation. Third, by utilizing a 6T hierarchical-bitline-switching transpose-SRAM (HBST-TRAM), 2-D data reuse is enabled in the proposed multi-bit frequency-domain multiply–accumulate (MAC) array. STICKER-T was fabricated in a 65-nm CMOS technology. It can operate at 0.54–1.15 V and 25–200 MHz with 13.3–339-mW power consumption. The peak energy efficiency achieves 140.3 TOPS/W. It shows 8.1 $\times $ area efficiency and 4.2 $\times $ energy efficiency at 4-bit precision compared with the state-of-the-art reconfigurable NN processor.

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF’s reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 $\times $ 10−6 and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

As the growing demand on artificial intelligence (AI) Internet-of-Things (IoT) devices, smart vision sensors with energy-efficient computing capability are required. This article presents a low-power and low-voltage dual mode 0.5-V computational CMOS image sensor (C2IS) with array-parallel computing capability for feature extraction using convolution. In the feature extraction mode, by applying the pulsewidth modulation (PWM) pixel and switch-current integration (SCI) circuit, the in-sensor eight-directional matrix-parallel multiply–accumulate (MAC) operation is realized. Furthermore, the analog-domain convolution-on-readout (COR) operation, the programmable $3\times3$ kernel with ±3-bit weights, and the tunable-resolution column-parallel analog-to-digital converter (ADC) (1–8 bit) are implemented to achieve the real-time feature extraction without using additional memory and sacrificing frame rate. In the image capturing mode, the sensor provides the linear-response 8-bit raw image data. The C2IS prototype has been fabricated in the TSMC 0.18- $\mu \text{m}$ standard process technology and verified to demonstrate the raw and feature images at 480 frames/s with a power consumption of 77/ $117~\mu \text{W}$ and the resultant FoM of 9.8/14.8 pJ/pixel/frame, respectively. The prototype sensor is used as a real-time edge feature detection frond-end camera and accompanied with a simplified convolutional neural network (CNN) architecture to demonstrate the hand gesture recognition. The prototype system achieves more than 95% validation accuracy.

Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high-precision operations, large cell array area overhead, and limited compatibility with many input and weight configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing multibit PS accumulation to increase read accuracy and reduce area overhead; 2) column-based place-value-grouped weight mapping and a serial-bit input (SBIN) mapping scheme to facilitate reconfiguration and increase array efficiency under various input and weight configurations; 3) a self-reference multilevel reader (SRMLR) to reduce read-out energy and achieve a sensing margin 2 $\times $ that of the mid-point reference scheme; and 4) an input-aware bitline voltage compensation scheme to ensure successful read operations across various input-weight patterns. A 4-Kb configurable 6T-SRAM CIM unit-macro was fabricated using a 55-nm CMOS process with foundry 6T-SRAM cells. The resulting macro achieved access times of 3.5 ns per cycle (pipeline) and energy efficiency of 0.6–40.2 TOPS/W under binary to 8-b input/8-b weight precision.

Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area-latency-energy tradeoff for multibit MAC operations, pattern-dependent degradation in signal margin, and small read margin. To overcome these challenges, this article proposes the following: 1) a serial-input non-weighted product (SINWP) structure; 2) a down-scaling weighted current translator (DSWCT) and positive–negative current-subtractor (PN-ISUB); 3) a current-aware bitline clamper (CABLC) scheme; and 4) a triple-margin small-offset current-mode sense amplifier (TMCSA). A 55-nm 1-Mb ReRAM-CIM macro was fabricated to demonstrate the MAC operation of 2-b-input, 3-b-weight with 4-b-out. This nvCIM macro achieved $T_{\text {MAC}}= 14.6$ ns at 4-b-out with peak energy efficiency of 53.17 TOPS/W.

Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 $\times $ 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output.

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2019 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 17–21, 2019, in San Francisco, CA, USA. This Special Issue covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), and Memory Committees.

Many cost-aware IoE devices require embedded nonvolatile memory (eNVM) to achieve high-speed read and low-power write operations for serving as code and data storage unit. Resistive random access memory (ReRAM) is a good candidate for eNVM of Internet-of-Everything (IoE) but suffers low read yield and require long read latency ( $T_{\text {CD}}$ ) against small $R$ -ratio, large cell-resistance variations, and device-mismatch induced input offset at current-mode sense amplifier (CSA). The wide distribution in write time also causes large wasted write power ( $E_{\text {W}}$ ) and long NVM-stress-time ( $T_{\text {STRS}}$ ). This paper proposes a bitline-current-aware small-offset CSA, using dynamic trip-point-mismatch sampling (DTPMS) scheme, to improve read yield and shorten $T_{\text {CD}}$ . This paper also proposes a low dc-current voltage-mode write termination (LDC-VWT) module, including SET and RESET termination circuits, to suppress $E_{\text {W}}$ and $T_{\text {STRS}}$ . A fabricated 65-nm 2-Mb ReRAM macro achieved $T_{\text {CD}}= 2.6$ ns and confirm the write-termination operations for reduction in $T_{\text {STRS}}$ and $E_{\text {W}}$ .

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as “normally off” applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6 $\times $ and >6000 $\times $ higher speed and energy efficiency of restore and >4 $\times $ faster operating frequency compared with that of state of the art.